CN115541955A - Oscilloscope for realizing analog triggering - Google Patents
Oscilloscope for realizing analog triggering Download PDFInfo
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- CN115541955A CN115541955A CN202211522766.7A CN202211522766A CN115541955A CN 115541955 A CN115541955 A CN 115541955A CN 202211522766 A CN202211522766 A CN 202211522766A CN 115541955 A CN115541955 A CN 115541955A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R13/00—Arrangements for displaying electric variables or waveforms
- G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
- G01R13/0218—Circuits therefor
- G01R13/0254—Circuits therefor for triggering, synchronisation
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/027—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
- G01R29/0276—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values the pulse characteristic being rise time
Abstract
The invention relates to an oscilloscope for realizing analog triggering, wherein a triggering module in the oscilloscope comprises a triggering pulse expansion circuit and a digital TDC circuit, the triggering pulse expansion circuit is used for converting an analog triggering signal into a triggering pulse signal, and the pulse width of the triggering pulse signal comprises the time difference between the triggering edge of the analog triggering signal and the clock edge of the clock signal and the period of a fixed number of clock signals.
Description
Technical Field
The invention relates to the technical field of digital oscilloscopes, in particular to an oscilloscope for realizing analog triggering.
Background
At present, in order to be compatible with the former analog oscilloscope and used for channel expansion, the digital oscilloscope also reserves an analog trigger channel, namely an external trigger channel; since the digital oscilloscope belongs to a discrete system, and the analog trigger belongs to continuous signal trigger, an uncertain time difference exists between a frame and a frame from the trigger edge of the analog trigger signal to the clock edge of the digital clock signal, so that the waveform sampled by the analog trigger is jittered. Therefore, in order to stabilize the waveform sampled by the analog trigger, the time difference needs to be measured to compensate for the waveform jitter problem caused by the misalignment of the trigger edge and the clock edge.
Disclosure of Invention
The invention mainly solves the technical problem of how to determine the time difference between the trigger edge of an analog trigger signal and the clock edge of a clock signal under the condition of analog triggering.
An oscilloscope implementing analog triggering provided in one embodiment includes:
the data acquisition module is used for acquiring data of the signals input by the signal channel;
the analog trigger channel is used for acquiring a trigger input signal and comparing the trigger input signal with a preset trigger level to obtain an analog trigger signal;
a trigger module comprising a trigger pulse expansion circuit and a digital TDC circuit;
the trigger pulse expansion circuit is used for carrying out delay adjustment on the trigger edge of the analog trigger signal after starting to carry out data acquisition on the signal input by the signal channel to obtain a third trigger synchronous signal, and the trigger edge of the third trigger synchronous signal is synchronous with the clock edge of the clock signal of the oscilloscope; the trigger pulse expansion circuit is further configured to generate a trigger pulse signal according to a trigger edge of the analog trigger synchronization signal and a trigger edge of the third trigger synchronization signal, where a rising edge of the trigger pulse signal is the trigger edge of the analog trigger synchronization signal, and a falling edge of the trigger pulse signal is the trigger edge of the third trigger synchronization signal;
the digital TDC circuit is used for acquiring the pulse width of the trigger pulse signal and the number of clock signal cycles of the oscilloscope contained in the pulse width of the trigger pulse signal, and determining the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal based on the pulse width of the trigger pulse signal and the number of clock signal cycles of the oscilloscope contained in the pulse width of the trigger pulse signal;
and the compensation module is used for adjusting the trigger edge of the analog trigger signal based on the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal so as to synchronize the trigger edge of the analog trigger signal with the clock edge of the clock signal.
According to the oscilloscope realizing the analog trigger in the embodiment, the trigger module in the oscilloscope comprises the trigger pulse expansion circuit and the digital TDC circuit, wherein the trigger pulse expansion circuit is used for converting the analog trigger signal into the trigger pulse signal, and the pulse width of the trigger pulse signal comprises the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal and the cycles of a fixed number of clock signals, so the digital TDC circuit determines the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal according to the pulse width of the trigger pulse signal and the number of the cycles of the clock signal of the oscilloscope contained in the pulse width of the trigger pulse signal, and based on the time difference, the compensation module can adjust the trigger edge of the analog trigger signal to synchronize the trigger edge of the analog trigger signal with the clock edge of the clock signal, thereby solving the problem of sampled waveform jitter during the analog trigger.
Drawings
FIG. 1 is a schematic diagram of measuring the time difference of a trigger edge of an analog trigger signal to a clock edge of a clock signal by an analog TDC technique;
FIG. 2 is a schematic diagram of measuring the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal by a high-speed clock multiphase sampling technique;
FIG. 3 is a schematic diagram of a trigger module of an oscilloscope according to an embodiment;
FIG. 4 is a schematic diagram of a clock signal, an analog trigger signal w, a first trigger synchronization signal w1, a second trigger synchronization signal w2, a third trigger synchronization signal w3 and a trigger pulse signal p;
FIG. 5 is a schematic diagram of an embodiment of a digital TDC circuit;
FIG. 6 is a schematic diagram showing the existence of a metastable state;
FIG. 7 is a schematic diagram of a digital TDC circuit according to another embodiment;
FIG. 8 is a decoding timing diagram;
FIG. 9 is a schematic diagram of a clock signal, signals for each delay tap, and a valid signal 1;
FIG. 10 is a schematic diagram of the clock signal, the signals for the various delay taps, and the valid signal valid 2;
fig. 11 is a waveform diagram of an oscilloscope under an analog trigger.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments have been given like element numbers associated therewith. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in this specification in order not to obscure the core of the present application with unnecessary detail, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the described features, operations, or characteristics may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the description of the methods may be transposed or transposed in order, as will be apparent to a person skilled in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The ordinal numbers used herein for the components, such as "first," "second," etc., are used merely to distinguish between the objects described, and do not have any sequential or technical meaning. The term "connected" and "coupled" as used herein includes both direct and indirect connections (couplings), unless otherwise specified.
Referring to fig. 1, fig. 1 shows an example of measuring a time difference between a trigger edge of an analog trigger signal and a clock edge of a clock signal by using an analog TDC technique, where a programmable logic device (FPGA) in an oscilloscope sends a pulse 1clk with a clock width to an analog TDC circuit for spreading to obtain T1; then, sending a pulse 2clk with two clock widths to the analog TDC circuit for broadening to obtain T2; assuming that the analog TDC circuit is linear and the coefficient of spread is a, one clock signal is divided into a parts, each part having a width T = (T2-T1)/a. As shown in fig. 1, the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal is Δ T, a pulse signal composed of the analog trigger signal and the analog trigger synchronization signal is sent to the analog TDC circuit to be spread, Δ T is obtained, and the distance from the analog trigger signal to the clock edge can be calculated according to T. However, this method requires an additional hardware analog circuit for support, and the components in the analog circuit are susceptible to temperature, thereby affecting the final output result.
Referring to fig. 2, fig. 2 shows an example of measuring a time difference from a trigger edge of an analog trigger signal to a clock edge of a clock signal by using a high-speed clock multiphase sampling technique, if the clock 1 is an FPGA master clock, a higher-speed clock 2 can be used to sample the analog trigger signal, the clock 1 and the clock 2 have a certain relationship, and if 1. However, since the resolution of 1ns is only achieved with the sampling frequency of 1G, and the sampling clock needs 50G speed assuming that the resolution of 20ps is required, the FPGA cannot support such a high sampling speed.
Based on the above problems, the embodiment of the present invention converts the analog trigger signal into the trigger pulse signal, determines the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal based on the pulse width of the trigger pulse signal and the number of cycles of the clock signal included in the trigger pulse signal, and implements the analog trigger function through the digital circuit, and integrates the digital circuit into the FPGA chip of the oscilloscope without an additional hardware analog circuit.
The embodiment of the invention provides an oscilloscope for realizing analog trigger, which is called the oscilloscope for short, and comprises: the device comprises a data acquisition module, an analog trigger channel, a trigger module and a compensation module, wherein the data acquisition module is used for acquiring data of signals input by a signal channel; the analog trigger channel is used for acquiring a trigger input signal and comparing the trigger input signal with a preset trigger level to obtain an analog trigger signal; the trigger module is used for determining the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal; the compensation module is used for adjusting the trigger edge of the analog trigger signal based on the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal, so that the trigger edge of the analog trigger signal is synchronous with the clock edge of the clock signal.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a trigger module according to an embodiment, where the trigger module includes a T flip-flop 101, a first alternative switch 102, a trigger pulse expansion circuit 103, a second alternative switch 104, and a digital TDC circuit 105, which will be described in detail below.
The T trigger 101 is used for clearing the output when starting to collect data of the signal input by the signal channel, and receiving and outputting the analog trigger signal after the pre-trigger depth is full. A pin D of the T-flip-flop 101 is connected to a power VCC, a pin C (input pin) of the T-flip-flop 101 is used to receive an analog trigger signal, a pin CE of the T-flip-flop 101 is used to obtain a pre-trigger signal, and a pin RS of the T-flip-flop 101 is used to obtain an acquisition start signal, where the acquisition start signal is used to characterize a data acquisition module of the oscilloscope to start data acquisition.
In this embodiment, the analog trigger signal is output through an analog comparator, where the analog comparator includes a positive input terminal and a negative input terminal, the positive input terminal is configured to obtain an externally input trigger input signal, the negative input terminal is configured to obtain a preset trigger level, and the analog comparator is configured to compare the trigger input signal with the preset trigger level and output the analog trigger signal.
The first two-out-of-one switch 102 includes a first end, a second end, and a third end, the first end of the first two-out-of-one switch 102 is used to obtain an analog trigger signal output by the T flip-flop, the second end of the first two-out-of-one switch 102 is used to obtain a digital trigger signal, the third end of the first two-out-of-one switch 102 is connected to an input end of the trigger pulse extension circuit, and the third end is used to output the analog trigger signal or the digital trigger signal under the trigger of the trigger selection signal, that is, the first two-out-of-one switch 102 is used to switch the trigger modes of the analog trigger and the digital trigger.
The trigger pulse expansion circuit 103 is configured to perform delay adjustment on a trigger edge of the analog trigger signal after starting data acquisition on a signal input by the signal channel, so as to obtain a third trigger synchronization signal; wherein a trigger edge of the third trigger synchronization signal is synchronized with a clock edge of a clock signal of the oscilloscope. It should be noted that the clock signal of the oscilloscope refers to a local clock signal used by the oscilloscope for sampling, which is generated by the FPGA.
In addition, the trigger pulse expansion circuit 103 is further configured to generate a trigger pulse signal according to a trigger edge of the analog trigger synchronization signal and a trigger edge of the third trigger synchronization signal, where a rising edge of the trigger pulse signal is the trigger edge of the analog trigger synchronization signal, and a falling edge of the trigger pulse signal is the trigger edge of the third trigger synchronization signal.
The second alternative switch 104 includes a first terminal, a second terminal, and a third terminal, the first terminal of the second alternative switch 104 is used for acquiring the trigger pulse signal, the second terminal of the second alternative switch 104 is used for acquiring the calibration sequence signal, the third terminal of the second alternative switch 104 is connected to the input terminal of the digital TDC circuit, and the third terminal is used for calibrating the trigger pulse signal under the trigger of the calibration selection signal.
The digital TDC circuit 105 is configured to obtain a pulse width of the trigger pulse signal and a number of clock signal cycles of the oscilloscope included in the pulse width of the trigger pulse signal, and determine a time difference between a trigger edge of the analog trigger signal and a clock edge of the clock signal based on the pulse width of the trigger pulse signal and the number of clock signal cycles of the oscilloscope included in the pulse width of the trigger pulse signal.
The trigger module provided by the embodiment of the invention is a digital circuit, can be directly integrated in an FPGA of an oscilloscope, does not need an external analog circuit to measure the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal, has higher measurement precision and is not influenced by environmental factors such as temperature and the like.
The trigger pulse expansion circuit 103 and the digital TDC circuit 105 will be described in detail below.
In an embodiment, the delay adjustment of the trigger edge of the analog trigger signal by the trigger pulse spreading circuit 103 to obtain the third trigger synchronization signal includes: acquiring the period of a clock signal where a trigger edge of an analog trigger signal is positioned, and taking the clock signal corresponding to the acquired period of the clock signal as a synchronous clock signal; generating a first trigger synchronous signal based on a synchronous clock signal, wherein a trigger edge of the first trigger synchronous signal is synchronous with a clock edge of the synchronous clock signal; generating a second trigger synchronizing signal based on the first trigger synchronizing signal, wherein the trigger edge of the second trigger synchronizing signal is delayed by one clock signal period relative to the trigger edge of the first trigger synchronizing signal; and generating a third trigger synchronous signal based on the second trigger synchronous signal, wherein the triggering edge of the third trigger synchronous signal is delayed by one clock signal period relative to the triggering edge of the second trigger synchronous signal.
Referring to fig. 4, fig. 4 is a timing diagram of a clock signal, an analog trigger signal w, a first trigger synchronization signal w1, a second trigger synchronization signal w2, a third trigger synchronization signal w3 and a trigger pulse signal p. Because the analog trigger signal and the clock signal of the oscilloscope are asynchronous, the embodiment firstly synchronizes the analog trigger signal w with asynchronous signals, sequentially generates a first trigger synchronous signal w1, a second trigger synchronous signal w2 and a third trigger synchronous signal w3 to synchronize the obtained third trigger synchronous signal w3 with the clock edge of the clock signal, then takes the trigger edge of the analog trigger signal w as a rising edge and the trigger edge of the third trigger synchronous signal w3 as a falling edge to form a trigger pulse signal p, wherein the expression p =! w3& w of the trigger pulse signal p represents a logical AND! Indicating that the logic is inverted.
It should be noted that, for a clock signal, a holding time window exists on a clock edge of the clock signal, and if a trigger edge of an analog trigger signal falls within the holding time window of the clock edge, it can be considered as being synchronized with the clock edge of the clock signal, where the holding time window of the clock edge is a preset time range centered on the clock edge. In fig. 4, the trigger edge of the third trigger synchronization signal is not perfectly aligned with the clock edge of the clock signal, and the time difference between the trigger edge and the clock edge is T4, but considering the hold time window of the clock edge, the trigger edge of the third trigger synchronization signal is also considered to be synchronized with the clock edge of the clock signal, and similarly, T3 is the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal, considering the hold window time, and therefore, T3 is not a perfect trigger edge to clock edge time difference. In addition, the T time interval in fig. 4 indicates an interval in which an analog trigger signal may occur.
To sum up, the synchronizing the trigger edge of the third trigger synchronization signal with the clock edge of the clock signal of the oscilloscope comprises: the trigger edge of the third trigger synchronous signal is positioned in a holding time window of the clock edge of the clock signal of the oscilloscope; the triggering edge of the first trigger synchronization signal is synchronized with the clock edge of the synchronization clock signal and comprises the following steps: the trigger edge of the first trigger synchronization signal is within a hold time window of the clock edge of the synchronized clock signal.
It should be further noted that the trigger pulse spreading circuit 103 provided in this embodiment may be implemented by a digital circuit, for example, by three D flip-flops, where the first trigger synchronization signal is a signal output by one D flip-flop, the second trigger synchronization signal is a signal output by two D flip-flops, and the third trigger synchronization signal is a signal output by three D flip-flops.
In one embodiment, referring to FIG. 5, the digital TDC circuit 105 includes a delay chain 1051, a plurality of D flip-flops 1052, and a first thermometer code decoder 1053, which is described in detail below.
The input terminal of the delay chain 1051 is connected to the third terminal of the second one-of-two switch 104, and is configured to receive the signal output from the third terminal of the second one-of-two switch 104.
The delay chain 1051 includes a plurality of delay taps, the delay taps 11 correspond to the D flip-flops 1052 one-to-one, and each delay tap is connected to the input pin of the D flip-flop 1052 corresponding thereto; each delay tap is used for performing a delay operation with different delay times on a signal received by the delay chain 1051, wherein:
the delay tap 1 is used for performing delay operation of delay time t on the signal received by the delay chain 1051;
the delay tap 2 is used for performing delay operation of delay time 2t on the signal received by the delay chain 1051;
…
the delay tap n is used for delaying the signal received by the delay chain 1051 by a delay time nt.
Each D flip-flop 1052 is configured to receive a signal output by a corresponding delay tap, and output an active level signal when the signal received by the delay chain 1051 is a trigger pulse signal; otherwise, an invalid level signal is output. That is, when the delay chain 1051 does not receive the trigger pulse signal, all the D flip-flops output the invalid level signal, after the delay chain 1051 receives the trigger pulse signal, since the pulse width of the trigger pulse signal is limited, some of the D flip-flops 1052 output the valid level signal, and the width of the trigger pulse signal can be obtained according to the number of the D flip-flops corresponding to the output valid level signals and the delay time of the corresponding connected delay taps, in another embodiment, if the number of the D flip-flops 1052 matches the pulse width of the trigger pulse signal, it is also possible that all the D flip-flops 1052 output the valid level signal.
The first thermometer code decoder is used for receiving the level signals output by the D triggers and outputting corresponding first decoding value sequences, each first decoding value sequence comprises a plurality of first decoding values, and each first decoding value corresponds to the level signal output by each D trigger one by one; the first thermometer code decoding module determines the pulse width of the trigger pulse signal according to the number of effective decoding values in the first decoding value sequence.
In one embodiment, the number of clock signal cycles of the oscilloscope included in the pulse width of the trigger pulse signal is 2; then, determining the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal based on the pulse width of the trigger pulse signal and the number of oscilloscope clock signal cycles contained in the pulse width of the trigger pulse signal comprises: and subtracting two clock signal periods from the pulse width of the trigger pulse signal to obtain the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal.
Referring to fig. 6, when the analog trigger signal falls within the retention time window of the clock edge due to the metastable state, the analog trigger signal may be synchronized by the current clock edge as the synchronization signal 1, or may be synchronized by the next clock edge as the synchronization signal 2, that is, when the trigger pulse extension circuit 103 performs the delay adjustment on the trigger edge of the analog trigger signal, the obtained third trigger synchronization signal may include two clock signal cycles or may include three clock signal cycles with the analog trigger signal. If the number of the clock signal cycles of the oscilloscope included in the pulse width of the trigger pulse signal is taken as 2, a waveform displayed by the oscilloscope may have jitter of one clock signal cycle, and in order to avoid the existence of such a metastable state, this embodiment improves the digital TDC circuit shown in fig. 5, please refer to fig. 7, where the digital TDC circuit further includes: a second thermometer code decoder 1054, a subtractor 1055, and a counter 1056.
The first thermometer code decoder 1053 is further configured to receive signals output from the respective delay taps of the delay chain and to output a first decoded value upon detection of a first data other than 0. The second thermometer code decoder 1054 is arranged to receive the inverse of the signal output from each delay tap of the delay chain and to output a second decoded value when the first data other than 0 is detected. Referring to fig. 8, fig. 8 shows a decoding timing sequence, wherein valid1 is a first decoded value, valid2 is a second decoded value, data1 is a source signal output by the delay chain, and data2 is an anti-code signal of the source signal.
The subtractor 1055 is configured to obtain a first decoded value and a second decoded value, and perform a subtraction operation on the first decoded value and the second decoded value to obtain a first signal.
The counter 1056 is configured to receive the first signal and count the first signal to obtain a count value, where the count value is the number of clock signal periods of the oscilloscope included in the pulse width of the trigger pulse signal.
In this embodiment, if the first signal is k, then the signal k is counted, and the count value is s, then: tedge1 = (s-2) × Tclk + T3-T4, wherein Tedge1 is the trigger edge and of the analog trigger signal after the metastable state is eliminated; a time difference between clock edges of the clock signal; if the third trigger sync signal w3 is perfectly aligned with the clock edge, i.e. T4=0, the final time difference Tfinal after eliminating the metastable state is: tfinal = (s-2) × Tclk + T3.
Referring to fig. 9, if the trigger pulse signal is input to the delay chain, D (0), D (1) \8230; D (n-1) represents the signal of each delay tap, each clock signal samples the signal on the delay chain, and after a first value different from 0 is detected on the tap, the valid signal valid1 is pulled high, and the value is output, and detection is not continued any more thereafter.
Referring to fig. 10, if the trigger pulse signal is input to the delay chain, D (0) ', D (1)' \8230; 'D (n-1)' indicates the anti-code signal of each delay tap, each clock signal samples the signal on the delay chain, and after a first value other than 0 is detected on the tap, the valid signal valid2 is pulled high, and the value is output and is not detected any more thereafter.
As can be seen from a comparison between fig. 9 and fig. 10, the inversion detection timing is detected by converting the falling edge of the trigger pulse signal p into the rising edge. The analog trigger signal w has a metastable state, the third trigger synchronization signal w3 is already a steady-state signal, and 2 complete clock signal cycles exist between the rising edge and the falling edge of the trigger pulse signal p through a logic relation, so that the time difference from the analog trigger signal to the clock edge can be calculated.
The invention widens the trigger edge of the analog trigger signal into a trigger pulse signal, and then performs subtraction calculation, so that the principle that the conversion calculation can eliminate the metastable state is to avoid detecting which specific delay tap position of the trigger edge in a delay chain, but detect the relative position, and the relative position of the trigger edge is not changed when the metastable state occurs and only belongs to different clock cycles, so that the delay value of the metastable state can be combined to the next clock calculation by detecting the relative position.
Referring to fig. 11, fig. 11 is a schematic diagram of waveforms of an oscilloscope triggered by simulation, a test signal with a fixed phase difference between 20000 times and a clock signal is sent, a sample standard deviation σ =0.9lsb =16.6ps is calculated, lsb represents that the measured resolution is 18.5ps, and it can be seen from fig. 11 that the jitter peak-to-peak value of the waveform is about 300ps, which is much improved over the jitter performance of the prior art.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.
Claims (10)
1. An oscilloscope for implementing analog triggering, comprising:
the data acquisition module is used for acquiring data of the signals input by the signal channel;
the analog trigger channel is used for acquiring a trigger input signal and comparing the trigger input signal with a preset trigger level to obtain an analog trigger signal;
the trigger module comprises a trigger pulse expansion circuit and a digital TDC circuit;
the trigger pulse expansion circuit is used for carrying out delay adjustment on the trigger edge of the analog trigger signal after starting to carry out data acquisition on the signal input by the signal channel to obtain a third trigger synchronous signal, and the trigger edge of the third trigger synchronous signal is synchronous with the clock edge of the clock signal of the oscilloscope; the trigger pulse expansion circuit is further configured to generate a trigger pulse signal according to a trigger edge of the analog trigger synchronization signal and a trigger edge of the third trigger synchronization signal, where a rising edge of the trigger pulse signal is the trigger edge of the analog trigger synchronization signal, and a falling edge of the trigger pulse signal is the trigger edge of the third trigger synchronization signal;
the digital TDC circuit is used for acquiring the pulse width of the trigger pulse signal and the number of clock signal cycles of the oscilloscope contained in the pulse width of the trigger pulse signal, and determining the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal based on the pulse width of the trigger pulse signal and the number of clock signal cycles of the oscilloscope contained in the pulse width of the trigger pulse signal;
and the compensation module is used for adjusting the trigger edge of the analog trigger signal based on the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal so as to synchronize the trigger edge of the analog trigger signal with the clock edge of the clock signal.
2. The oscilloscope of claim 1, wherein the delay adjusting the trigger edge of the analog trigger signal to obtain a third trigger synchronization signal comprises:
acquiring the period of the clock signal where the trigger edge of the analog trigger signal is located, and taking the clock signal corresponding to the acquired period of the clock signal as a synchronous clock signal;
generating a first trigger synchronization signal based on the synchronous clock signal, wherein a trigger edge of the first trigger synchronization signal is synchronous with a clock edge of the synchronous clock signal;
generating a second trigger synchronization signal based on the first trigger synchronization signal, a trigger edge of the second trigger synchronization signal being delayed by a period of a clock signal relative to a trigger edge of the first trigger synchronization signal;
and generating a third trigger synchronous signal based on the second trigger synchronous signal, wherein the trigger edge of the third trigger synchronous signal is delayed by one clock signal period relative to the trigger edge of the second trigger synchronous signal.
3. The oscilloscope of claim 2, wherein synchronizing the trigger edge of the third trigger synchronization signal to the clock edge of the oscilloscope's clock signal comprises:
the trigger edge of the third trigger synchronous signal is positioned in a holding time window of the clock edge of the clock signal of the oscilloscope; the holding time window of the clock edge is a preset time range taking the clock edge as a center;
the triggering edge of the first trigger synchronizing signal and the clock edge of the synchronizing clock signal synchronously comprise:
a trigger edge of the first trigger synchronization signal is within a hold time window of a clock edge of the synchronized clock signal.
4. The oscilloscope of claim 1, wherein the digital TDC circuit comprises: the thermometer code decoder comprises a delay chain, a plurality of D triggers and a first thermometer code decoder;
the delay chain comprises a plurality of delay taps, the delay taps correspond to the D triggers one by one, and each delay tap is connected with an input pin of the corresponding D trigger; each delay tap is used for performing delay operation with different delay time on the signal received by the delay chain, wherein:
the delay tap 1 is used for carrying out delay operation of delay time t on the signal received by the delay chain;
the delay tap 2 is used for carrying out delay operation of delay time 2t on the signal received by the delay chain;
…
the delay tap n is used for carrying out delay operation of delay time nt on the signal received by the delay chain;
each D trigger is used for receiving a signal output by the corresponding delay tap and outputting an effective level signal when the received signal is the trigger pulse signal; otherwise, outputting an invalid level signal;
the first thermometer code decoder is used for receiving the level signals output by the D triggers and outputting corresponding first decoding value sequences, the first decoding value sequences comprise a plurality of first decoding values, and the first decoding values correspond to the level signals output by the D triggers one to one; the first thermometer code decoder determines the pulse width of the trigger pulse signal according to the number of effective decoding values in the first decoding value sequence.
5. The oscilloscope of claim 4, wherein the number of clock signal cycles of the oscilloscope included in the pulse width of the trigger pulse signal is 2;
the determining a time difference between a trigger edge of the analog trigger signal and a clock edge of the clock signal based on the pulse width of the trigger pulse signal and the number of clock signal cycles of the oscilloscope included in the pulse width of the trigger pulse signal comprises:
and subtracting two clock signal periods from the pulse width of the trigger pulse signal to obtain the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal.
6. The oscilloscope of claim 4, wherein the digital TDC circuit further comprises: a second thermometer code decoder, a subtractor and a counter;
the first thermometer code decoder is further used for receiving signals output by each delay tap of the delay chain and outputting a first decoded value when a first signal which is not 0 is detected;
the second thermometer code decoder is used for receiving the code reversal signal of the signal output by each delay tap of the delay chain and outputting a second decoding value when detecting the first data which is not 0;
the subtracter is used for acquiring a first decoding value and a second decoding value and performing subtraction operation on the first decoding value and the second decoding value to obtain a first signal;
the counter is used for receiving the first signal and counting the first signal to obtain a count value, wherein the count value is the number of clock signal cycles of the oscilloscope included in the pulse width of the trigger pulse signal.
7. The oscilloscope of claim 6, wherein said determining a time difference between a trigger edge of the analog trigger signal and a clock edge of the clock signal based on a pulse width of the trigger pulse signal and a number of clock signal cycles of the oscilloscope contained in the pulse width of the trigger pulse signal comprises:
and subtracting the counted number of clock signal cycles from the pulse width of the trigger pulse signal to obtain the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal.
8. The oscilloscope of claim 1, wherein the trigger module further comprises: the trigger circuit comprises a T trigger, a first alternative switch and a second alternative switch;
the T trigger is used for resetting the output when starting to acquire data of a signal input by the signal channel, and receiving and outputting the analog trigger signal after the pre-trigger depth is full;
the first alternative switch comprises a first end, a second end and a third end, wherein the first end is used for acquiring the analog trigger signal output by the T trigger, the second end is used for acquiring the digital trigger signal, the third end is connected with the input end of the trigger pulse expansion circuit, and the third end is used for outputting the analog trigger signal or the digital trigger signal under the trigger of the trigger selection signal;
the second alternative switch comprises a first end, a second end and a third end, wherein the first end is used for acquiring the trigger pulse signal, the second end is used for acquiring a calibration sequence signal, the third end is connected with the input end of the digital TDC circuit, and the third end is used for correcting the trigger pulse signal under the trigger of a correction selection signal.
9. The oscilloscope of claim 1, wherein the analog trigger path comprises:
the analog comparator comprises a positive phase input end and a negative phase input end, the positive phase input end is used for obtaining the trigger input signal, the negative phase input end is used for obtaining a preset trigger level, and the analog comparator is used for comparing the trigger input signal with the preset trigger level and outputting the analog trigger signal.
10. The oscilloscope of claim 1, comprising:
the trigger module is integrated in the programmable logic device.
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