CN113315521A - Digital time converter and electronic device - Google Patents
Digital time converter and electronic device Download PDFInfo
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- CN113315521A CN113315521A CN202110514323.2A CN202110514323A CN113315521A CN 113315521 A CN113315521 A CN 113315521A CN 202110514323 A CN202110514323 A CN 202110514323A CN 113315521 A CN113315521 A CN 113315521A
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- H03—ELECTRONIC CIRCUITRY
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- H03M1/12—Analogue/digital converters
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Abstract
The invention discloses a digital time converter and an electronic device, wherein the digital time converter comprises more than one level of digital time conversion units; the digital time conversion unit includes: a first Delay unit (Delay), a second Delay, a first D flip-flop (DFF) and a second DFF; the input end of the first Delay receives a first input signal or is connected with the output end of an adjacent digital time conversion unit, and the output end of the first Delay is respectively connected with the first input ends of the first DFF and the second DFF and the input end of the adjacent digital time conversion unit; the input end of the second Delay receives a second input signal or is connected with the output end of the adjacent digital time conversion unit; the input end and the output end of the second Delay are respectively connected with the second input ends of the second DFF and the first DFF; the first and second DFFs respectively output digital signals representing lead or lag information; the Delay time duration is the same for all Delay. The embodiment of the invention designs the time-to-digital converter which is more in line with the application requirements in all aspects.
Description
Technical Field
The present disclosure relates to, but not limited to, time interval measurement techniques, and more particularly, to a digital-to-time converter and an electronic device.
Background
In the field of large-scale integrated circuits, the time resolution of a traditional Flash memory (Flash) type time-to-digital converter (TDC) is the time delay of a single delay unit, and the clocks of all D triggers are reference clocks; the fan-out of Flash type time-to-digital converters (the larger the fan-out, the more problems need to be considered during design, and thus the higher the complexity) is large; the mismatch problem is very serious due to the use of a single delay chain. The Vernier (Vernier) type time-to-digital converter adopts two fast and slow delay chains, the output of each stage of slow delay unit is respectively used as a clock of a D trigger (DFF), and the fan-out problem is relieved; the time resolution of the Vernier time-to-digital converter is the difference value of the delay time of the fast delay unit and the delay time of the slow delay unit, so that higher time resolution can be realized; however, since the difference of the delay times of the delay units of the two delay chains is relied on, calibration is required; in addition, because a single delay unit has larger delay, the Vernier time-to-digital converter generally has larger area, and the larger parasitic capacitance causes the Vernier time-to-digital converter to have higher dynamic power consumption.
In summary, it is a problem to be solved to design and implement a time-to-digital converter that can satisfy application requirements in aspects of fan-out, mismatch, time resolution, power consumption, and the like.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
Embodiments of the present invention provide a digital-to-time converter and an electronic device, which can obtain a time-to-digital converter that better meets application requirements in all aspects.
An embodiment of the present invention provides a digital time converter, including: more than one stage of digital time conversion unit; the digital time conversion unit includes: the digital signal processing device comprises a first delay unit, a second delay unit, a first D trigger and a second D trigger; wherein the content of the first and second substances,
the input end of the first delay unit is used for receiving a first input signal or connecting the output ends of the adjacent digital time conversion units; the output end of the first delay unit is respectively connected with the first input end of the first D trigger and the first input end of the second D trigger, and is connected with the input ends of the adjacent digital time conversion units;
the input end of the second delay unit is used for receiving a second input signal or connecting the output ends of the adjacent digital time conversion units; the input end and the output end of the second delay unit are respectively connected with the second input end of the second D trigger and the second input end of the first D trigger;
the first D flip-flop outputs a first output signal representing a lead or lag of the first input signal after transmission through the first D flip-flop; the second D flip-flop outputs a second output signal which is used for representing the lead or lag of the second input signal after being transmitted by the second D flip-flop;
and all the first delay units and the second delay units have the same delay time length.
In an exemplary embodiment, the output terminal of the first D flip-flop and the output terminal of the second D flip-flop are respectively connected to the input terminal of the codec.
In one illustrative example, the codec comprises: a thermometer codec.
In one illustrative example, the number of stages of the digital-to-time conversion unit includes: and 32 stages.
In one illustrative example, the first input signal comprises: a pulse signal; the second input signal comprises: a reference signal.
On the other hand, the embodiment of the invention also provides an electronic device, which comprises the digital-to-time converter.
The digital time converter of the embodiment of the invention comprises more than one level of digital time conversion units; the digital time conversion unit includes: the digital signal processing device comprises a first delay unit, a second delay unit, a first D trigger and a second D trigger; the input end of the first delay unit is used for receiving a first input signal or connecting the output ends of the adjacent digital time conversion units; the output end of the first delay unit is respectively connected with the first input end of the first D trigger and the first input end of the second D trigger, and is connected with the input ends of the adjacent digital time conversion units; the input end of the second delay unit is used for receiving a second input signal or connecting the output ends of the adjacent digital time conversion units; the input end and the output end of the second delay unit are respectively connected with the second input end of the second D trigger and the second input end of the first D trigger; the first D flip-flop outputs a first output signal representing a lead or lag of the first input signal after transmission through the first D flip-flop; the second D flip-flop outputs a second output signal which is used for representing the lead or lag of the second input signal after being transmitted by the second D flip-flop; and all the first delay units and the second delay units have the same delay time length. The embodiment of the invention designs and realizes the time-to-digital converter which is more in line with the application requirements in all aspects.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
FIG. 1 is a block diagram of a digital-to-time converter according to an embodiment of the present invention;
FIG. 2 is a coding diagram of a codec according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.
Fig. 1 is a block diagram of a digital-to-time converter according to an embodiment of the present invention, as shown in fig. 1, including: more than one stage of digital time conversion unit; the digital time conversion unit includes: a first Delay unit (Delay), a second Delay unit, a first D flip-flop (DFF) and a second D flip-flop; wherein the content of the first and second substances,
the input end of the first delay unit is used for receiving a first input signal or connecting the output ends of the adjacent digital time conversion units; the output end of the first delay unit is respectively connected with the first input end of the first D trigger and the first input end of the second D trigger, and is connected with the input ends of the adjacent digital time conversion units;
the input end of the second delay unit is used for receiving a second input signal or connecting the output ends of the adjacent digital time conversion units; the input end and the output end of the second delay unit are respectively connected with the second input end of the second D trigger and the second input end of the first D trigger;
the first D flip-flop outputs a first output signal representing a lead or lag of the first input signal after transmission through the first D flip-flop; the second D flip-flop outputs a second output signal which is used for representing the lead or lag of the second input signal after being transmitted by the second D flip-flop;
and all the first delay units and the second delay units have the same delay time length.
In one illustrative example, the first output signal and the second output signal of embodiments of the present invention may be 0/1 digital signals that are used to characterize lead or lag information.
In an illustrative example, the first D flip-flop and the second D flip-flop of the embodiment of the present invention output a phase difference of digital signals,
the digital time converter of the embodiment of the invention comprises more than one level of digital time conversion units; the digital time conversion unit includes: the digital signal processing device comprises a first delay unit, a second delay unit, a first D trigger and a second D trigger; the input end of the first delay unit is used for receiving a first input signal or connecting the output ends of the adjacent digital time conversion units; the output end of the first delay unit is respectively connected with the first input end of the first D trigger and the first input end of the second D trigger, and is connected with the input ends of the adjacent digital time conversion units; the input end of the second delay unit is used for receiving a second input signal or connecting the output ends of the adjacent digital time conversion units; the input end and the output end of the second delay unit are respectively connected with the second input end of the second D trigger and the second input end of the first D trigger; the first D flip-flop outputs a first output signal representing a lead or lag of the first input signal after transmission through the first D flip-flop; the second D flip-flop outputs a second output signal which is used for representing the lead or lag of the second input signal after being transmitted by the second D flip-flop; and the delay time lengths of all the first delay units and the second delay units are the same. The embodiment of the invention designs and realizes the time-to-digital converter which is more in line with the application requirements in all aspects.
In an exemplary embodiment, the first delay units included in more than one digital-to-time conversion units are forward-serially connected to form a delay chain, that is, the input end of the first delay unit is used for receiving the first input signal or connecting the output end of the first delay unit in the adjacent digital-to-time conversion unit.
In an exemplary embodiment, the second delay units included in more than one digital-to-time conversion units are connected in series in reverse to form a delay chain, that is, the input end of the second delay unit is used for receiving a second input signal or connecting the output end of the second delay unit in an adjacent digital-to-time conversion unit.
In an exemplary embodiment, the output terminal of the embodiment of the present invention and the output terminal of the second D flip-flop are respectively connected to the input terminal of the codec.
In one illustrative example, a codec according to an embodiment of the present invention includes: a thermometer codec.
In the embodiment of the invention, after the first delay unit and the second delay unit transmit and process the first input signal and the second input signal, the first D trigger and the second D trigger output signals representing the phase difference of the digital signals to the coder-decoder.
In an illustrative example, the number of stages of the digital-to-time conversion unit in an embodiment of the present invention includes: and 32 stages. Fig. 2 is a schematic encoding diagram of a codec according to an embodiment of the present invention, and as shown in fig. 2, for a digital-to-time converter including 32 stages of digital-to-time conversion units, the decoding result is [ -31, 32], and positive delay and negative delay can be measured.
In an exemplary embodiment, when the number of stages included in the digital-to-time conversion unit is greater than 2, loads of the digital-to-time conversion units at different stages are the same based on forward and reverse links of the first delay unit and the second delay unit included in the digital-to-time conversion unit.
In one illustrative example, a first input signal of an embodiment of the present invention comprises: a reference clock signal; the second input signal includes: the clock signal is divided.
In one illustrative example, a first input signal of an embodiment of the present invention comprises: a pulse signal; the second input signal includes: a reference signal.
In an exemplary example, the first input signal and the second input signal may be other kinds of signals according to application scenarios of the digital-to-time converter, for example, the first input signal and the second input signal may be two-way input signals for differential operation.
The TDC provided by the embodiment of the invention can be applied to the technical fields of telecommunication communication, chip design, digital oscilloscopes, atomic physics, astronomical observation, laser ranging, satellite positioning and the like.
An embodiment of the present invention further provides an electronic device, which includes the digital-to-time converter shown in fig. 1.
In an illustrative example, an electronic device according to an embodiment of the present invention may include: the device comprises a digital delay lock loop, a testing device, a phase locking circuit, a communication transceiver, a time calibration device and the like.
In an exemplary embodiment, when the electronic device is a phase-locked circuit, the port of the first delay unit receiving the first input signal may be connected to an output of the reference clock, the port of the second delay unit receiving the second input signal may be connected to an output of the feedback clock, and the time-to-digital converter is configured to quantize a phase difference between the reference clock and the feedback clock. For some communication transceivers, the port of the first delay unit for receiving the first input signal may be connected to the output of the pulse signal, the port of the second delay unit for receiving the second input signal may be connected to the output of the reference signal, and the time-to-digital converter is used to quantize the phase difference between the received signal and the clock.
"one of ordinary skill in the art will appreciate that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media "as is well known to those of ordinary skill in the art.
Claims (7)
1. A digital-to-time converter comprising: more than one stage of digital time conversion unit; the digital time conversion unit includes: the digital signal processing device comprises a first delay unit, a second delay unit, a first D trigger and a second D trigger; wherein the content of the first and second substances,
the input end of the first delay unit is used for receiving a first input signal or connecting the output ends of the adjacent digital time conversion units; the output end of the first delay unit is respectively connected with the first input end of the first D trigger and the first input end of the second D trigger, and is connected with the input ends of the adjacent digital time conversion units;
the input end of the second delay unit is used for receiving a second input signal or connecting the output ends of the adjacent digital time conversion units; the input end and the output end of the second delay unit are respectively connected with the second input end of the second D trigger and the second input end of the first D trigger;
the first D flip-flop outputs a first output signal representing a lead or lag of the first input signal after transmission through the first D flip-flop; the second D flip-flop outputs a second output signal which is used for representing the lead or lag of the second input signal after being transmitted by the second D flip-flop;
and all the first delay units and the second delay units have the same delay time length.
2. The digital-to-time converter according to claim 1, wherein the output of the first D flip-flop and the output of the second D flip-flop are each connected to an input of a codec.
3. The digital to time converter of claim 2, wherein said codec comprises: a thermometer codec.
4. The digital to time converter of claim 1, wherein the number of stages of the digital to time conversion unit comprises: and 32 stages.
5. A digital to time converter according to any of claims 1 to 4, wherein the first input signal comprises: a pulse signal; the second input signal comprises: a reference signal.
6. A digital to time converter according to any of claims 1 to 4, wherein the first input signal comprises: a reference clock signal; the second input signal comprises: the clock signal is divided.
7. An electronic device comprising a digital-to-time converter as claimed in any one of claims 1 to 6.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115541955A (en) * | 2022-12-01 | 2022-12-30 | 深圳市鼎阳科技股份有限公司 | Oscilloscope for realizing analog triggering |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103262423A (en) * | 2011-03-07 | 2013-08-21 | 松下电器产业株式会社 | Phase-to-digital conversion circuit and phase-to-digital converter provided therewith |
| CN103986461A (en) * | 2014-05-30 | 2014-08-13 | 华为技术有限公司 | Time digital conversion method and time digital converter |
| KR20140137276A (en) * | 2013-05-22 | 2014-12-02 | 서울대학교산학협력단 | Delay line time-to-digital converter |
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- 2021-05-07 CN CN202110514323.2A patent/CN113315521B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103262423A (en) * | 2011-03-07 | 2013-08-21 | 松下电器产业株式会社 | Phase-to-digital conversion circuit and phase-to-digital converter provided therewith |
| KR20140137276A (en) * | 2013-05-22 | 2014-12-02 | 서울대학교산학협력단 | Delay line time-to-digital converter |
| CN103986461A (en) * | 2014-05-30 | 2014-08-13 | 华为技术有限公司 | Time digital conversion method and time digital converter |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115541955A (en) * | 2022-12-01 | 2022-12-30 | 深圳市鼎阳科技股份有限公司 | Oscilloscope for realizing analog triggering |
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