CN112487354B - Multi-channel high-speed real-time cross-correlation operation device based on comparator and FPGA - Google Patents

Multi-channel high-speed real-time cross-correlation operation device based on comparator and FPGA Download PDF

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CN112487354B
CN112487354B CN202011376874.9A CN202011376874A CN112487354B CN 112487354 B CN112487354 B CN 112487354B CN 202011376874 A CN202011376874 A CN 202011376874A CN 112487354 B CN112487354 B CN 112487354B
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fpga
data
stage
correlation operation
comparator
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CN112487354A (en
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苗俊刚
胡岸勇
郭翔宙
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Beihang University
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Beihang University
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/15—Correlation function computation including computation of convolution operations

Abstract

The invention relates to a multi-channel high-speed real-time cross-correlation operation device based on a comparator and an FPGA (field programmable gate array). The comparator is used for carrying out high-speed low-order quantization sampling on an analog input signal, and compared with a general high-order quantization analog-to-digital converter, the multi-channel high-speed real-time cross-correlation operation device reduces the cost, the volume and the power consumption of a sampling circuit; the FPGA carries out real-time delay correction on the received high-speed serial data, so that the receiving rate of the multi-channel synchronous data is improved; meanwhile, the FPGA converts the received high-speed serial data into parallel data to perform cross-correlation operation, and the problem that the internal logic working clock frequency of the FPGA is lower than the sampling clock frequency is solved. The invention uses FPGA as the operation processor, which has strong reconfigurability and can be widely applied to various microwave and millimeter wave measurement systems.

Description

Multi-channel high-speed real-time cross-correlation operation device based on comparator and FPGA
Technical Field
The invention relates to a cross-correlation operation structure, in particular to a multi-channel high-speed real-time cross-correlation operation device based on a comparator and an FPGA.
Background
In many microwave and millimeter wave measurement systems, correlators are core devices, and the number of correlators is proportional to the square of the number of analog channels required to perform pairwise cross-correlation. For a microwave millimeter wave multi-channel real-time interferometry system with a large bandwidth, the number of correlators is large, and the problems of cost, power consumption and size are faced in the implementation process by adopting a correlation operation structure of a general high-order quantization analog-to-digital converter. Therefore, the real-time cross-correlation operation structure with low cost, small power consumption and high integration level has important significance for the microwave and millimeter wave interference measurement system.
Disclosure of Invention
The invention solves the problems: the device overcomes the defects of the prior art, provides the multichannel high-speed real-time cross-correlation operation device based on the comparator and the FPGA, solves the problem that the internal logic working clock frequency of the FPGA is lower than the sampling clock frequency, reduces the cost, the volume and the power consumption of a sampling circuit, and simultaneously improves the receiving rate of multichannel synchronous data.
The technical scheme of the invention is as follows: a real-time correlation operation device based on a comparator and an FPGA is characterized by comprising: and performing low-order quantization sampling by using a comparator, and performing real-time correlation operation processing by using an FPGA (field programmable gate array). The clock circuit generates a synchronous sampling clock with adjustable relative delay and a data receiving clock, the synchronous sampling clock is provided for the comparator, and the data receiving clock is provided for the FPGA. The FPGA carries out real-time delay correction on the received high-speed serial data, so that the receiving rate of the multichannel synchronous data is improved. The FPGA converts the received high-speed serial data into parallel data to perform cross-correlation operation, and the problem that the internal logic working clock frequency of the FPGA is lower than the sampling clock frequency is solved. The accumulator of the correlation operation uses a two-stage accumulation structure, and the consumption of logic resources is reduced. The accumulator for parallel data correlation operation reduces the working clock frequency of the accumulator by truncating part of the less significant bits.
Compared with the prior art, the invention has the advantages that:
(1) The invention uses the comparator to carry out low-order quantization on the input analog signal, and because the comparator has simple structure, the cost, the power consumption and the volume are far lower than those of a common high-order quantization analog-to-digital converter, and the requirement of sampling rate can be met.
(2) The invention carries out real-time delay correction on the received high-speed serial data in the FPGA chip, and improves the receiving rate of the multichannel synchronous data.
(3) According to the invention, the received high-speed serial data is converted into parallel data in the FPGA chip for cross-correlation operation, so that the problem that the internal logic working clock frequency of the FPGA is lower than the sampling clock frequency is solved.
Drawings
FIG. 1 is a basic block diagram of the apparatus of the present invention;
FIG. 2 is a basic structure of a clock circuit;
FIG. 3 is a basic structure of an edge latch comparator;
FIG. 4 is a functional block diagram of serial-to-parallel conversion and data delay correction;
FIG. 5 is a delay adjustment method when the delay time of reference data is half a bit period longer than the delay time of original data;
FIG. 6 is a method of delay adjustment when the reference data is half a bit period shorter than the original data delay time;
FIG. 7 is a functional block diagram of a correlation operation using parallel data;
FIG. 8 is a truth table of second-order quantization correlation operation;
FIG. 9 is a truth table for three-order quantization correlation operations;
FIG. 10 is a block diagram of a two-stage accumulation operation;
fig. 11 is a low order truncated accumulator structure.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
As shown in fig. 1, the structure of the present invention uses a comparator array to perform low-order quantization sampling, and uses an FPGA to perform real-time correlation operation processing. The clock circuit generates a synchronous sampling clock and a data receiving clock, the sampling clock is provided for the comparator, and the data receiving clock is provided for the FPGA. The FPGA carries out real-time delay correction on the received high-speed serial data, so that the receiving rate of the multichannel synchronous data is improved. The FPGA converts the received high-speed serial data into parallel data to perform cross-correlation operation, and solves the problem that the internal logic working clock frequency of the FPGA is lower than the sampling clock frequency.
Referring to fig. 2, in a large-scale system where a single clock generator chip generally does not have enough output to drive all analog-to-digital converters and processor chips, the present invention employs a multi-level structure of clock trees to drive the various devices synchronously.
Referring to fig. 3, the comparator adopts an edge latch structure, and the data output has a two-stage latch structure. The output of the comparator will lock onto the input signal state at the time of the rising edge of the sampling clock and remain unchanged until the next rising edge of the sampling clock comes to update its output. The edge-latched comparator can remain stable throughout the clock cycle.
Referring to fig. 4, the data receiving clock input to the FPGA chip is generated by an external clock circuit, the clock is directly used as a serial data receiving clock in the serial-to-parallel module, and a low-speed clock obtained by dividing the frequency of the clock within the FPGA chip is used to drive logic related to parallel data. The phase relationship (relative delay) of the data receiving clock of the FPGA chip and the sampling clock of the comparator will be discussed in detail below. High-speed serial data input into the FPGA chip is converted into low-speed parallel data through a serial-to-parallel module, and the parallel data are transmitted to internal logic through asynchronous FIFO (First-in/First-out) so as to avoid increasing the time sequence complexity of the internal logic. In order to increase the rate of serial-to-parallel conversion module receiving serial data as much as possible, the serial data is delayed in time before being input into the serial-to-parallel conversion module, and the serial data receiving clock is adjusted to be at the optimal position, namely the middle point of each bit period, for sampling. The delay adjustment method adopted by the invention needs an extra path of data as reference, the delay time of the path of data is different from the original data by half bit period, and the extra path of data is only used for adjusting data delay and is not transmitted to internal operation logic. For convenience of the following description, serial data finally transferred to the internal arithmetic logic is referred to as original data, and serial data used only for delay adjustment is referred to as reference data. Because the delay adjustment module is realized by using internal logic resources of the FPGA chip, the highest working clock frequency of the delay adjustment module is lower than the high-speed sampling clock frequency, delay adjustment can be carried out only by using parallel data, and the reference data also needs to carry out serial-to-parallel operation. The serial-to-parallel modules of the original data and the reference data use the same clock configuration.
Referring to fig. 5 and 6, the delay adjustment module determines a position of a sampling point of the serial data receiving clock in the original data bit period relative to a midpoint of the bit period based on a principle of a binary phase detector, and increases or decreases a delay time of the input reference data to make the sampling point continuously approach the midpoint of the bit period and finally stabilize at the midpoint of the bit period. When the reference data is longer than the delay time of the original data by half a bit period, after the data is changed once, if the sampling results of the original data and the reference data are the same, the data receiving clock is located at the second half of the bit period at the sampling point of the original data, and the delay time of the original data should be increased, as shown in (a) of fig. 5; if the sampling results of the original data and the reference data are different, the data reception clock is located in the first half bit period at the sampling point of the original data, and the delay time of the original data should be reduced, as shown in (b) of fig. 5. When the reference data is a half bit period shorter than the delay time of the original data, after the change of the primary data, if the sampling results of the original data and the reference data are the same, the data receiving clock is located in the first half bit period at the sampling point of the original data, and the delay time of the original data should be reduced, as shown in (a) of fig. 6; if the original data and the reference data have different sampling results, the data reception clock is located in the second half bit period at the sampling point of the original data, and the delay time of the original data should be increased, as shown in (b) of fig. 6. The delay adjustment method needs dynamic change of input data, and if the input data is always 0 or always 1, the delay time can keep the initial value unchanged. Because the resolution of delay adjustment in practical application cannot be infinitesimal, the sampling point of the final data receiving clock cannot be accurately located at the midpoint of the bit period, but swings left and right at the midpoint of the bit period, and is in a dynamic balance state.
Referring to fig. 7, when performing correlation operation using parallel data, multiplication operations are first performed on the parallel data, the multiplication results are then added, and finally the output results of the adder are accumulated.
Referring to fig. 8, for the second-order quantization multiplication operation, since the multiplication result only contains "0" and "1", the accumulation operation can be implemented by using a one-way accumulator with an input bit width of 1.
Referring to fig. 9, for the third-order quantization multiplication, the input data of the multiplication is the original binary encoding mode of the third-order quantization result, and no additional encoder is needed to encode the quantization result. The output result of the multiplication operation adopts a binary complement form, and the accumulation operation can be realized by adopting a one-way accumulator with the input bit width of 2.
Referring to fig. 10, the accumulator employs a two-stage accumulation structure to reduce the logic resource usage of the accumulation operation. Setting input data bit width to N 0 In the two-stage accumulation structure, the first-stage accumulator is used for completing accumulation operation of short point number, and the output bit width is N 1 When the maximum number of times of accumulation 2 is reached N1 Then, latching the accumulation result, then resetting the first-stage accumulator and starting a new accumulation period; the second-stage accumulator reads the latched result of the first-stage accumulator and continues to perform the operation by the first-stage accumulated resultThe operation is accumulated to obtain a longer integration time. Because the first-stage accumulator updates the latched result after reaching the maximum accumulation times, the second-stage accumulation operation times required to be executed in one integration period are far less than the first-stage accumulation operation times, and a plurality of first-stage accumulators can share one second-stage accumulator. In order to realize multiplexing of the second-stage accumulator, a dual-port Random Access Memory (RAM) is used as a buffer for the accumulation result of the second-stage accumulator. When the second-stage accumulator works, the address generator generates the serial number of the first-stage accumulator and the corresponding RAM address, the serial number and the corresponding RAM address are written into the RAM when the latch result of the first-stage accumulator is read for the first time, then the currently stored result of the dual-port RAM is read out through one port and added with the latch result of the corresponding first-stage accumulator when the latch result of the first-stage accumulator is read each time, and finally the added result is written back to the RAM. When one integration period is finished, the correlation operation result is read out from the other port of the dual-port RAM. Because the dual-port RAM needs to participate in the whole operation process, the relative operation result in the dual-port RAM is not read in enough time. In order to solve the problem, the dual-port RAM adopts a ping-pong structure, an internal storage area of the dual-port RAM is equally divided into two parts, the two parts of the storage area are in a data operation state and a data reading state in turn, and a system can read a correlation operation result of the previous integration period while performing correlation operation. When M first-stage accumulators share one second-stage accumulator, the depth of the dual-port RAM required by a single second-stage accumulator is 2M.
Referring to fig. 11, when the operating clock of the two-stage accumulation structure in fig. 10 cannot reach the required frequency, the first-stage accumulator may be split into two accumulators connected in series. The output bit width of the first accumulator is N 11 The output bit width of the second accumulator is N 12 And N is 11 +N 12 ＝N 1 . The first accumulator takes only the carry output of the most significant bit as the input of the second accumulator, which degenerates into a counter, for convenience of description hereinafter, the first accumulator is referred to as the carry output accumulator, and the second accumulator is referred to as the second accumulatorThe device is called a counter. The update time of the carry output accumulator is 2 N11-N0 ×T 1 Thus, the duty cycle of the counter may be increased to 2 N11-N0 ×T 1 I.e. the frequency of the counter's operating clock can be reduced to 1/2 of the carry output accumulator N11-N0 The operating clock frequency of the corresponding subsequent structure is also reduced proportionally. The structure reduces the area of a high-speed clock area in the FPGA chip, thereby being beneficial to improving the working frequency of a high-density accumulator array. It should be noted that the counter is equivalent to 2 N11 Count in units of units, and multiply the output by 2 N11 The original result is the final accumulated result, and the final accumulated result has an error with the original result, the maximum value of the error is (2) N11 -1). Since it usually satisfies 2 N11 <<2 N2 The error is negligible.
In a word, the analog input signal is subjected to high-speed low-order quantization sampling by using the comparator, and compared with a general high-order quantization analog-to-digital converter, the cost, the volume and the power consumption of a sampling circuit are reduced; the FPGA carries out real-time delay correction on the received high-speed serial data, so that the receiving rate of the multi-channel synchronous data is improved; meanwhile, the FPGA converts the received high-speed serial data into parallel data to perform cross-correlation operation, and the problem that the internal logic working clock frequency of the FPGA is lower than the sampling clock frequency is solved. The invention uses FPGA as the operation processor, which has strong reconfigurability and can be widely applied to various microwave and millimeter wave measurement systems.
The above description of the embodiments of the present invention is provided in conjunction with the accompanying drawings, which mainly illustrate the design idea and design principle of a multi-channel high-speed real-time cross-correlation structure based on comparators and FPGA, and is not intended to limit the present invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (3)

1. A multi-channel high-speed real-time cross-correlation operation device based on a comparator and an FPGA is characterized by comprising: the hardware consists of a comparator array, an FPGA and a clock circuit; the comparator carries out low-order quantization sampling on the input signal, and the FPGA receives a sampling result and carries out real-time correlation operation processing; the clock circuit generates a synchronous sampling clock with adjustable relative delay and a data receiving clock, the synchronous sampling clock is provided for the comparator, and the data receiving clock is provided for the FPGA;
the FPGA carries out real-time delay correction on the received high-speed serial data, and then the FPGA converts the received high-speed serial data into parallel data to carry out cross-correlation operation;
the accumulator for correlation operation uses a two-stage accumulation structure, which specifically comprises: setting input data bit width to N 0 In the two-stage accumulation structure, the first-stage accumulator is used for completing short point number accumulation operation, and the output bit width is N 1 When the maximum accumulation times reach 2N1, the accumulation result is latched, then the first-stage accumulator is cleared, and a new accumulation period is started; the second-stage accumulator reads the latching result of the first-stage accumulator and continues accumulation operation on the first-stage accumulation result; a plurality of first-stage accumulators share one second-stage accumulator; when the second-stage accumulator works, the address generator generates the serial number of the first-stage accumulator and the corresponding RAM address, the serial number and the corresponding RAM address are written into the RAM when the latch result of the first-stage accumulator is read for the first time, then the currently stored result of the dual-port RAM is read out through one port when the latch result of the first-stage accumulator is read each time, and is added with the latch result of the corresponding first-stage accumulator, and finally the added result is written back into the RAM; after one integration period is finished, reading out a correlation operation result from the other port of the dual-port RAM; the dual-port RAM adopts a ping-pong structure, an internal storage area of the dual-port RAM is equally divided into two parts, the two parts of storage areas are in a data operation state and a data reading state in turn, and a correlation operation result of the previous integration period is read while correlation operation is carried out; when M first-stage accumulators share one second-stage accumulator, the depth of the dual-port RAM required by a single second-stage accumulator is 2M.
2. The multi-channel high-speed real-time cross-correlation operation device based on the comparator and the FPGA as claimed in claim 1, wherein: the comparator is in an edge latching structure, and a digital output interface of the comparator only outputs serial data and does not output a source synchronous clock.
3. The multi-channel high-speed real-time cross-correlation operation device based on the comparator and the FPGA of claim 1, wherein: the accumulator of the parallel data correlation operation splits the first stage accumulator into two serially connected accumulators.
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