CN107425953B - Synchronizing device, synchronous method and the speed receiver using the synchronizing device - Google Patents
Synchronizing device, synchronous method and the speed receiver using the synchronizing device Download PDFInfo
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- CN107425953B CN107425953B CN201710382528.3A CN201710382528A CN107425953B CN 107425953 B CN107425953 B CN 107425953B CN 201710382528 A CN201710382528 A CN 201710382528A CN 107425953 B CN107425953 B CN 107425953B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
- H04L7/007—Detection of the synchronisation error by features other than the received signal transition detection of error based on maximum signal power, e.g. peak value, maximizing autocorrelation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
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Abstract
The invention proposes a kind of synchronizing device of laser communication ranging integral system, synchronous method and use the speed receiver of the synchronizing device.Speed receiver receives high speed signal, it is sampled using analog-digital converter (ADC) first, sampled data is sent into gigabit transceiver (GTH) again and carries out serioparallel exchange, converting high-speed serial is changed to the lower multidiameter delay data of rate.Subsequent parallel data is admitted in synchronizing device that carry out signal synchronous, and parallel data will carry out parallel data frame-grab, dynamic calibration and high-speed phase-locked loop tracking in synchronizing device, and receiver completes the precise synchronization to high speed signal as a result,.On the basis of signal precise synchronization, the ranging branch and communication leg of receiver will calculate distance measurement result and communication data.The present invention alleviates clock burden while guaranteeing signal precise synchronization, ranging and accurate result of communication, and effectively reduces hard-wired complexity.
Description
Technical field
Together the present invention relates to one of laser communication ranging integral system synchronizing device, synchronous method and using this
The speed receiver for walking device, belongs to electronic communication and Radar Technology field.
Background technique
Laser communication ranging integral system requires between space-based terminal (satellite) and earth station, space-based terminal (satellite) and
High speed data transfer and precision distance measurement integrated function are realized using laser between space-based terminal (satellite).Namely using same
The signal in one channel is completed at the same time communication and two kinds of functions of ranging, needs the similarities and differences from two kinds of functions to start with, merges as far as possible
The calculation step of the two, economizes on resources and power consumption, constructs intensive system.
It is that frequency spectrum resource is big that an advantage of signal transmission is carried out using laser as medium, and signal transmission rate is high.But phase
A problem of Ying Ersheng is that receiver processing speed also will be promoted significantly therewith.The system symbol rate that the present invention designs can
To reach Gbps rank, the sampling rate of analog-digital converter (ADC) needs to meet Nyquist's theorem (the i.e. sample frequency of ADC
At least 2 times of signal frequency) transmitted symbol can just be sampled, the signal after sampling is each even across serioparallel exchange
The processing clock of road signal also reaches up to a hundred megahertzs, and traditional synchronous method is difficult to synchronize the signal of such high-speed；
In addition, when the relative motion rate (dynamic rate) between satellite and earth station it is big to a certain extent when, the Doppler that causes
Effect will bring big frequency shift (FS), can not also synchronize to signal, this but also receiver is unable to complete ranging and communication,
Therefore a kind of speed receiver and method of reseptance are proposed to solve this problem, wherein signal high-speed synchronous is this high quick access
The core technology of receipts machine and method of reseptance.
Summary of the invention
In view of the above problems, the invention proposes one of laser communication ranging integral system speed receiver and its
Method.The thinking for the laser communication ranging integral system speed receiver that the present invention designs is to be turned using high-speed ADC to photoelectricity
Reception signal after changing is sampled, and sampled data, which switchs to multidiameter delay data by high speed serial parallel exchange interface, (reduces every road
Data processing speed mitigates clock burden), the synchronizing device in speed receiver carries out precise synchronization to parallel data, in turn
It can calculate and receive signal delay, to calculate distance measurement value；Made simultaneously with the code phase of phaselocked loop digital controlled oscillator output
To do interpolation, demodulation according to reception signal, the communication information is extracted, completes laser communication ranging integral system high speed since then
The design of receiver.Specifically, a kind of synchronizing device of laser communication ranging integral system, including
Parallel capture circuit: signal arrival time is searched for using parallel computation mode, is captured as a result, realizing signal
It is thick synchronous；Dynamic calibration circuit: correcting the frequency shift (FS) of Doppler effect bring by Fast Fourier Transform (FFT) algorithm,
Export the mark and result of dynamic calibration；And high speed tracking circuit: with integral remove operation on the basis of parallel capture into
One step reduces local code sequence and receives the code phase difference of sequence, realizes the precise synchronization of signal；The parallel capture circuit will
Capture result is sent to the dynamic calibration circuit and high speed tracking circuit, and the dynamic calibration circuit is defeated by the mark of dynamic calibration
Parallel capture circuit is given, the result of dynamic calibration is output to high speed tracking circuit.
Further, the parallel capture circuit includes for storing the register group (Reg0) and storage number that receive data
According to the local code sequential register (Reg1) of frame frame alignment word sampled value, the data that are stored in the data and Reg0 that are stored in Reg1
Related operation and comparison operation are carried out using n stage pipeline structure, sentenced by comparing the peak value of one group of related operation with preset
Certainly thresholding size determines the capture result in the clock cycle.
Further, the dynamic calibration circuit is to the frame alignment word (N for being added in data frame1Bit) with data field (N3bit)
Between one section the periodic sequence (N that forms is recycled by binary number " 1 ", " 0 "2Bit FFT) is carried out, is found in FFT operation result
The position m of peak point, measures the frequency shift (FS).
Further, the catch position that the high speed tracking circuit is slightly synchronized according to the parallel capture circuit, benefit
With the data that 3 periods receive before this period to this period, advanced branch E, instant branch I and lag branch L are extracted
Data, with local code table generate local code sequence carry out integral remove operation；The extraction position of the instant branch I is just
It is aligned with catch position, the super previous Baud Length of the advanced more instant branch I of branch E, the lag branch L is propped up more immediately
The stagnant the latter Baud Length of road I, the frame alignment word of the local code table store frames of data.
Further, the capture result of the parallel capture circuit is acquisition success or capture failure, works as comparison operation
When the correlation peak of appearance is greater than default decision threshold, capture result is acquisition success, while recording the position of relevant peaks appearance
It sets, when the correlation peak that comparison operation occurs is not more than default decision threshold, capture result is capture failure.
Further, the Reg0 in the parallel capture circuit at least stores 2M × N1A reception data, each clock week
Phase is by M × N of high address1A data remove Reg0；Low M × N1A data are to high M × N1Address polishing；M × the N newly to arrive1It is a
Data are stored in low M × N1In a address；Wherein, M is the ratio between sample frequency and signal rate, N1It is the frame synchronization of data frame frame head
Word bit number.
Further, in the related operation of the parallel capture circuit, each period carries out M × N1Group related operation, often
Group related operation can generate M × N first1A dot product adds up dot product result as a result, reusing n stage pipeline structure；Institute
It states in comparison operation, using n stage pipeline structure to M × N1The result of group related operation carries out size comparison, exports maximum
That correlated results and its corresponding position；Wherein, M is the ratio between sample frequency and signal rate, N1It is the frame of data frame frame head
Synchronous word bit number, M × N1=2n。
Further, the dynamic calibration circuit is after the completion of parallel capture, to N2Bit periodic sequence extracts fixed value
After the sampled point at interval, then FFT operation is carried out, the position m of peak point is found in operation result, it is inclined that measurement obtains the frequency
It movesCalculating bit rate rate variance as caused by dynamic effects isIts
In, fclkIndicate that clock frequency is, p indicates sampling interval points, and q indicates FFT operation points, RSIndicate that character rate, % indicate
Complementation, by result Δ RSDeviation frequency can be compensated by being sent into high speed tracking circuit.And then it usesTo mesh
Mark relative motion rate is estimated that wherein c indicates the light velocity under vacuum.
Further, the integral of advanced branch E, instant branch I and lag branch L are removed knot by the high speed tracking circuit
Fruit CE, CI, CL input phase discriminator, and phase demodulation value eck, eck is calculated and obtains code phase controlling increment Δ after filter filtering
FTW calculates the relevant parameter of next frame, including code phase control word, code initial phase, data frame length and data-frame sync word
It is long, the code phase control word being calculated, code initial phase and data-frame sync word are sent into local code table, local code table produces
Raw new code sequence；The data frame length being calculated is subjected to delay calculating, next frame frame alignment word is calculated and goes out needed for current moment
After delay cycle number, next frame is waited to arrive, the frame alignment word data for the new code sequence and next frame that local code table generates are done
Integral removes operation, opens next round signal trace.
Further, the phase change of the high speed tracking instant branch I of circuit real-time tracking, and adjust local code table
Output, approaches the phase of its output code sequence gradually to instant branch, until locking.
The invention also provides a kind of synchronous method of laser communication ranging integral system, comprising the following steps:
Step 1: being fed through parallel capture circuit for parallel data, carries out signal capture, local code sequence and it is received simultaneously
Row data do parallel related operation, obtain correlation result, if the maximum value in correlation result is greater than default decision gate
Limit, then acquisition success, records catch position, and output " first time acquisition success " mark stops capturing and carries out step 2, if phase
The maximum value closed in operation result is not more than default decision threshold, then captures failure, then update the reception signal of input, continue into
Row step 1 is until acquisition success；
Step 2: dynamic calibration circuit detects that " first time acquisition success " indicates, starts to carry out dynamic calibration, by right
Have between frame alignment word and data field in data frame by " 1 ", the periodic sequence of " 0 " circulation composition carries out Fast Fourier Transform
(FFT) or to having between frame alignment word and data field in data frame by " 1 ", the periodic sequence of " 0 " circulation composition is adopted
FFT is carried out after sample again, corrects Doppler effect bring frequency shift (FS) fd, " dynamic calibration completions " mark is issued to being caught parallel
Circuit is obtained, output dynamic calibration result tracks circuit to high speed, carries out step 3；
Step 3: after parallel capture circuit detects " dynamic calibration completion " mark, it will be again started up capture operation, when catching
When succeeding, catch position is recorded, output " capture is completed " mark stops capturing and carries out step 4；If capture failure, after
It is continuous to carry out step 3 until capture is completed；
Step 4: high speed tracking circuit is according to the dynamic calibration for receiving dynamic calibration circuit as a result, correcting local code table
Initial rate control word；After " capture complete " mark for detecting parallel capture circuit output, then with integral removing operation
Local code sequence is further reduced on the basis of parallel capture and receives the code phase difference of sequence, progress signal trace, one
After the completion of the signal trace of cycle period, continue step 4, reception signal is tracked in real time, until tracking occurs
Abnormal losing lock causes to receive system reset, comes back to step 1 and carries out signal capture again.
The invention also provides the speed receivers in a kind of laser communication ranging integral system, including analog-digital converter
(ADC): the analog signal received is converted into digital signal；Gigabit transceiver (GTH): the digital signal of ADC is carried out
Serioparallel exchange；Synchronizing device: the parallel signal of GTH output is subjected to parallel data frame-grab, dynamic calibration and high-speed phase-locked loop
It is synchronous to complete signal for tracking；Ranging branch: range measurement is realized by the synchronization signal that synchronizing device obtains；And communication branch
Road: realize that communication data resolves by the synchronization signal that synchronizing device obtains.
Further, using preceding feature in the speed receiver in the laser communication ranging integral system
Synchronizing device.
The beneficial technical effect of the present invention is as follows:
1., using n stage pipeline structure, the processing that can mitigate clock is negative in the parallel capture circuit of synchronizing device
Load, while reducing requirement of the system to hardware circuit timing.
2. the dynamic calibration circuit in synchronizing device can eliminate the influence of big dynamic rate bring Doppler effect,
Effectively increase the synchronous precision of signal.
3. the local code table in high speed tracking circuit, adjustable minimum phase are Ts/2wid_NCO(TsFor a symbol
Length, wid_NCO are that local code table quantization is wide), the synchronous precision of signal has also been effectively ensured in this.
Detailed description of the invention
Fig. 1 is speed receiver structure chart；
Fig. 2 is parallel capture processing method schematic diagram；
Fig. 3 is the pipeline organization figure of related operation；
Fig. 4 is the pipeline organization of comparison operation；
Fig. 5 is the process flow diagram of dynamic calibration；
Fig. 6 is the process flow diagram of high speed tracking；
Fig. 7 is the synchronous Matlab emulation aircraft pursuit course of signal；
Fig. 8 is the signal synchronized tracking curve that the FPGA of Modelsim crawl is realized.
Specific embodiment
With reference to the accompanying drawing, technical solution of the present invention is described further.
Speed receiver structure proposed by the present invention is as shown in Figure 1.A kind of height in laser communication ranging integral system
Fast receiver, including analog-digital converter (ADC): the analog signal received is converted to digital signal；Gigabit transceiver
(GTH): the digital signal of ADC is subjected to serioparallel exchange；Synchronizing device: the parallel signal of GTH output is subjected to parallel data frame
Capture, dynamic calibration and high-speed phase-locked loop tracking, it is synchronous to complete signal；Ranging branch: the synchronous letter obtained by synchronizing device
Number realize range measurement；And communication leg: realize that communication data resolves by the synchronization signal that synchronizing device obtains.Receive letter
Number treatment process are as follows: the analog signal received is sampled through ADC, obtains digital signal；The digital signal of sampling is sent into lucky ratio
Serioparallel exchange is carried out in special transceiver (GTH)；It is same that the parallel data obtained after GTH serioparallel exchange completes signal in synchronizing device
Step；Signal after synchronizing is sent into ranging branch and communication leg completes range measurement and communication data resolves.
The precise synchronization of signal is the basis of ranging and communication, therefore synchronizing device and synchronous method are that the present invention proposes to swash
The core of receiver and method of reseptance in optic communication ranging integral system.Synchronizing device carries out input parallel signal parallel
Data frame-grab, dynamic calibration and high-speed phase-locked loop tracking, when input signal is phase locked ring tracking lock, receiver is just completed
To the precise synchronization for receiving signal.For the synchronous effect reached, a kind of data frame data format is had also been devised in the present invention,
Specifically: frame alignment word (N1Bit)+" 1 ", " 0 " alternate data (N2Bit)+data field (N3Bit), wherein N2Bit " 1 ", " 0 " are handed over
It for data is added to measure Doppler shift.In speed receiver, synchronizing device is by parallel capture circuit, dynamic
Correcting circuit and high speed tracking circuit three parts composition, are separately below described in detail these three circuits.
Parallel capture circuit searches for signal arrival time using parallel computation mode, realizes the thick synchronization of signal.Every number
N is used according to frame head portion1(under conditions of M sampling, M is the ratio between sample frequency and signal rate to bit, is equivalent to M × N1It is a to adopt
Sampling point) synchronization character, as long as synchronous word location, which can be accurately positioned, can be completed search to signal arrival time.Parallel capture
Process flow can store 2M × N as shown in Fig. 2, being arranged one first1(for convenience of operation, limit M × N1=2n, n is positive whole
Number) a data register group (Reg0), for storing reception data, it is (2M × N that address, which is compiled,1- 1)~0, initial value is all 0.It connects
The mode for receiving data deposit Reg0 is first in, first out, i.e., each clock cycle is by M × N of high address1A data remove Reg0；It is low
M×N1A data are to high M × N1Address polishing；M × the N newly to arrive1A data are stored in low M × N1In a address.Local code sequence
The sampled value of register (Reg1) store frames of data frame alignment word, be used for and receive signal carry out related operation, due to it is each when
It will be updated M × N in clock period Reg01A data, therefore M × N will be completed in a clock cycle1The capture of a Data Position,
Namely M × N1Group related operation.
To reduce influence of a large amount of operations to system velocity, related operation (Fig. 3) and comparison operation (Fig. 4) process are all made of
N stage pipeline structure.In related operation shown in Fig. 3, each period carries out M × N1Group related operation, every group of related operation
M × N can be generated first1A dot product adds up dot product result as a result, reusing n stage pipeline structure.First level production line
In operation, number dot product by turn in Reg0 per adjacent two numbers and Reg1, results added, M × N1/ 2 groups of add operations generate M
×N1/ 2 accumulation results, are transferred to the second level production line；Second level production line is with the operation result of the first level production line
For input, make to be added per two adjacent accumulation results, M × N1/ 4 groups of add operations generate M × N1/ 4 accumulation results, and will
It sends third level production line to；And so on, until the n-th level production line only remains two accumulation results as input, by this two
A accumulation result is added, and obtains the final result of this group of related operation.Similarly, it in comparison operation shown in Fig. 4, also uses
N stage pipeline structure is to M × N1The size of group correlated results is compared, to adjacent correlated results ratio in each level production line
Compared with size, that bigger correlated results is delivered to next stage, two correlated results are only remained until n-th grade, by that bigger
A correlated results and its output of corresponding position.It can guarantee to carry out incessantly reception signal using n stage pipeline structure
Capture, Real-time Feedback capture result.When the correlation peak that one group of operation occurs is greater than default decision threshold, it was demonstrated that acquisition success
And record the position of relevant peaks appearance；Conversely, then proving capture failure, new data will be used to continue to capture operation.
Dynamic calibration circuit is for correcting Doppler effect bring frequency shift (FS).The process flow of dynamic calibration circuit is such as
Shown in Fig. 5, in data frame format, one section is added between frame alignment word and data field by binary number " 1 ", " 0 " circulation group
At periodic sequence (101010 ... 10) correspond at frequency point in a frequency domain poly- since this section of sequence has good periodicity
Collection property is good, and the method that Fast Fourier Transform (Fast Fourier Transform, FFT) can be used measures its frequency deviation.Due to
Sample frequency is very high, to obtain higher frequency deviation measurement precision, needs to take very long sequence to be FFT, but long sequence FFT ten
Divide consumption resource, and mass data domain can be occupied, so following method is taken to complete frequency shift (FS) operation: being completed in parallel capture
Afterwards, dynamic calibration circuit starts to extract sampled point in this section of sequence, is divided into fixed value between extraction.When being drawn into enough adopt
After sampling point, FFT operation is carried out to these sampled points, the position m of peak point is found in operation result frequency spectrum.Assuming that sampling clock
Frequency is fclk, sampling interval points are p, and FFT operation points are q, then frequency shift (FS)Bit rate is due to dynamic
Rate variance caused by influenceRSIndicate character rate, % indicates complementation, by result Δ RS
Deviation frequency can be compensated by being sent into high speed tracking circuit.And then it usesTarget relative movement rate is carried out
Estimation, wherein c indicates the light velocity under vacuum.
High speed tracking circuit realizes the precise synchronization of signal, and local code sequence is further reduced on the basis of parallel capture
With the code phase difference for receiving sequence.The process flow of high speed tracking circuit is as shown in fig. 6, high speed tracking circuit each the past in period
Grade receives M × N1A data store 3 periods before this period to this period using shift register in a manner of first in, first out
The data received, then extracted simultaneously from register according to slightly synchronous catch position advanced branch E, instant branch I and
Lag branch L (the extraction position of instant branch I is just aligned with catch position, and advanced branch E and lag branch L respectively compared with
Instant one Baud Length of branch I lead and lag) data and the local code table (frame synchronization of local code table store frames of data
Word) generate local code sequence carry out integral remove operation.
Data frame only has frame alignment word part to remove operation for carrying out integral, therefore the time for integrating removing is frame synchronization
Word sequence time duration, remaining time can be used to carry out subsequent arithmetic processing.Since every frame remaining time is more abundant, from section
Resource-saving angle is set out, and the mode that sequence executes can be used in subsequent arithmetic: integrating 3 tunnels remove result C firstE、CI、CLInput
Phase discriminator is calculated phase demodulation value eck, eck and obtains code phase controlling increment Δ FTW after filter filtering, joins to it
Number calculates, and calculates the relevant parameter of next frame, including code phase control word, code initial phase, data frame length and data frame are same
Walk word length.The code phase control word being calculated, code initial phase and data-frame sync word are sent into local code table, local code
Table generates new code sequence；The data frame length being calculated is subjected to delay calculating, next frame frame alignment word is calculated and goes out current moment
After required delay cycle number, next frame is waited to arrive, the frame synchronization number of words for the new code sequence and next frame that local code table generates
Operation is removed according to integral is done, opens next round signal trace.It loops back and forth like this, high speed tracks the instant branch of circuit real-time tracking
Phase change, and adjust the output of local code table, approach the phase of its output code sequence gradually to instant branch, until lock
It is fixed.
The chip rate of laser communication ranging integrated system transmission data is set as 4.976Gbps, target is relatively radially transported
Dynamic speed reaches 4km/s.Speed receiver ADC sampling rate is 10Gsps, and the data after sampling are gone here and there and turned by GTH
It changes, is converted to 64 channel parallel datas, while clock frequency is reduced to the 1/64 of former clock, i.e. 156.25MHz.Since ADC samples speed
Rate is approximately equal to 2 times of chip rate, therefore local code sequence length is set as 64 sampled points.The data rate of each circuit-switched data is
77.75Mbps.The data format of data frame are as follows: frame alignment word (32bit)+" 1 ", " 0 " alternate data (832bit)+data field
(7328bit), frame alignment word select 0x1ACFFC1D.In order to obtain accurate distance measurement result and extract the communication information, now want
The high speed signal to ADC acquisition is asked to carry out precise synchronization.High-speed synchronous method is realized by following steps:
Step 1: sending 64 channel parallel datas into parallel capture circuit, search for frame alignment word arrival time, carries out signal and catches
It obtains.64 channel parallel datas that local code sequence and each period update do parallel related operation, obtain correlation result, if this
Maximum value in 64 correlation results is greater than default decision threshold, then it is assumed that acquisition success records correlation peak location, defeated
" first time acquisition success " indicates out, and carries out step 2, and otherwise, capture failure updates the reception signal of input, continues
Step 1 is until acquisition success.
Step 2: dynamic calibration circuit detects that " first time acquisition success " indicates, it will opens dynamic calibration.In data
In frame structure, there is 832bit by " 1 ", the sequence of " 0 " circulation composition, dynamic calibration circuit between frame alignment word and data field
This section of sequence of data frame will be sampled, every frame takes out 1 point, 2048 points are continuously extracted from 2048 data frames,
Zero padding is FFT to 8192 points, obtains dynamic frequency offset fd, resolution ratio is about 74.2Hz.Then dynamic calibration circuit issues
" dynamic calibration completion " mark, and dynamic calibration result is sent into high speed tracking circuit, correct the initial bit rate of local code table
Control word (FTW0), signal is faster locked when to track, carries out step 3.
Step 3: after parallel capture circuit detects " dynamic compensation is completed " mark, it will be again turned on capture operation.By
Longer in dynamic compensation process, catch position when first time acquisition success has lost meaning for high speed tracking circuit
Justice, therefore second of signal capture is carried out after dynamic compensates.When acquisition success, catch position is recorded, output " has captured
At " mark, stop capturing and carries out step 4；Otherwise, continue step 3 until capture is completed.
Step 4: after high speed tracking circuit detects " capture is completed " mark, will start to track signal.Root first
Instant branch I, advanced branch E and lag branch L are extracted according to catch position, local code table is by corrected initial code phase positions
Control word (FTW0) generation local code sequence is controlled, local code sequence carries out integral removing with the data of three branches respectively, and
Three tunnels are integrated and remove result progress phase demodulation, identified result is sent into loop filter, is filtered using second order Jaffe-Rechtin
Algorithm filters it, obtains final code phase controlling increment (Δ FTW).Code phase controlling increment (Δ FTW) and initial code phase
Position control word (FTW0) stack up, obtain new code phase control word (FTWn).On the basis of new code phase control word,
Continue to calculate the prediction long to next frame code initial phase, data frame length and data frame head, wherein at the beginning of code phase control word, code
Beginning phase and data-frame sync word will instruct local code table to generate new local code sequence；And data frame length will be used under prediction
The initial position of one frame is instructed in subsequent cycle periodicity extraction new instant branch I, advanced branch E and lag branch L.Continue
Step 4 is carried out, and thus circulation is gone down, causes to receive system reset until abnormal losing lock occurs in tracking, come back to step 1
Carry out signal capture again, thus realize track loop to the real-time tracking of signal phase with it is synchronous.
As shown in Figure 7 and Figure 8, it is 4.976Gbps, system high-speed receiver that this, which is the chip rate for transmitting data in system,
Matlab emulation aircraft pursuit course (Fig. 7) synchronized in the case that ADC sampling rate is 10Gsps to signal and base
The aircraft pursuit course (Fig. 8) realized in FPGA.Square, diamond shape and five-pointed star in figure respectively indicate advanced, instant and lag three
The integral of branch removes result curve as seen from the figure, and after tracking after a period of time, three roads integral removes result will
It tends towards stability, advanced, lag two-way result levels off to identical, and branch will be far longer than advanced, lag two-way integral immediately
It removes as a result, this illustrates that loop has entered lock.
Table 1 is the verifying to dynamic calibration circuit function.It is listed respectively in table whether there is or not when dynamic calibration, synchronizing device pair
The deviation that high speed signal synchronizes, it is as can be seen from Table 1, how general when target relative radial rate reaches certain numerical value
Synchronizing for signal can be affected by strangling the frequency shift (FS) of effect bring, if not doing dynamic calibration, signal can not be stablized into lock.
Dynamic calibration circuit can correct Doppler effect bring frequency shift (FS), even if when dynamic speed is very big, it can also basis
The movement rate of target is adjusted, so that synchronism deviation amount maintains to a very small extent.
Whether there is or not dynamic calibrations on synchronism deviation influence comparison for table 1
It is possible thereby to verify the laser communication ranging integral system high speed comprising dynamic calibration circuit that the present invention designs
Receiver can carry out precise synchronization and reception to high transfer rate signal under high dynamic environment, be laser communication ranging one
Change system provides powerful guarantee.
Claims (6)
1. a kind of synchronizing device of laser communication ranging integral system, comprising:
Parallel capture circuit: searching for signal arrival time using parallel computation mode, is captured as a result, realizing the thick same of signal
Step；The parallel capture circuit includes for storing the register group Reg0 and the sampling of store frames of data frame alignment word that receive data
The data stored in the data and Reg0 stored in local code the sequential register Reg1, Reg1 of value use n stage pipeline structure
Related operation and comparison operation are carried out, peak value and preset decision threshold size by comparing one group of related operation, determination are worked as
Capture result in the preceding clock cycle；The capture result is acquisition success or capture failure, when the phase that comparison operation occurs
When closing peak value and being greater than default decision threshold, capture result is acquisition success, while recording the position that relevant peaks occur, when comparing
When the correlation peak that operation occurs is not more than default decision threshold, capture result is capture failure；
Dynamic calibration circuit: by fft algorithm correct the frequency shift (FS) of Doppler effect bring, export dynamic calibration mark and
As a result；The dynamic calibration circuit is to the N for being added in data frame1Bit frame alignment word and N3Between bit data field one section by binary system
The N of number " 1 ", " 0 " circulation composition2Bit periodic sequence carries out FFT, and the position m of peak point is found in FFT operation result, measures
The frequency shift (FS)；The dynamic calibration circuit is after the completion of parallel capture, to N2It is interval that bit periodic sequence, which extracts fixed value,
Sampled point after, then carry out FFT operation, the position m of peak point found in operation result, measurement obtains the frequency shift (FS)Calculating bit rate rate variance as caused by dynamic effects isIts
In, fclkIndicate that clock frequency is, p indicates sampling interval points, and q indicates FFT operation points, RSIndicate that character rate, % indicate
Complementation, by result △ RSDeviation frequency can be compensated by being sent into high speed tracking circuit, and then be usedTo mesh
Mark relative motion rate is estimated that wherein c indicates the light velocity under vacuum；
High speed tracking circuit: operation is removed with integral and further reduces local code sequence and Receiving Order on the basis of parallel capture
The code phase difference of column realizes the precise synchronization of signal；High speed tracking circuit is slightly synchronous according to the parallel capture circuit
The catch position arrived extracts advanced branch E, instant branch I using the data that 3 periods receive before this period to this period
With the data of lag branch L, the local code sequence generated with local code table carries out integral and removes operation；The instant branch I's
It extracts position to be just aligned with catch position, the super previous Baud Length of the advanced more instant branch I of branch E, the lag
The stagnant the latter Baud Length of the more instant branch I of branch L, the frame alignment word of the local code table store frames of data；The high speed with
The integral of advanced branch E, instant branch I and lag branch L are removed result CE, CI, CL and input phase discriminator by track circuit, are calculated
Code phase controlling increment Δ FTW is obtained after filter filtering to phase demodulation value eck, eck, calculates the relevant parameter of next frame, is wrapped
Code phase control word, code initial phase, data frame length and data-frame sync word length are included, the code phase being calculated is controlled
Word, code initial phase and data-frame sync word are sent into local code table, and local code table generates new code sequence；By what is be calculated
Data frame length carries out delay calculating and waits next frame to arrive after calculating next frame frame alignment word goes out delay cycle number needed for current moment
Come, the frame alignment word data for the new code sequence and next frame that local code table generates do integral and remove operation, open next round letter
Number tracking；
The parallel capture circuit will capture result and send to the dynamic calibration circuit and high speed tracking circuit, the dynamic calibration
The mark of dynamic calibration is exported and gives parallel capture circuit by circuit, and the result of dynamic calibration is output to high speed tracking circuit.
2. synchronizing device as described in claim 1, which is characterized in that the Reg0 at least stores 2M × N1A reception data, often
A clock cycle is by M × N of high address1A data remove Reg0；Low M × N1A data are to high M × N1Address polishing；It is new to arrive
M × N1A data are stored in low M × N1In a address；Wherein, M is the ratio between sample frequency and signal rate, N1It is data frame frame head
Frame alignment word digit.
3. synchronizing device as described in claim 1, which is characterized in that in the related operation, each period carries out M × N1Group
Related operation, every group of related operation can generate M × N first1A dot product is as a result, reuse n stage pipeline structure for dot product result
It adds up；In the comparison operation, using n stage pipeline structure to M × N1The result of group related operation carries out size comparison,
Export that maximum correlated results and its corresponding position；Wherein, M is the ratio between sample frequency and signal rate, N1It is data
The frame alignment word digit of frame frame head, M × N1=2n。
4. synchronizing device as described in claim 1, which is characterized in that the high speed tracks the instant branch I of circuit real-time tracking
Phase change, and adjust the output of local code table, approach the phase of its output code sequence gradually to instant branch, until lock
It is fixed.
5. a kind of synchronous method of laser communication ranging integral system, comprising the following steps:
Step 1: parallel data is fed through parallel capture circuit, carries out signal capture, local code sequence and received and line number
According to parallel related operation is done, correlation result is obtained, if the maximum value in correlation result is greater than default decision threshold,
Acquisition success records catch position, and output " first time acquisition success " mark stops capturing and carrying out step 2, if related fortune
It calculates the maximum value in result and is not more than default decision threshold, then capture failure, then update the reception signal of input, continue to walk
Rapid one until acquisition success；
Step 2: dynamic calibration circuit detects that " first time acquisition success " indicates, starts to carry out dynamic calibration, by data
Have between frame alignment word and data field in frame by " 1 ", the periodic sequence of " 0 " circulation composition carries out FFT or to frame in data frame
Have between synchronization character and data field by " 1 ", the periodic sequence of " 0 " circulation composition carries out FFT after being sampled again, how general corrects
Strangle effect bring frequency shift (FS) fd, issue " dynamic calibration completion " mark and give parallel capture circuit, export dynamic calibration result
Circuit is tracked to high speed, carries out step 3；
Step 3: after parallel capture circuit detects " dynamic calibration completion " mark, it will be again started up capture operation, when being captured as
When function, catch position is recorded, output " capture is completed " mark stops capturing and carries out step 4；If capture failure, continue into
Row step 3 is until capture is completed；
Step 4: high speed tracking circuit is according to the dynamic calibration for receiving dynamic calibration circuit as a result, correcting the first of local code table
Beginning rate control word；After " capture is completed " mark for detecting parallel capture circuit output, then with integral removing operation simultaneously
Local code sequence is further reduced on the basis of row capture and receives the code phase difference of sequence, carries out signal trace, a circulation
After the completion of the signal trace in period, continue step 4, reception signal is tracked in real time, until exception occurs in tracking
Losing lock causes to receive system reset, comes back to step 1 and carries out signal capture again.
6. the speed receiver in a kind of laser communication ranging integral system, including analog-digital converter: the simulation that will be received
Signal is converted to digital signal；Gigabit transceiver: the digital signal of analog-digital converter is subjected to serioparallel exchange；Synchronizing device:
The parallel signal that gigabit transceiver is exported carries out parallel data frame-grab, dynamic calibration and high-speed phase-locked loop tracking, completes
Signal is synchronous；Ranging branch: range measurement is realized by the synchronization signal that synchronizing device obtains；And communication leg: by same
The synchronization signal that step device obtains realizes that communication data resolves；The speed receiver is appointed using in such as Claims 1 to 4
Synchronizing device described in one claim.
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| CN108650047B (en) * | 2017-12-29 | 2020-02-21 | 北京时代民芯科技有限公司 | Serial data receiving real-time synchronous monitoring circuit and monitoring method |
| CN108599915A (en) * | 2018-03-12 | 2018-09-28 | 北京理工大学 | Based on number between the send-receive clock of closed loop phase ambiguity estimation and compensation method |
| US11585916B2 (en) | 2018-06-29 | 2023-02-21 | Apple Inc. | Ranging using beamforming antenna weight vectors and secure ranging packet with phase tracking |
| CN109660309B (en) * | 2018-12-26 | 2021-08-13 | 中国人民解放军63921部队 | Method for measuring clock error frequency difference of range speed by using bidirectional communication transmission frame synchronous code |
| CN110149197B (en) * | 2019-05-22 | 2021-12-07 | 北京睿信丰科技有限公司 | High-precision synchronization method and system for clock synchronization system |
| CN110505175B (en) * | 2019-06-05 | 2022-02-18 | 暨南大学 | Fast frame synchronization method and frame synchronization device |
| CN110351217A (en) * | 2019-08-02 | 2019-10-18 | 中国电子科技集团公司第五十四研究所 | A kind of non-cycle prefix is burst orthogonal frequency-division multiplex singal transmission method |
| CN110943747B (en) * | 2019-11-20 | 2022-03-04 | 北京无线电计量测试研究所 | Broadband microwave signal capturing method and system |
| CN110868239B (en) * | 2019-11-25 | 2022-03-04 | 北京无线电计量测试研究所 | Broadband microwave signal tracking method and system |
| CN111641490B (en) * | 2020-05-20 | 2021-07-09 | 中国人民解放军国防科技大学 | High-precision phase calibration and time reference determination method for sampling clock |
| CN112487354B (en) * | 2020-11-30 | 2022-10-04 | 北京航空航天大学 | Multi-channel high-speed real-time cross-correlation operation device based on comparator and FPGA |
| CN113791390B (en) * | 2021-08-31 | 2023-08-29 | 北京信息科技大学 | Radar communication integrated signal design method based on RS sequence and soft spread spectrum technology |
| CN116684001B (en) * | 2023-07-28 | 2023-10-03 | 中国科学院空天信息创新研究院 | Satellite laser communication frequency offset capturing and tracking method based on physical frame header |
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