CN206489205U - Reduce system, digit chip and the oscillograph of oscillograph external trigger waveform shake - Google Patents
Reduce system, digit chip and the oscillograph of oscillograph external trigger waveform shake Download PDFInfo
- Publication number
- CN206489205U CN206489205U CN201720141733.6U CN201720141733U CN206489205U CN 206489205 U CN206489205 U CN 206489205U CN 201720141733 U CN201720141733 U CN 201720141733U CN 206489205 U CN206489205 U CN 206489205U
- Authority
- CN
- China
- Prior art keywords
- external trigger
- signal
- clock
- waveform
- oscillograph
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The utility model discloses system, digit chip and the oscillograph of reduction oscillograph external trigger waveform shake, wherein, the system includes external trigger passage, comparison module and trigger control module.When selecting external trigger passage to be triggered, the signal that external trigger passage is exported is compared with comparative level by comparison module, the signal that external trigger passage is exported is converted to the external trigger signal of low and high level；K times of the external trigger clock that one frequency is system clock frequency is produced by trigger control module；According to the external trigger clock and external trigger signal, external trigger pulse signal is generated；K is more than 1.Because the frequency of external trigger clock is higher than system clock frequency so that oscilloscope sampling rate is uprised, and reduces the shake of waveform, improves the stability of waveform acquisition.
Description
Technical field
The utility model is related to oscillograph field, and in particular to a kind of system of reduction oscillograph external trigger waveform shake,
Digit chip and oscillograph.
Background technology
When carrying out modern electronic design, engineer is in the electronic signal in paying close attention to its design, needed for often occurring
The signal waveform number to be observed exceedes the situation of oscilloscope analog channel number, thus needs the trigger port choosing of oscillograph
It is selected as external trigger passage (compared with analog channel, the waveform of external trigger passage input can not be shown on oscillograph).External trigger
Function belongs to simulation triggering, when the trigger signal produced using external trigger passage controls waveform acquisition, reduces external trigger passage
The waveform shake brought, the stability for improving waveform acquisition is very important.
Measured signal is output to analog channel and external trigger passage simultaneously first in prior art.External trigger passage
The measured signal of input input gives digit chip after amplification coupling circuit is sent to external trigger analog comparator.Digital core
Piece using its internal phaselocked loop from from analog-digital converter (ADC) with system clock is recovered in the clock of road, to produce
Trigger pulse.The trigger pulse is sent in the external trigger pulse expanded circuit of outside sends back to digit chip after progress Linear expansion
In.The system clock that digit chip is worked using itself is counted to the pulse after Linear expansion, statistical value is converted to tactile
Send out corrected value.
Assuming that analog-digital converter ADC sample rate is Fc, the system clock cycle of digit chip is T, then digit chip is every
Individual system clock needs the number of parallel data to be processed to be M=Fc × T.And external trigger pulse expanded circuit can support in office
The multiple of linear expansion is fixed under what environment, it is assumed that be N times.Then understand resolution ratio R (each pulses of the expanded circuit
The number for the sampled point that measurement period can be represented) it is R=M ÷ N=Fc × T ÷ N.It was found from formula, when Fc is higher, R is got over
Greatly, that is to say, that the points of unit interval are more, i.e., resolution ratio is more coarse, the waveform shake brought is bigger.
Therefore, prior art has much room for improvement and improved.
Utility model content
The application provides a kind of system, digit chip and the oscillograph of the shake of reduction oscillograph external trigger waveform, passes through production
A raw frequency is K times of external trigger clock of system clock frequency, and external trigger pulse letter is produced according to the external trigger clock
Number, to improve oscilloscope sampling rate, so as to reduce the shake of waveform, improve the stability of waveform acquisition.
According to of the present utility model in a first aspect, the utility model provides what a kind of reduction oscillograph external trigger waveform was shaken
System, including：
External trigger passage, for receiving measured signal；
Comparison module, the signal for external trigger passage to be exported is compared with comparative level, and external trigger passage is exported
Signal is converted to the external trigger signal of low and high level；
Trigger control module, for producing K times of the external trigger clock that a frequency is system clock frequency；According to described
External trigger clock and external trigger signal, generate external trigger pulse signal；K is more than 1；
The output end of the external trigger passage connects trigger control module by comparison module.
The system of described reduction oscillograph external trigger waveform shake, wherein, the system also includes controlling with the triggering
The external trigger pulse expanded circuit of molding block connection, for carrying out Linear expansion to the external trigger pulse signal.
The system of described reduction oscillograph external trigger waveform shake, wherein, the trigger control module includes：
Phaselocked loop, for recovering system clock in the clock of road, and it to be described to produce a frequency from measured signal
The external trigger clock of K times of system clock frequency；
External trigger pulse generation unit, for according to the external trigger clock and external trigger signal, generating external trigger pulse
Signal is to control waveform acquisition；
Timeslice detection unit, for system clock cycle to be divided into K timeslice according to the external trigger clock, and is examined
Measure the timeslice residing for the time of origin of the external trigger pulse signal；
Pulse width statistic unit is extended, for the width of the external trigger pulse signal after statistically linear broadening, with reference to outer
Timeslice residing for start pulse signal obtains triggering corrected value, to carry out position correction to collection waveform；
The first input end of the external trigger output terminal of clock connection external trigger pulse generation unit of the phaselocked loop, timeslice
The first input end of detection unit and the first input end of extension pulse width statistic unit；The external trigger pulse generation unit
The second input connect comparison module output end, the external trigger pulse generation unit output end connection external trigger pulse
The input of expanded circuit and the second input of timeslice detection unit, the output end connection of the timeslice detection unit are expanded
Open up the second input of pulse width statistic unit, the output end connection extension pulse width of the external trigger pulse expanded circuit
3rd input of statistic unit.
The system of described reduction oscillograph external trigger waveform shake, wherein, the system also includes being serially connected in external trigger
External trigger passage amplification coupling circuit between passage and comparison module, gain is carried out for the signal that external trigger port is exported
Control and alternating current and direct current coupling.
The system of described reduction oscillograph external trigger waveform shake, wherein, the system also includes：
Analog channel, for receiving the measured signal；
Undulating path amplifies and termination power, carries out gain control and exchange for the signal that is exported to analog channel, straight
Stream coupling；
Analog-digital converter, for analog waveform signal to be converted into digital waveform signal；
The output end of the analog channel is amplified by undulating path and termination power connects the input of analog-digital converter,
The output end connection phaselocked loop of the analog-digital converter.
The system of described reduction oscillograph external trigger waveform shake, wherein, the trigger control module also includes：
ADC interface；
Down-sampled and memory module, the parallel data stream for being exported to ADC interface carries out down-sampled and/or storage；
The input of ADC interface connects the output end of analog-digital converter, and the output end connection of ADC interface is down-sampled and stores
Module, described down-sampled and memory module is also connected with the system clock output end of phaselocked loop.
The system of described reduction oscillograph external trigger waveform shake, wherein, the trigger control module includes digital core
Piece.
According to second aspect of the present utility model, the utility model provides a kind of digit chip, including：
Phaselocked loop, for recovering system clock in the clock of road, and producing a frequency from oscillograph measured signal
For K times of external trigger clock of the system clock frequency；
External trigger pulse generation unit, the external trigger signal for receiving outside input, according to the external trigger signal and
External trigger clock generates external trigger pulse signal to control waveform acquisition；
Timeslice detection unit, for system clock cycle to be divided into K timeslice according to the external trigger clock, and is examined
Measure the timeslice residing for the time of origin of the external trigger pulse signal；
Pulse width statistic unit is extended, for receiving the external trigger pulse signal after Linear expansion, and statistically linear exhibition
The width of external trigger pulse signal after width, the timeslice with reference to residing for external trigger pulse signal obtains triggering corrected value, with right
Gather waveform and carry out position correction；
External trigger output terminal of clock connection external trigger pulse generation unit, timeslice detection unit and the expansion of the phaselocked loop
Open up pulse width statistic unit；The external trigger pulse generation unit passage time piece detection unit connection extension pulse width system
Count unit.
Described digit chip, wherein, the digit chip also includes：
ADC interface；
Down-sampled and memory module, the parallel data stream for being exported to ADC interface carries out down-sampled and/or storage；
The output end of ADC interface connects down-sampled and memory module, and described down-sampled and memory module is also connected with phaselocked loop
System clock output end.
According to the third aspect of the present utility model, the utility model provides a kind of oscillograph, including reduction as described above
The system of oscillograph external trigger waveform shake, or, including digit chip as described above.
The beneficial effects of the utility model：When the utility model selection external trigger passage is triggered, pass through comparison module
The signal that external trigger passage is exported is compared with comparative level, and the signal that external trigger passage is exported is converted to the outer of low and high level
Trigger signal；K times of the external trigger clock that one frequency is system clock frequency is produced by trigger control module；According to described outer
Clock and external trigger signal are triggered, external trigger pulse signal is generated；K is more than 1.Because the frequency of external trigger clock compares system clock
Frequency is high so that oscilloscope sampling rate is uprised, and reduces the shake of waveform, improves the stability of waveform acquisition.
Brief description of the drawings
The structured flowchart of the system for the reduction oscillograph external trigger waveform shake that Fig. 1 provides for the utility model；
In the system for the reduction oscillograph external trigger waveform shake that Fig. 2 provides for the utility model, system clock, external trigger
The waveform diagram of external trigger signal after clock, external trigger signal and broadening；
The structured flowchart for the digit chip that Fig. 3 provides for the utility model.
Embodiment
The utility model is described in further detail below by embodiment combination accompanying drawing.
In the utility model embodiment, by providing a kind of oscillograph, it includes reduction oscillograph external trigger waveform and trembled
Dynamic system, the system by producing an external trigger clock Fe, the external trigger clock phaselocked loop inside digit chip more
Fe frequency is K times of system clock, and K is more than 1, and external trigger pulse signal and extension arteries and veins are produced using the external trigger clock Fe
The statistics of width is rushed, and records the timeslice position of external trigger pulse signal place system clock cycle, the two is combined,
Obtain triggering corrected value.Wait the frame data collection finish after, using trigger corrected value to collection waveform carry out position correction,
It is finally shown on screen.Because the frequency of external trigger clock is higher than system clock frequency so that oscilloscope sampling rate is uprised, drop
The low shake of waveform, improves the stability of waveform acquisition.
Fig. 1 is refer to, what the utility model was provided reduces the system that oscillograph external trigger waveform is shaken, including：External trigger
Passage, analog channel, external trigger passage amplification coupling circuit 10, comparison module 20, trigger control module 40, external trigger pulse expand
Open up circuit 30, undulating path amplification and termination power 50 and analog-digital converter 60.External trigger passage and analog channel are used to connect
Receive measured signal.
Comparison module 20, the signal for external trigger passage to be exported is compared with comparative level, and external trigger passage is exported
Signal be converted to the external trigger signal of low and high level.
Trigger control module 40, for producing K times of the external trigger clock Fe that a frequency is system clock Fs frequencies；Root
According to the external trigger clock and external trigger signal, external trigger pulse signal is generated；K is more than 1；It is preferred that, K is just whole more than 1
Number.
The output end of external trigger passage connects trigger control module 40 by comparison module 20.
Because external trigger clock Fe frequency of the frequency than system clock Fs is high so that oscilloscope sampling rate is uprised, reduction
The shake of waveform, improves the stability of waveform acquisition.
External trigger passage amplification coupling circuit 10 is serially connected between external trigger passage and comparison module 20, for external trigger
The signal of passage output carries out gain control and alternating current and direct current coupling, the i.e. signal for being exported to oscillograph external trigger passage
It is amplified and couples.
External trigger pulse expanded circuit 30 is connected with trigger control module 40, is carried out for external start pulse signal linear
Broadening (Linear Amplifer), is additionally operable to before external trigger is started, and first carries out external trigger pulse expanded circuit Linear Amplifer region school
Just, it is ensured that line of the pulse of the distribution (0~T/K) produced by trigger control module 40 in external trigger pulse expanded circuit 30
In property magnification region.
Undulating path amplifies and termination power 50, for the signal that is exported to analog channel carry out gain control and exchange,
Dc-couple；It is used to the signal that oscilloscope analog passage is exported is amplified and coupled.
Analog-digital converter (ADC) 60, for realizing analog signal sample quantization function, i.e. analog waveform signal is changed
For digital waveform signal.
The output end of analog channel is amplified by undulating path and termination power 50 connects the input of analog-digital converter 60,
The output end connection trigger control module 40 of analog-digital converter 60.
Further, trigger control module 40 is included in digit chip, the present embodiment, and trigger control module 40 is digital core
Piece.Trigger control module 40 includes：
Phaselocked loop 430, for realizing clock division and double frequency function, specifically, from measured signal with extensive in the clock of road
Appear again system clock Fs, and produces K times of the external trigger clock Fe that a frequency is the system clock frequency.Compared to existing skill
Art, phaselocked loop more than 430 produces an external trigger clock Fe, it is assumed that the cycle of system clock is T, then external trigger clock Fe cycle
For T/K, it is easy to external trigger pulse generation unit 440 and external trigger pulse signal is produced using the clock, and extension pulse is wide
Spend the statistics of 460 pairs of extension pulse widths of statistic unit.
External trigger pulse generation unit 440, for according to the external trigger clock Fe and external trigger signal, generating external trigger
Pulse signal is to control waveform acquisition.
Timeslice detection unit 450, for system clock cycle to be divided into K time according to the external trigger clock Fe
Piece, i.e., each external trigger clock cycle is 1 timeslice, and is detected residing for the time of origin of the external trigger pulse signal
Timeslice.Which timeslice is timeslice detection unit 450 be located at by detecting record external trigger pulse signal, and by record
Timeslice information gives that extension pulse width statistic unit 460 below is further to be handled.
Pulse width statistic unit 460 is extended, for the width of the external trigger pulse signal after statistically linear broadening, and will
It is transformed into trigger position up, i.e., the timeslice with reference to residing for external trigger pulse signal obtains triggering corrected value, with to collection
Waveform carries out position correction.
The first input end of the external trigger output terminal of clock connection external trigger pulse generation unit 440 of phaselocked loop 430, time
The first input end of piece detection unit 450 and the first input end of extension pulse width statistic unit 460；External trigger pulse is generated
Second input of unit 440 connects the output end of comparison module 20, and the output end connection of external trigger pulse generation unit 440 is outer
The input of trigger pulse expanded circuit 30 and the second input of timeslice detection unit 450, timeslice detection unit 450
Second input of output end connection extension pulse width statistic unit 460, the output end of external trigger pulse expanded circuit 30 connects
Connect the 3rd input of extension pulse width statistic unit 460.
ADC interface 410, receives the highspeed serial data stream from analog-digital converter and is converted to the parallel data of low speed
Stream.
Down-sampled and memory module 420, various sample rate functions and data storage function for realizing oscillograph, i.e.
Down-sampled and/or storage is carried out to the parallel data stream that ADC interface 410 is exported.
The input of ADC interface 410 and the input of phaselocked loop 430 are all connected with the output end of analog-digital converter 60, and ADC connects
The output end of mouth 410 connects down-sampled and memory module 420, the system that down-sampled and memory module 420 is also connected with phaselocked loop 430
Output terminal of clock.
In the utility model, when system clock cycle is divided into K timeslice, i.e. each external trigger by trigger control module 40
The clock cycle is 1 timeslice, and the number of the corresponding parallel data of each timeslice is Mnew=Fc × T ÷ K.With prior art phase
Than the utility model produces external trigger pulse signal using external trigger clock Fe, it is known that the distribution of pulse is 0<TRO<T
÷K.It is assumed that the multiple of the linear expansion of external trigger pulse expanded circuit 30 is N, then expanded circuit of the present utility model resolution ratio
Rnew (number for the sampled point that each pulse measurement period can be represented) is：
Rnew=(Mnew) ÷ N=Fc × T ÷ K ÷ N=(Fc × T) ÷ (K × N)；
The R and Rnew expression formulas of the present utility model contrasted in background technology is understood, in the utility model, each pulse
The number of sampled point represented by measurement period is changed into original 1/K, with prior art ratio, and resolution ratio improves K times, will
Greatly reduce the shake of waveform.The timeslice X that external trigger pulse occurs is passed into follow-up extension pulse width simultaneously to unite
Unit 460 is counted, triggering is parsed along the particular location for being located at system clock cycle by it.
Also referring to Fig. 2, the system that the utility model is provided will first carry out external trigger pulse before external trigger is started
The Linear Amplifer region of expanded circuit 30 is corrected, it is ensured that the distribution (0~T/K) produced by external trigger pulse generation unit 440
Pulse in the Linear Amplifer region of external trigger pulse expanded circuit 30.Then according to waveform collecting flowchart, start
Waveform acquisition, after pre-trigger position is met, waits the external trigger signal TR for meeting setting condition, external trigger pulse generation unit
External trigger signal TR progress delays are changed into TRD by 440, then by TR and upper TRD low level, produce external trigger pulse signal
TRO.And then the external start pulse signal TRO of external trigger pulse expanded circuit 30 carries out Linear expansion, and by extension pulse width
Statistic unit 460 is extended the statistics of pulse width, while the timeslice of system clock cycle where recording external trigger pulse
Position, the two is combined, and obtains triggering corrected value.Wait after frame data collection finishes, using triggering corrected value pair
Gather waveform and carry out position correction, be finally shown on screen.External trigger pulse generation unit 440 carries out external trigger signal TR
The time delay of delay can be one or more external trigger clock cycle, be configured as needed, outer subsequently calculating again
Need to subtract unnecessary delayed clock during the real position of trigger pulse, system clock cycle where obtaining external trigger pulse
Timeslice position.
It follows that the utility model uses frequency to produce external trigger arteries and veins for F (F=K/T, T represent system clock cycle)
Signal is rushed, while the time that external trigger pulse signal is occurred and the position of its timeslice in a system clock cycle
Combine, obtain the triggering correction result of higher resolution.
In second embodiment of the present utility model, the utility model provides a kind of digit chip, referring to Fig. 3, digital
Chip includes：
Phaselocked loop 430, for recovering system clock in the clock of road, and producing a frequency from oscillograph measured signal
Rate is K times of external trigger clock of the system clock frequency.
External trigger pulse generation unit 440, the external trigger signal for receiving outside input, according to the external trigger signal
Generate external trigger pulse signal to control waveform acquisition with external trigger clock.
Timeslice detection unit 450, for system clock cycle to be divided into K timeslice according to the external trigger clock,
And detect the timeslice residing for the time of origin of the external trigger pulse signal.
Pulse width statistic unit 460 is extended, for receiving the external trigger pulse signal after Linear expansion, and it is statistically linear
The width of external trigger pulse signal after broadening, the timeslice with reference to residing for external trigger pulse signal obtains triggering corrected value, with
Position correction is carried out to collection waveform.
ADC interface 410, for receive the highspeed serial data stream from analog-digital converter and be converted to low speed and line number
According to stream.
Down-sampled and memory module 420, the parallel data stream for being exported to ADC interface carries out down-sampled and/or storage.
The external trigger output terminal of clock connection external trigger pulse generation unit 440 of the phaselocked loop 430, timeslice detection are single
Member 450 and extension pulse width statistic unit 460；440 passage time of the external trigger pulse generation unit piece detection unit 450
Connection extension pulse width statistic unit 460.
The output end of ADC interface 410 connects down-sampled and memory module 420, and down-sampled and memory module 420 is also connected with lock
The system clock output end of phase ring 430.
Because the digit chip in the present embodiment has been elaborated in a upper embodiment, it will not be repeated here.
Use above specific case is illustrated to the utility model, is only intended to help and is understood the utility model, and
Not to limit the utility model.For the utility model person of ordinary skill in the field, think according to of the present utility model
Think, some simple deductions, deformation can also be made or replaced.
Claims (10)
1. a kind of system for reducing the shake of oscillograph external trigger waveform, it is characterised in that including：
External trigger passage, for receiving measured signal；
Comparison module, the signal for external trigger passage to be exported is compared with comparative level, the signal that external trigger passage is exported
Be converted to the external trigger signal of low and high level；
Trigger control module, for producing K times of the external trigger clock that a frequency is system clock frequency；According to described outer tactile
Clock and external trigger signal are sent out, external trigger pulse signal is generated；K is more than 1；
The output end of the external trigger passage connects trigger control module by comparison module.
2. the system that reduction oscillograph external trigger waveform is shaken as claimed in claim 1, it is characterised in that the system is also wrapped
The external trigger pulse expanded circuit being connected with the trigger control module is included, it is linear for being carried out to the external trigger pulse signal
Broadening.
3. the system that reduction oscillograph external trigger waveform is shaken as claimed in claim 2, it is characterised in that the triggering control
Module includes：
Phaselocked loop, for recovering system clock in the clock of road, and it to be the system to produce a frequency from measured signal
The external trigger clock of K times of clock frequency；
External trigger pulse generation unit, for according to the external trigger clock and external trigger signal, generating external trigger pulse signal
To control waveform acquisition；
Timeslice detection unit, for system clock cycle to be divided into K timeslice according to the external trigger clock, and is detected
Timeslice residing for the time of origin of the external trigger pulse signal；
Pulse width statistic unit is extended, for the width of the external trigger pulse signal after statistically linear broadening, with reference to external trigger
Timeslice residing for pulse signal obtains triggering corrected value, to carry out position correction to collection waveform；
The first input end of the external trigger output terminal of clock connection external trigger pulse generation unit of the phaselocked loop, timeslice detection
The first input end of unit and the first input end of extension pulse width statistic unit；The of the external trigger pulse generation unit
Two inputs connect the output end of comparison module, the output end connection external trigger pulse extension of the external trigger pulse generation unit
The input of circuit and the second input of timeslice detection unit, the output end connection extension arteries and veins of the timeslice detection unit
Rush the second input of width statistic unit, the output end connection extension pulse width statistics of the external trigger pulse expanded circuit
3rd input of unit.
4. the system that reduction oscillograph external trigger waveform is shaken as claimed in claim 2 or claim 3, it is characterised in that the system
Also include the external trigger passage amplification coupling circuit being serially connected between external trigger passage and comparison module, for external trigger port
The signal of output carries out gain control and alternating current and direct current coupling.
5. the system that reduction oscillograph external trigger waveform is shaken as claimed in claim 3, it is characterised in that the system is also wrapped
Include：
Analog channel, for receiving the measured signal；
Undulating path amplifies and termination power, and the signal for being exported to analog channel carries out gain control and alternating current and direct current coupling
Close；
Analog-digital converter, for analog waveform signal to be converted into digital waveform signal；
The output end of the analog channel is amplified by undulating path and termination power connects the input of analog-digital converter, described
The output end connection phaselocked loop of analog-digital converter.
6. the system that reduction oscillograph external trigger waveform is shaken as claimed in claim 5, it is characterised in that the triggering control
Module also includes：
ADC interface；
Down-sampled and memory module, the parallel data stream for being exported to ADC interface carries out down-sampled and/or storage；
The input of ADC interface connects the output end of analog-digital converter, and the output end connection of ADC interface is down-sampled and stores mould
Block, described down-sampled and memory module is also connected with the system clock output end of phaselocked loop.
7. the system that reduction oscillograph external trigger waveform is shaken as claimed in claim 6, it is characterised in that the triggering control
Module includes digit chip.
8. a kind of digit chip, it is characterised in that including：
Phaselocked loop, for recovering system clock in the clock of road, and it to be institute to produce a frequency from oscillograph measured signal
State K times of external trigger clock of system clock frequency；
External trigger pulse generation unit, the external trigger signal for receiving outside input, according to the external trigger signal and it is outer touch
Hair clock generates external trigger pulse signal to control waveform acquisition；
Timeslice detection unit, for system clock cycle to be divided into K timeslice according to the external trigger clock, and is detected
Timeslice residing for the time of origin of the external trigger pulse signal；
Pulse width statistic unit is extended, for receiving the external trigger pulse signal after Linear expansion, and after statistically linear broadening
External trigger pulse signal width, the timeslice with reference to residing for external trigger pulse signal obtain trigger corrected value, with to collection
Waveform carries out position correction；
External trigger output terminal of clock connection external trigger pulse generation unit, timeslice detection unit and the extension arteries and veins of the phaselocked loop
Rush width statistic unit；The external trigger pulse generation unit passage time piece detection unit connection extension pulse width statistics is single
Member.
9. digit chip as claimed in claim 8, it is characterised in that the digit chip also includes：
ADC interface；
Down-sampled and memory module, the parallel data stream for being exported to ADC interface carries out down-sampled and/or storage；
The output end of ADC interface connects down-sampled and memory module, and what described down-sampled and memory module was also connected with phaselocked loop is
System output terminal of clock.
10. a kind of oscillograph, it is characterised in that including the reduction oscillograph external trigger as described in claim 1-7 any one
The system of waveform shake, or, including digit chip as claimed in claim 8 or 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720141733.6U CN206489205U (en) | 2017-02-16 | 2017-02-16 | Reduce system, digit chip and the oscillograph of oscillograph external trigger waveform shake |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720141733.6U CN206489205U (en) | 2017-02-16 | 2017-02-16 | Reduce system, digit chip and the oscillograph of oscillograph external trigger waveform shake |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206489205U true CN206489205U (en) | 2017-09-12 |
Family
ID=59765420
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720141733.6U Active CN206489205U (en) | 2017-02-16 | 2017-02-16 | Reduce system, digit chip and the oscillograph of oscillograph external trigger waveform shake |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206489205U (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108572266A (en) * | 2017-12-11 | 2018-09-25 | 深圳市鼎阳科技有限公司 | A kind of waveshape generating device |
| CN108982940A (en) * | 2018-06-13 | 2018-12-11 | 深圳市鼎阳科技有限公司 | A kind of external trigger device and external trigger method, oscillograph based on serial receiver |
| CN110672899A (en) * | 2019-12-05 | 2020-01-10 | 深圳市鼎阳科技股份有限公司 | Eye pattern reconstruction method for digital oscilloscope and storage medium |
| CN110836993A (en) * | 2019-11-14 | 2020-02-25 | 电子科技大学 | FPGA-based random equivalent acquisition system |
| CN115541955A (en) * | 2022-12-01 | 2022-12-30 | 深圳市鼎阳科技股份有限公司 | Oscilloscope for realizing analog triggering |
| CN116087860A (en) * | 2023-03-30 | 2023-05-09 | 深圳市鼎阳科技股份有限公司 | Oscilloscope external trigger correction method, debugging equipment, system and storage medium |
-
2017
- 2017-02-16 CN CN201720141733.6U patent/CN206489205U/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108572266A (en) * | 2017-12-11 | 2018-09-25 | 深圳市鼎阳科技有限公司 | A kind of waveshape generating device |
| CN108572266B (en) * | 2017-12-11 | 2020-09-15 | 深圳市鼎阳科技股份有限公司 | Waveform generating device |
| CN108982940A (en) * | 2018-06-13 | 2018-12-11 | 深圳市鼎阳科技有限公司 | A kind of external trigger device and external trigger method, oscillograph based on serial receiver |
| CN110836993A (en) * | 2019-11-14 | 2020-02-25 | 电子科技大学 | FPGA-based random equivalent acquisition system |
| CN110672899A (en) * | 2019-12-05 | 2020-01-10 | 深圳市鼎阳科技股份有限公司 | Eye pattern reconstruction method for digital oscilloscope and storage medium |
| CN115541955A (en) * | 2022-12-01 | 2022-12-30 | 深圳市鼎阳科技股份有限公司 | Oscilloscope for realizing analog triggering |
| CN116087860A (en) * | 2023-03-30 | 2023-05-09 | 深圳市鼎阳科技股份有限公司 | Oscilloscope external trigger correction method, debugging equipment, system and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN206489205U (en) | Reduce system, digit chip and the oscillograph of oscillograph external trigger waveform shake | |
| CN100489544C (en) | Spectrogram mask trigger | |
| CN107145468B (en) | Signal generating and reading device and control method | |
| CN103018512B (en) | A kind of oscillograph with external trigger function | |
| JPH0785089B2 (en) | Data acquisition device | |
| CN101324640A (en) | Double-time base digital storage oscillograph | |
| CN110166046B (en) | Sequential equivalent sampling system based on phase delay | |
| CN109212586B (en) | Particle component analysis system and method based on neutral atom imaging device | |
| CN106443184A (en) | Phase detection device and phase detection method | |
| JP2011191178A (en) | Time-width measuring device | |
| CN104090160A (en) | High-precision frequency measuring device | |
| CN110887992A (en) | Clock frequency detection circuit | |
| CN110887984B (en) | Digital oscilloscope supporting eye pattern reconstruction | |
| CN103901243A (en) | High-trigger-accuracy oscilloscope | |
| CN111413725B (en) | System and method for realizing gamma-gamma digital coincidence measurement by using virtual instrument technology | |
| CN103869123B (en) | It is a kind of that there is the oscillograph of pulse width measure | |
| CN106053961B (en) | A kind of the pulse signal synchronous integration measuring device and method of anti-random noise | |
| CN109298248A (en) | A kind of complicated impulse modulation sequence measuring circuit and method based on FPGA | |
| CN105866557B (en) | A kind of realization GHZThe time of pulse percent of pass, energy bispectrum synchronized measurement system | |
| CN207571261U (en) | A kind of system for signal acquisition in integrated circuit testing | |
| CN109948223A (en) | A kind of impulse amplitude acquisition methods based on Lagrange's interpolation | |
| CN110729988A (en) | Circuit, output device, detection system and method for outputting clock jitter signal | |
| CN104749407B (en) | Oscillograph triggers pulse width detection method, apparatus and a kind of oscillograph | |
| CN108226596A (en) | Oscillograph | |
| CN110346625A (en) | A kind of trigger signal production method of adjustable frequency divider |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 518000 Guangdong Province, Baoan District, Baoan District, Xin'an Street, Xingdong Community, 68 District, Antongda Industrial Factory Area, 4 factories, 3 floors, 5 office buildings, 1-3 floors Patentee after: Shenzhen dingyang Technology Co., Ltd Address before: Shenzhen City, Guangdong province Baoan District 518000 District 68 road left three Antongda Industrial Park, 4 floor Patentee before: Shenzhen Siglent Technologies Co., Ltd. |