CN108572266B - Waveform generating device - Google Patents

Waveform generating device Download PDF

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Publication number
CN108572266B
CN108572266B CN201711307712.8A CN201711307712A CN108572266B CN 108572266 B CN108572266 B CN 108572266B CN 201711307712 A CN201711307712 A CN 201711307712A CN 108572266 B CN108572266 B CN 108572266B
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phase
filtering
pulse wave
module
ftw1
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CN108572266A (en
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陆顺杰
王永添
罗森
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Shenzhen Siglent Technologies Co Ltd
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Shenzhen Siglent Technologies Co Ltd
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    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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    • G01R1/28—Provision in measuring instruments for reference values, e.g. standard voltage, standard waveform

Abstract

A waveform generating device comprises a processor, a waveform preprocessing module and a filtering module; the processor is used for calculating pulse wave configuration parameters according to the pulse wave parameters input by a user and configuring the pulse wave configuration parameters to the waveform preprocessing module; the waveform preprocessing module is used for determining a filtering address of the filtering module according to the pulse wave configuration parameters, outputting the filtering address to the filtering module and inputting data to be filtered to the filtering module; the filtering module is used for obtaining a filtering coefficient according to the filtering address and filtering the data to be filtered by adopting the filtering coefficient to obtain the digital pulse wave. Because the filter coefficient can be determined according to the pulse wave configuration parameters, the data to be filtered is filtered by adopting the filter coefficient, and the jitter signals in the data to be filtered are filtered, the generated pulse waves do not have clock jitter of one period, and the pulse waves have good waveform quality and high performance.

Description

Waveform generating device
Technical Field
The invention relates to the technical field of electronics, in particular to a waveform generating device.
Background
Pulse wave and Pulse Width Modulation (PWM) play an important role in the field of electronic technology, and are widely used in the fields of electronic computers, communication, electric power, automatic control and measurement technology, and the like. Current waveform generators generally employ Direct Digital Synthesis (DDS) techniques to generate waveforms. Compared with the traditional frequency synthesizer, the DDS has the advantages of low cost, low power consumption, high resolution, quick conversion time and the like, is widely used in the field of telecommunication and electronic instruments, and is a key technology for realizing full digitalization of equipment. Fig. 1 is a schematic diagram of waveforms generated by the DDS, and as shown in fig. 1, the DDS mainly includes three parts, namely a Frequency control register, a phase accumulator and a waveform memory, in which a Frequency control Word (FTW) input by a user is loaded and registered in the Frequency control register, the phase accumulator performs phase accumulation in each clock cycle according to the FTW to obtain a phase value, the phase value is truncated, a high N bit of the phase value is taken as an address of the waveform memory to obtain an output of the waveform memory, and the output of the waveform memory is directly output to a Digital-to-analog converter (DAC) to generate a desired waveform. When the waveform stored in the waveform memory is a pulse wave, the pulse wave can be generated.
At present, jitter of a system clock period exists when a DDS technology is adopted to generate pulse waves and PWM waves, the jitter is generally fixed to be a few nanoseconds, the jitter is large, and the waveform quality of the generated pulse waves and the PWM waves is poor.
Disclosure of Invention
The application provides a waveform generating device which is used for generating pulse waves or PWM waves so as to reduce waveform jitter and improve waveform quality of the pulse waves or the PWM waves.
According to a first aspect, there is provided in an embodiment a waveform generation apparatus comprising: the device comprises a processor, a waveform preprocessing module and a filtering module;
the processor is used for calculating pulse wave configuration parameters according to pulse wave parameters input by a user and configuring the pulse wave configuration parameters to the waveform preprocessing module;
the waveform preprocessing module is used for determining a filtering address of the filtering module according to the pulse wave configuration parameters, outputting the filtering address to the filtering module, and inputting data to be filtered to the filtering module;
and the filtering module is used for acquiring a filtering coefficient according to the filtering address and filtering the data to be filtered by adopting the filtering coefficient to obtain a digital pulse wave.
According to a second aspect, there is provided in one embodiment a waveform generation apparatus comprising: the device comprises a processor, a phase determining module, a waveform preprocessing module and a filtering module;
the processor is used for calculating PWM wave configuration parameters according to PWM wave parameters input by a user and configuring the PWM wave configuration parameters to the phase determining module and the waveform preprocessing module;
the phase determining module is used for determining a phase P according to the PWM wave configuration parameters and outputting the phase P to the waveform preprocessing module;
the waveform preprocessing module is used for determining a filtering address of the filtering module according to the PWM wave configuration parameters and the P, outputting the filtering address to the filtering module, and inputting data to be filtered to the filtering module;
and the filtering module is used for acquiring a filtering coefficient according to the filtering address, and filtering the data to be filtered by adopting the filtering coefficient to obtain a digital PWM wave.
According to the waveform generating device of the embodiment, the waveform preprocessing module can determine the filtering address of the filtering module according to the pulse wave configuration parameters or the PWM wave configuration parameters, and the filtering module can obtain the corresponding filtering coefficient according to the filtering address, and then filter the data to be filtered by using the filtering coefficient, so as to filter the jitter signal in the data to be filtered, reduce the jitter of the pulse wave or the PWM wave, and make the waveform quality of the generated pulse wave or the PWM wave better and the performance higher.
Drawings
FIG. 1 is a schematic diagram of waveforms generated by a DDS;
FIG. 2 is a parameter diagram of a pulse wave;
FIG. 3 is a schematic diagram of a waveform generator according to an embodiment;
FIG. 4 is a schematic diagram of a waveform generator according to an embodiment
FIG. 5 is a flow chart of a method of generating a pulsed wave in one embodiment;
FIG. 6 is a schematic diagram of a waveform generation apparatus in yet another embodiment;
FIG. 7 is a schematic structural diagram of a waveform generating apparatus according to another embodiment;
FIG. 8 is a schematic diagram of a waveform generation apparatus in another embodiment;
FIG. 9 is a flow chart of a method of generating a PWM wave in another embodiment;
FIG. 10 is a schematic diagram of a waveform generator according to still another embodiment.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings.
In the following embodiments, the description of the relevant parameters of the pulse wave can be represented by fig. 2, as shown in fig. 2, a represents the rising edge time, B represents the falling edge time, C represents the pulse width, which can also be referred to as the duty cycle, and D represents the pulse period, which reflects the frequency of the pulse, which can represent the pulse frequency.
In the embodiment of the invention, the pulse wave configuration parameters or the PWM wave configuration parameters are calculated according to the pulse wave parameters or the PWM wave parameters input by a user, the filter coefficients of the filter are determined according to the pulse wave configuration parameters or the PWM wave configuration parameters, the data to be filtered are filtered by adopting the filter coefficients, and finally the pulse waves or the PWM waves required by the user are output.
The first embodiment is as follows:
fig. 3 is a schematic structural diagram of a waveform generating apparatus according to an embodiment of the present application, and as shown in fig. 3, the waveform generating apparatus 01 includes a processor 1, a waveform preprocessing module 2, and a filtering module 3.
The processor 1 is configured to calculate a pulse wave configuration parameter according to a pulse wave parameter input by a user, and configure the obtained pulse wave configuration parameter to the waveform preprocessing module 2. The pulse wave parameters input by the user may include a pulse wave frequency f, a pulse wave pulse width, a pulse wave rise time rise, and a pulse wave fall time fall. The pulse wave configuration parameters obtained by the processor 1 comprise frequency control words FTW1, FTW2, FTW3 and phase P, wherein FTW1 is proportional to f, the ratio of FTW1 to FTW2 is proportional to rise and inversely proportional to 1/2f, the ratio of FTW1 to FTW3 is proportional to fall and inversely proportional to 1/2f, and P is calculated according to f, width, rise and fall. In one embodiment, FTW1, FTW2, FTW3 and P may be calculated from the following equations:
the formula for FTW1 is:
Figure BDA0001502317380000031
where M is the system bit width, fclkA system clock;
the formula for FTW2 is:
Figure BDA0001502317380000032
the formula for FTW3 is:
Figure BDA0001502317380000033
the formula for P is:
Figure BDA0001502317380000034
the waveform preprocessing module 2 is configured to determine a filtering address of the filtering module 3 according to the pulse wave configuration parameters, that is, determine the filtering address of the filtering module 3 according to the FTW1, FTW2, FTW3, and P calculated by the processor 1, for example, the filtering address of the filtering module 3 may be obtained through certain logic operation according to the FTW1, FTW2, FTW3, and P, and then output the filtering address to the filtering module 3, and input data to be filtered to the filtering module 3.
The filtering module 3 is configured to obtain a filtering coefficient according to the filtering address determined by the waveform preprocessing module 2, and filter the data to be filtered by using the filtering coefficient to obtain a digital pulse wave. For example, the filter module 3 stores a correspondence between a filter address and a filter coefficient in advance, so that the filter coefficient corresponding to the address can be found from the correspondence by using the filter address determined by the waveform preprocessing module 2, and the correspondence between the filter address and the filter coefficient stored in advance in the filter module 3 can be configured by the processor 1.
The waveform generating device provided by this embodiment can determine the filter coefficient of the filtering module according to the pulse wave parameters input by the user, where the determined filter coefficient will be changed, and then filter the data to be filtered by using the filter coefficient, so as to filter the jitter signal in the data to be filtered, so that the generated digital pulse wave will not have clock jitter of one cycle as the pulse wave generated by using the DDS principle, and the waveform quality of the generated pulse wave is better.
Example two
Based on the first embodiment, fig. 4 is a schematic structural diagram of a waveform generating apparatus in a specific embodiment, as shown in fig. 4, a waveform generating apparatus 01 includes a processor 1, a waveform preprocessing module 2, and a filtering module 3, where the waveform preprocessing module 2 includes a first phase accumulator 21, a multiplier 22, and a second phase accumulator 23, and the filtering module 3 includes a filter coefficient memory 31 and a Finite Impulse Response (FIR) filter 32.
The operation of the processor 1 is the same as that of the first embodiment, and is not described here again.
The first phase accumulator 21 is configured to start running with FTW1 as a frequency control word after receiving the pulse wave configuration parameters FTW1 and P, accumulate FTW1, overflow after reaching an upper phase limit, and output an overflow phase to a first end of the multiplier 22; first phase accumulator 21 controls the second terminal input of multiplier 22 to alternate between FTW3/FTW1 and FTW2/FTW1 at each overflow, and controls the frequency control word of second phase accumulator 23 to alternate between FTW3 and FTW2, and alternates the upper phase limit between phase P and phase 720-P. In this process, since FTW2 is proportional to the rise time rise of the pulse wave rise time rise and FTW3 is proportional to the fall time fall of the pulse wave, the first phase accumulator 21 can control the rise time and the fall time of the pulse wave by controlling FTW2 and FTW3, i.e., controlling the accumulation amount of the second phase accumulator 23, at each overflow. Further, since the phase P is related to the rising time, the falling time and the pulse width of the pulse wave, the first phase accumulator 21 can control the pulse width of the pulse wave by controlling its upper phase limit after the rising time and the falling time of the pulse wave are controlled.
The multiplier 22 is configured to multiply the inputs of the first terminal and the second terminal, and output the result to the second phase accumulator 23. The second phase accumulator 23 is configured to output the accumulated phase to the filter coefficient memory 31 every clock cycle according to the operation result of FTW3 and the multiplier or according to the operation result of FTW2 and the multiplier. That is, the multiplier 22 multiplies the overflow phase of the first phase accumulator 21 by FTW3/FTW1, and outputs the phase obtained by the multiplication to the second phase accumulator 23; second phase accumulator 23 starts to operate with FTW3 as a frequency control word and the phase obtained by operation of multiplier 22 as an initial phase, and outputs the accumulated phase to filter coefficient memory 31 every clock cycle under the action of the system clock. Or, the multiplier 22 multiplies the overflow phase of the first phase accumulator 21 by FTW2/FTW1, and outputs the phase obtained by the multiplication to the second phase accumulator 23; second phase accumulator 23 starts operation with FTW2 as a frequency control word and the phase obtained by operation of multiplier 22 as an initial phase, and outputs the phase to filter coefficient memory 31 every clock cycle under the action of the system clock.
The filter coefficient memory 31 is configured to determine a filter coefficient corresponding to the filter address by using the phase output by the second phase accumulator 23 as the filter address, and output the determined filter coefficient to the FIR filter 32. The filter coefficient memory 31 stores a plurality of sets of filter coefficients, the storage mode of the filter coefficients is that each address corresponds to one set of filter coefficients, the corresponding relation can exist in a form of table and can be configured by the processor 1; the set of filter coefficients corresponding to each address may be linear interpolation coefficients, sinusoidal interpolation coefficients, or custom interpolation coefficients. The filter coefficient memory 31 uses the phase output from the second phase accumulator 23 as a filter address, finds a set of filter coefficients corresponding to the filter address from the correspondence between the filter address and the filter coefficients, and outputs the set of filter coefficients to the FIR filter 32.
The FIR filter 32 is configured to perform an operation on the filter coefficient and the data to be filtered, and filter out a dither signal in the data to be filtered (i.e., "01" data, "0" represents a low level, and "1" represents a high level) to obtain a digital pulse wave with a high waveform quality, where a filtering effect depends on the filter coefficient.
Based on the waveform generating apparatus 01, as shown in fig. 5, which is a flowchart of a method for generating a pulse wave according to this embodiment, the method for generating a pulse wave may include:
and calculating pulse wave configuration parameters. According to the pulse wave parameters f, width, rise and fall input by the user, the processor 1 calculates the pulse wave configuration parameters according to the calculation formulas of the pulse wave configuration parameters FTW1, FTW2, FTW3 and P, and configures the obtained pulse wave configuration parameters to the first phase accumulator 21, the multiplier 22 and the second phase accumulator 23.
And determining a filter coefficient according to the pulse wave configuration parameters. The process of determining the filter coefficients may be implemented by steps S11 to S15, specifically:
s11: the first phase accumulator 21 starts to run with FTW1 as the frequency control word, P as the upper phase limit and 0 as the initial phase under the action of the system clock, accumulates FTW1, and overflows after reaching the upper phase limit.
S12: when the first phase accumulator 21 overflows, the first phase accumulator 21 outputs the overflowing phase to the first terminal of the multiplier 22, while controlling the second terminal input of the multiplier 22 to be FTW3/FTW1, controlling the frequency control word of the second phase accumulator 23 to be FTW3, updating the phase upper limit thereof to 720-P, and controlling the data to be filtered "01" to be input "0" to the FIR filter 32.
S13: the multiplier 22 multiplies the inputs of the first terminal and the second terminal, and outputs the phase obtained by the operation to the second phase accumulator 23.
S14: the second phase accumulator 23 starts to run with the phase output from the multiplier 22 as an initial phase and the frequency control word determined by the first phase accumulator 21 as a frequency control word, and then starts to run at the system clock fclkFor example, if the output phase of the second phase accumulator 23 at the current time is a, the next clock output phase is a + FTW 3.
S15: the filter coefficient memory 31 reads out a filter coefficient corresponding to an address of the phase output from the second phase accumulator 23, and outputs the filter coefficient to the FIR filter 32. The filter coefficients stored in the filter coefficient memory 31 may be calculated and configured by the processor.
And filtering the data to be filtered according to the filter coefficient. The filtering process is implemented by step S16, specifically:
s16: at the system clock fclkUnder the action of the filter, the FIR filter 32 performs an operation on the input data and the filter coefficient to obtain a digital pulse wave.
And continuing to filter the next data to be filtered. The specific execution process includes steps S17 to S18:
s17: when the first phase accumulator 21 overflows again, the first phase accumulator 21 outputs the overflowing phase to the first terminal of the multiplier 22 while controlling the second terminal input of the multiplier 22 to be FTW2/FTW1, controlling the frequency control word of the second phase accumulator 23 to be FTW2, updating the phase upper limit thereof to be P, and controlling the data to be filtered "01" to be input "1" to the FIR filter 32.
S18: steps S13 to S16 are performed.
Thereafter, the process of S12 to S18 is executed in a loop.
According to the generation process of the pulse wave, pulse wave parameters can be input according to the requirements of a user, then pulse wave configuration parameters are calculated according to the pulse wave parameters, the filter coefficient of the filter is determined according to the obtained pulse wave configuration parameters, then the data to be filtered is filtered by adopting the filter coefficient, and finally the pulse wave required by the user is output. When filtering data to be filtered (i.e., "01" data constituting a pulse wave) with a fixed filter coefficient, the data to be filtered can act as a smooth waveform, and different filter coefficients can produce different filtering effects, such as filtering into a signal similar to a sine wave. In the above-mentioned generation process of the pulse wave, because the filter coefficient is determined by the waveform preprocessing device according to the pulse wave configuration parameters, the determined filter coefficient is changed, the changed filter coefficient determines that the FIR filter is a low-pass filter, under the action of each system clock, the waveform preprocessing device can select a suitable filter coefficient for "0" or "1" in the "01" data, and the filter coefficient is used to smooth the "0" or "1" signal, so that the "0" or "1" signal is a low-jitter signal, and a high-frequency jitter signal in the data to be filtered is eliminated, therefore, there is no clock jitter of one cycle as in the prior art that the pulse wave is generated by using the DDS principle, so that the waveform quality of the generated pulse wave is better, and the performance is higher. Meanwhile, parameters such as the rising time, the falling time, the pulse width and the like of the pulse wave are input by a user according to actual needs, so that the parameters can be adjusted at will, for example, the adjustment range of the pulse width (duty ratio) can be from 0.01% to 99.99%, and the stepping amount can be as low as 0.1 ns.
EXAMPLE III
Based on the second embodiment, fig. 6 is a schematic structural diagram of a waveform generating apparatus in another specific embodiment, and as shown in fig. 6, the waveform preprocessing module 2 of the waveform generating apparatus 01 includes only a first phase accumulator 21 and a multiplier 22, which is different from the second embodiment. In the present embodiment, the first phase accumulator 21 starts to operate with FTW1 as a frequency control word after receiving the pulse wave configuration parameter, and outputs the accumulated phase of each clock to the first terminal of the multiplier 22. The first phase accumulator 21 overflows after reaching the upper phase limit, and alternately switches the upper phase limit between phase P and phase 720-P at each overflow, and controls the second terminal input of the multiplier to alternately switch between FTW3/FTW1 and FTW2/FTW 1. The multiplier 22 is configured to multiply the inputs of the first terminal and the second terminal, and output the phase obtained by the multiplication to the filter coefficient memory 31. The filter coefficient memory 31, the FIR filter 32 and the processor 1 operate in a manner similar to the filter coefficient memory 31, the FIR filter 32 and the processor 1 in fig. 4. In this embodiment, each output of the first phase accumulator 21 is input to the first end of the multiplier 22, and then the output of the multiplier is directly used as the filtering address of the filtering coefficient memory 31, so that compared with the two embodiments, the second phase accumulator 23 is omitted, thereby saving certain resources. Meanwhile, when the pulse wave is generated by using the waveform generating device, the rising edge and the falling edge of the pulse wave can be controlled by controlling FTW3/FTW1 and FTW2/FTW1, and the pulse width of the pulse wave can be controlled by controlling the upper limit of the phase of the first phase accumulator 21.
In practical application, the processor in each of the above embodiments may be an embedded processor, and mainly implements functions such as user interaction, setting of pulse wave parameters, calculation of pulse wave configuration parameters, and calculation and configuration of filter coefficients. The waveform preprocessing module and the filtering module may be implemented by a Field-Programmable Gate Array (FPGA).
Example four:
fig. 7 is a schematic structural diagram of a waveform generating apparatus according to another embodiment of the present application, and as shown in fig. 7, unlike the first embodiment, a waveform generating apparatus 02 includes a phase determining module 4 in addition to a processor 1, a waveform preprocessing module 2, and a filtering module 3. The waveform generating device may be used to generate a PWM wave.
The processor 1 is configured to calculate a PWM wave configuration parameter according to a PWM wave parameter input by a user, and configure the calculated PWM wave configuration parameter to the waveform preprocessing module 2 and the phase determining module 4. The PWM wave parameters input by the user may include a pulse wave frequency F, a pulse wave width, a pulse wave rise time rise, a pulse wave fall time fall, a modulation frequency F, a pulse width deviation t, and a modulation waveform wave. The PWM wave configuration parameters calculated by the processor 1 comprise frequency control words FTW1, FTW2, FTW3, FTW4 and a group of phases, wherein FTW1 is in direct proportion to F, the ratio of FTW1 to FTW2 is in direct proportion to rise and in inverse proportion to 1/2F, the ratio of FTW1 to FTW3 is in direct proportion to fall and in inverse proportion to 1/2F, FTW4 is in direct proportion to F, and the group of phases in the PWM wave configuration parameters are obtained according to width, t and wave. In a specific embodiment, the calculation formulas of FTW1, FTW2 and FTW3 are the same as those of FTW1, FTW2 and FTW3 in example one, and the calculation formula of FTW4 is:
Figure BDA0001502317380000081
where M is the system bit width, fclkIs the system clock.
One group of phases in the PWM wave configuration parameters are a group of phases corresponding to the wave of the modulation waveform, and can be obtained by converting the wave according to t and width, and the calculation method comprises the following steps: firstly, obtaining the maximum positive pulse width (width + t) and the minimum positive pulse width (width-t) according to t and width, and obtaining the maximum positive pulse width (width + t) and the maximum phase PmaxCorresponding to a minimum positive pulse width (width-t) and a minimum phaseBit PminCorrespondingly, P can be further determined by (width + t) and (width-t)maxAnd Pmin. And due to PmaxAnd PminCorresponding to the maximum amplitude value wave of the modulation waveform wavemaxAnd minimum amplitude value waveminAnd wave is known, then, by PmaxAnd PminAnd wavemaxAnd waveminThe corresponding relationship can determine the functional relationship between the phase and the modulation waveform, and each waveform point of the modulation waveform corresponds to a phase value, so that a group of phases corresponding to wave can be further calculated.
The phase determining module 4 is configured to determine a phase P according to the PWM wave configuration parameters, that is, determine a phase P from a group of phases in the PWM wave configuration parameters, and output the determined phase P to the waveform preprocessing module 2, where the phase P can be used to control the pulse width of the PWM wave.
The waveform preprocessing module 2 is configured to determine a filtering address of the filtering module 3 according to the PWM wave configuration parameter and the phase P, that is, determine the filtering address of the filtering module 3 according to the FTW1, FTW2, and FTW3 calculated by the processor 1 and the phase P determined by the phase determining module 4, for example, obtain the filtering address of the filtering module 3 through a certain logical operation according to the FTW1, the FTW2, the FTW3, and the phase P, and output the determined filtering address to the filtering module 3, and simultaneously input data to be filtered to the filtering module 3.
The operation of the filtering module 3 is similar to that in the first embodiment, and is not described herein again, so that the digital PWM wave can be obtained finally.
The waveform generating device provided by this embodiment can determine the filter coefficient of the filtering module according to the PWM wave parameters input by the user, where the determined filter coefficient will be changed, and then filter the data to be filtered by using the filter coefficient, so as to filter the jitter signal in the data to be filtered, and the generated digital pulse wave will not have clock jitter of one cycle as the pulse wave generated by using the DDS principle, so that the waveform quality of the generated PWM wave is better.
EXAMPLE five
Based on the fourth embodiment, fig. 8 is a schematic structural diagram of a waveform generating apparatus in another specific embodiment, as shown in fig. 8, a waveform generating apparatus 02 includes a processor 1, a waveform preprocessing module 2, a filtering module 3, and a phase determining module 4, where the waveform preprocessing module 2 includes a first phase accumulator 21, a multiplier 22, and a second phase accumulator 23, the filtering module 3 includes a filter coefficient memory 31 and an FIR filter 32, and the phase determining module 4 includes a third phase accumulator 41 and a phase memory 42.
The operation of the processor 1 is the same as that of the fourth embodiment, and is not described here again.
First phase accumulator 21 starts to operate with FTW1 as a frequency control word after receiving the PWM wave configuration parameters. The third phase accumulator 41 receives the PWM wave configuration parameter, operates simultaneously with the first phase accumulator 21 using FTW4 as a frequency control word, and outputs the phase to the phase memory 42.
The phase memory 42 is configured to determine P according to the output phase of the third phase accumulator 41 when the first phase accumulator 21 overflows every 2 times, for example, the output phase of the third phase accumulator 41 may be truncated, the upper N bits are taken as an address of the phase memory 42, and the phase P corresponding to the address is read out, that is, the phase P corresponding to the address is found from a set of phases in the PWM wave configuration parameters through the address, the set of phases is configured to the phase memory 42 by the processor 1, and the storage manner of the phase memory 42 is that each address corresponds to one phase in the set of phases. After phase memory 42 determines P, the determined P is output to first phase accumulator 21.
The first phase accumulator 21, the multiplier 22, the second phase accumulator 23, the filter coefficient memory 31 and the FIR filter 32 operate in a manner similar to that in the second embodiment, the only difference is that in the second embodiment, the phase P is fixed; in the present embodiment, the phase P is determined by the phase determining module 4, i.e. the third phase accumulator 41 and the phase memory 42, and the phase P is updated once every 2 times the first phase accumulator 21 overflows, i.e. the phase memory 42 outputs the determined phase P to the first phase accumulator 21 once every 2 times the first phase accumulator 21 overflows, and the phase P is changed. The value of P determines the high level duration of the pulse wave, i.e. the pulse width, so that the pulse width can be controlled by P, and the pulse width can be continuously adjusted by continuously updating the value of P, thereby realizing the function of PWM and generating the PWM wave. Similar to the second embodiment, the present embodiment provides that the waveform generating device 02 can also filter out the high-frequency jitter signal in the data to be filtered (i.e., "01" data), so as to obtain the digital PWM wave with better waveform quality.
In the existing PWM schemes, the adjustment of the pulse width deviation is usually controlled by using a register, and the minimum resolution of the pulse width deviation corresponding to the register is one period of a system clock, and the resolution is low, generally in ns order. The invention adopts the phase P to control the pulse width, the phase P is obtained by converting the modulation waveform according to the pulse width deviation and the pulse width, and the precision of the phase P determines the precision of the pulse width, so that the resolution of the pulse width deviation is equal to that of the phase P, the minimum resolution of the pulse width deviation of the PWM wave can reach ps level, the resolution of the pulse width deviation of the PWM wave is greatly optimized, and the generated PWM wave is closer to the ideal PWM wave.
Based on the waveform generating device 02, as shown in fig. 9, which is a flowchart of a method for generating a PWM wave according to this embodiment, the method for generating a PWM wave may include:
and calculating PWM wave configuration parameters. According to the PWM wave parameters F, width, rise, fall, F, t and wave input by the user, the processor 1 calculates the PWM wave configuration parameters according to the calculation formulas of the pulse wave configuration parameters FTW1, FTW2, FTW3 and FTW4 and the determination method of the phase, and configures the PWM wave configuration parameters to the first phase accumulator 21, the multiplier 22, the second phase accumulator 23, the third phase accumulator 41 and the phase memory 42.
And determining a filter coefficient according to the PWM wave configuration parameters. The process of determining the filter coefficients may be implemented by steps S21 to S25, specifically:
s21: first phase accumulator 21 begins running at FTW1 as a frequency control word under the influence of the system clock.
S22: the third phase accumulator 41 starts operating at the same time as the first phase accumulator 21 with FTW4 as a frequency control word and outputs the phase to the phase memory 42.
S23: the phase memory 42 determines a phase P from the output phase of the third phase accumulator 41, and outputs P to the first phase accumulator 21 as the upper phase limit of the first phase accumulator 21.
S24: the first phase accumulator 21 overflows after reaching the upper phase limit.
The execution processes of S25 to S28 are similar to those of S12 to S15 in the second embodiment, and are not described herein again.
And filtering the data to be filtered according to the filter coefficient. The filtering process is implemented by step S29, specifically:
s29: at the system clock fclkUnder the action of the filter, the FIR filter 32 performs an operation on the input data and the filter coefficient to obtain a digital PWM wave.
And continuing to filter the next data to be filtered. The specific execution process includes steps S210 to S211:
s210: when the first phase accumulator 21 overflows again, the phase memory 42 determines a new P from the output phase of the third phase accumulator 41. The first phase accumulator 21 outputs the overflow phase to the first terminal of the multiplier 22 while controlling the second terminal input of the multiplier 22 to be FTW2/FTW1, controlling the frequency control word of the second phase accumulator 23 to be FTW2, and controlling the new P output from the phase memory 42 as the upper phase limit and the data to be filtered "01" to be input "1" to the FIR filter 32.
S211: steps S26 to S29 are performed.
Thereafter, the process of S24 to S211 is cyclically executed.
According to the generation process of the PWM wave, similar to the second embodiment, the generated PWM wave does not have clock jitter of one period as the PWM wave generated by using the DDS principle in the prior art, and the generated PWM wave has good waveform quality and high performance. Meanwhile, parameters such as the rising time and the falling time of the PWM wave can be adjusted at will according to the requirements of users.
EXAMPLE six
Based on the fifth embodiment, fig. 10 is a schematic structural diagram of a waveform generating apparatus in yet another specific embodiment, and as shown in fig. 10, a waveform preprocessing module 2 of a waveform generating apparatus 02 includes only a first phase accumulator 21 and a multiplier 22, which is different from the fifth embodiment. The processor 1, the filter coefficient memory 31 and the FIR filter 32 operate in a manner similar to that in the fifth embodiment; the operation of the first phase accumulator 21 and the multiplier 22 is similar to that of the third embodiment, and the only difference is that: in the third embodiment, the phase P is fixed, and in the present embodiment, the phase P is determined by the phase determining module 4, i.e. the third phase accumulator 41 and the phase memory 42, and the phase P is updated once every 2 times the first phase accumulator 21 overflows, i.e. the phase memory 42 outputs the determined phase P to the first phase accumulator 21 once every 2 times the first phase accumulator 21 overflows, and the phase P is changed. Compared with the fifth embodiment, the second phase accumulator 23 is omitted in the present embodiment, so that certain resources can be saved.
In practical applications, the processors in the fourth to sixth embodiments may be embedded processors, and mainly implement functions of user interaction, setting of PWM wave parameters, calculation of PWM wave configuration parameters, calculation and configuration of filter coefficients, and the like. The waveform preprocessing module, the filtering module and the phase determination module may be implemented by an FPGA.
The above embodiments are described by taking a single-path mode as an example, and in practical applications, the pulse wave or the PWM wave may also be generated in a multi-path parallel mode, that is, the pulse wave is generated by the multi-path waveform preprocessing module and the filtering module together, or the PWM wave is generated by the multi-path waveform preprocessing module, the filtering module and the phase determining module together. When the pulse wave or the PWM wave is generated in a multipath parallel mode, the processor can obtain waveform configuration parameters through calculation and then configure the waveform configuration parameters to the multipath waveform preprocessing module and the filtering module or the multipath waveform preprocessing module, the filtering module and the phase determining module. Due to the adoption of a multi-path parallel mode, the upper limits of pulse wave parameters or PWM wave parameters such as rise time, fall time and the like can be improved. Meanwhile, compared with a single-path mode, under the same frequency, the data volume of the multi-path parallel mode for generating the pulse wave or the PWM wave is multiplied, namely the number of the waveform points is more, so that the waveform of the pulse wave or the PWM wave can be better reflected, and the quality of the generated pulse wave or the PWM wave is better.
In practical application, after the digital pulse wave or the digital PWM wave is obtained, the digital pulse wave or the digital PWM wave is input to the DAC, converted into an analog signal, and then output as an analog pulse wave or an analog PWM wave through the analog channel.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.

Claims (7)

1. A waveform generation device, comprising: the device comprises a processor, a waveform preprocessing module and a filtering module;
the processor is used for calculating pulse wave configuration parameters according to pulse wave parameters input by a user and configuring the pulse wave configuration parameters to the waveform preprocessing module;
the waveform preprocessing module is used for determining a filtering address of the filtering module according to the pulse wave configuration parameters, outputting the filtering address to the filtering module, inputting data to be filtered to the filtering module, and alternately switching the data to be filtered between 0 and 1 when the data to be filtered is input each time;
the filtering module is used for obtaining a filtering coefficient according to the filtering address and performing low-pass filtering on the data to be filtered by adopting the filtering coefficient to obtain a digital pulse wave;
the pulse wave parameters comprise pulse wave frequency f, pulse wave pulse width, pulse wave rise time rise and pulse wave fall;
the pulse wave configuration parameters comprise frequency control words FTW1, FTW2, FTW3 and phase P, wherein the FTW1 is proportional to the f, the ratio of the FTW1 to the FTW2 is proportional to the rise and inversely proportional to 1/2f, the ratio of the FTW1 to the FTW3 is proportional to the fall and inversely proportional to 1/2f, and the P is calculated according to the f, the width, the rise and the fall;
the waveform preprocessing module comprises a first phase accumulator and a multiplier;
the first phase accumulator is used for starting to run by taking the FTW1 as a frequency control word after receiving the pulse wave configuration parameters and outputting accumulated phases of each clock to the first end of the multiplier, the first phase accumulator overflows after reaching an upper phase limit, the upper phase limit is alternately switched between a phase P and a phase 720-P when overflowing, and the second end input of the multiplier is controlled to be alternately switched between FTW3/FTW1 and FTW2/FTW 1;
the multiplier is used for multiplying the input of the first end and the input of the second end and outputting the phase obtained by calculation to the filtering module.
2. A waveform generation device, comprising: the device comprises a processor, a waveform preprocessing module and a filtering module;
the processor is used for calculating pulse wave configuration parameters according to pulse wave parameters input by a user and configuring the pulse wave configuration parameters to the waveform preprocessing module;
the waveform preprocessing module is used for determining a filtering address of the filtering module according to the pulse wave configuration parameters, outputting the filtering address to the filtering module, inputting data to be filtered to the filtering module, and alternately switching the data to be filtered between 0 and 1 when the data to be filtered is input each time;
the filtering module is used for obtaining a filtering coefficient according to the filtering address and performing low-pass filtering on the data to be filtered by adopting the filtering coefficient to obtain a digital pulse wave;
the pulse wave parameters comprise pulse wave frequency f, pulse wave pulse width, pulse wave rise time rise and pulse wave fall;
the pulse wave configuration parameters comprise frequency control words FTW1, FTW2, FTW3 and phase P, wherein the FTW1 is proportional to the f, the ratio of the FTW1 to the FTW2 is proportional to the rise and inversely proportional to 1/2f, the ratio of the FTW1 to the FTW3 is proportional to the fall and inversely proportional to 1/2f, and the P is calculated according to the f, the width, the rise and the fall;
the waveform preprocessing module comprises a first phase accumulator, a multiplier and a second phase accumulator;
the first phase accumulator is used for starting to run by taking the FTW1 as a frequency control word after receiving the pulse wave configuration parameters, overflowing after reaching a phase upper limit, and outputting an overflowing phase to the first end of the multiplier, the first phase accumulator alternately switches the phase upper limit between a phase P and a phase 720-P at each overflow, controls the second end input of the multiplier to alternately switch between FTW3/FTW1 and FTW2/FTW1, and controls the frequency control word of the second phase accumulator to alternately switch between FTW3 and FTW 2;
the multiplier is used for performing multiplication operation on the input of the first end and the input of the second end and outputting an operation result to the second phase accumulator;
and the second phase accumulator is used for outputting a phase to the filtering module in each clock cycle according to the operation result of FTW3 or FTW2 and the multiplier.
3. The apparatus of claim 1 or 2, wherein the filtering module comprises: a filter coefficient memory and a finite impulse response FIR filter;
the filter coefficient memory is used for determining a filter coefficient corresponding to a filter address by taking the phase output by the waveform preprocessing module as the filter address, and outputting the filter coefficient to the FIR filter;
the FIR filter is used for calculating the filter coefficient and the data to be filtered to obtain the digital pulse wave.
4. A waveform generation device, comprising: the device comprises a processor, a phase determining module, a waveform preprocessing module and a filtering module;
the processor is used for calculating PWM wave configuration parameters according to PWM wave parameters input by a user and configuring the PWM wave configuration parameters to the phase determining module and the waveform preprocessing module;
the phase determining module is used for determining a phase P according to the PWM wave configuration parameters and outputting the phase P to the waveform preprocessing module;
the waveform preprocessing module is used for determining a filtering address of the filtering module according to the PWM wave configuration parameters and the P, outputting the filtering address to the filtering module, inputting data to be filtered to the filtering module, and alternately switching the data to be filtered between 0 and 1 when the data to be filtered is input each time;
the filtering module is used for obtaining a filtering coefficient according to the filtering address and performing low-pass filtering on the data to be filtered by adopting the filtering coefficient to obtain a digital PWM wave;
the PWM wave parameters comprise pulse wave frequency F, pulse wave pulse width, pulse wave rising time rise, pulse wave falling time fall, modulation frequency F, pulse width deviation t and modulation waveform wave;
the PWM wave configuration parameters comprise frequency control words FTW1, FTW2, FTW3, FTW4 and a set of phases, wherein the FTW1 is proportional to the F, the ratio of the FTW1 to the FTW2 is proportional to the rise and inversely proportional to 1/2F, the ratio of the FTW1 to the FTW3 is proportional to the fall and inversely proportional to 1/2F, the FTW4 is proportional to the F, and the set of phases is obtained according to the width, the t and the wave;
the waveform preprocessing module comprises a first phase accumulator and a multiplier;
the first phase accumulator is used for starting to run by taking the FTW1 as a frequency control word after receiving the PWM wave configuration parameter; outputting the accumulated phase of each clock to a first end of a multiplier, wherein the first phase accumulator overflows after reaching an upper phase limit, alternately switching the upper phase limit between the phase P and the phase 720-P when overflowing, and controlling the second end input of the multiplier to alternately switch between FTW3/FTW1 and FTW2/FTW 1;
the multiplier is used for multiplying the input of the first end and the input of the second end and outputting the phase obtained by calculation to the filtering module.
5. A waveform generation device, comprising: the device comprises a processor, a phase determining module, a waveform preprocessing module and a filtering module;
the processor is used for calculating PWM wave configuration parameters according to PWM wave parameters input by a user and configuring the PWM wave configuration parameters to the phase determining module and the waveform preprocessing module;
the phase determining module is used for determining a phase P according to the PWM wave configuration parameters and outputting the phase P to the waveform preprocessing module;
the waveform preprocessing module is used for determining a filtering address of the filtering module according to the PWM wave configuration parameters and the P, outputting the filtering address to the filtering module, inputting data to be filtered to the filtering module, and alternately switching the data to be filtered between 0 and 1 when the data to be filtered is input each time;
the filtering module is used for obtaining a filtering coefficient according to the filtering address and performing low-pass filtering on the data to be filtered by adopting the filtering coefficient to obtain a digital PWM wave;
the PWM wave parameters comprise pulse wave frequency F, pulse wave pulse width, pulse wave rising time rise, pulse wave falling time fall, modulation frequency F, pulse width deviation t and modulation waveform wave;
the PWM wave configuration parameters comprise frequency control words FTW1, FTW2, FTW3, FTW4 and a set of phases, wherein the FTW1 is proportional to the F, the ratio of the FTW1 to the FTW2 is proportional to the rise and inversely proportional to 1/2F, the ratio of the FTW1 to the FTW3 is proportional to the fall and inversely proportional to 1/2F, the FTW4 is proportional to the F, and the set of phases is obtained according to the width, the t and the wave;
the waveform preprocessing module comprises a first phase accumulator, a multiplier and a second phase accumulator;
the first phase accumulator is used for starting to run by taking the FTW1 as a frequency control word after receiving the PWM wave configuration parameters, overflowing after reaching a phase upper limit, and outputting an overflowing phase to the first end of the multiplier, the first phase accumulator alternately switches the phase upper limit between a phase P and a phase 720-P at each overflow, controls the second end input of the multiplier to alternately switch between FTW3/FTW1 and FTW2/FTW1, and controls the frequency control word of the second phase accumulator to alternately switch between FTW3 and FTW 2;
the multiplier is used for performing multiplication operation on the input of the first end and the input of the second end and outputting an operation result to the second phase accumulator;
and the second phase accumulator is used for outputting a phase to the filtering module in each clock cycle according to the operation result of FTW3 or FTW2 and the multiplier.
6. The apparatus of claim 4 or 5, wherein the phase determination module comprises: a third phase accumulator and a phase memory;
the third phase accumulator is used for operating simultaneously with the first phase accumulator and outputting the phase to the phase memory;
and the phase memory is used for determining the P according to the output phase of the third phase accumulator when the first phase accumulator overflows every 2 times, and outputting the P to the first phase accumulator.
7. The apparatus of claim 4 or 5, wherein the filtering module comprises: a filter coefficient memory and a finite impulse response FIR filter;
the filter coefficient memory is used for determining a filter coefficient corresponding to a filter address by taking the phase output by the waveform preprocessing module as the filter address, and outputting the filter coefficient to the FIR filter;
the FIR filter is used for calculating the filter coefficient and the data to be filtered to obtain a digital PWM wave.
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