CN107425861A - A kind of arbitrary bit rate digital modulation signals generation method based on SDR - Google Patents
A kind of arbitrary bit rate digital modulation signals generation method based on SDR Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0008—Modulated-carrier systems arrangements for allowing a transmitter or receiver to use more than one type of modulation
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Abstract
The present invention relates to a kind of arbitrary bit rate digital modulation signals generation method based on SDR, belong to signal of communication processing technology field.The present invention uses a FPGA and single channel DAC hardware structure, system processing clock parallel multi-channel generation signal is used as by the use of the frequency-dividing clock of fixed sample clock, filter tap coefficients in the look-up table designed under each clock according to bit rate, sampling clock, parallel channel number and channel value one are selected and carry out molding filtration computing with high code rate data stream, last multi-channel parallel signal obtains the digital intermediate frequency signal that code check can arbitrarily be set by Digital Up Convert and parallel-serial conversion, and being output to balun by DAC sends analog signal.Compared with conventional transformation sampling clock method, hardware configuration is simpler, and performance is more stable, and practicality is more preferable, and the degree of modularity is higher.
Description
Technical field
The present invention relates to a kind of arbitrary bit rate digital modulation signals generation method based on SDR, belongs to signal of communication processing
Technical field.
Background technology
As countries in the world are in the keen competition of aerospace field, used suitable for satellite communication, Unmanned Aerial Vehicle Data Link etc.
The high speed data transmission system of family spacecraft turns into the prior development direction of countries in the world.A kind of powerful, degree of modularity
Height, universal strong, it can seem particularly heavy as the arbitrary bit rate modulation signal occurrence device of test equipment or spacecraft load
Will.
It should be arbitrary bit rate modulation letter based on SDR (software radio) arbitrary bit rate digital modulation signals generation method
Key technology in number generating means.This method supports that including all width such as BPSK, QPSK, 8PSK is combined modulation system, can
Directly to produce arbitrary bit rate modulated intermediate frequency signal, code check and IF-FRE are limited solely by DAC sampling rates.
Conventional method produces the method that arbitrary bit rate signal uses transformed samples clock, is also needed in addition to signal processing chip
External clock chip, multi-disc DAC (or a piece of multichannel DAC) and simulation up-conversion chip, lead to not device miniaturization；It is given birth to
Into modulated signal code check can not be continuously any adjustable, lead to not the test suitable for all bit rate signals and application scenarios；
In its hardware structure, baseband signal, which need to export through multichannel DAC and simulate quadrature up-conversion, can just obtain intermediate-freuqncy signal, passage
Between imbalance and simulation quadrature carrier phase difference inaccuracy lead to not produce high-quality signal.
The content of the invention
The invention aims to solve the defects of above method, it is proposed that a kind of arbitrary bit rate number based on SDR
Word modulated signal generation method.
The present invention core concept be：Using a FPGA and the hardware structure of a single channel DAC, fixed sample clock is utilized
Frequency-dividing clock as system processing clock parallel multi-channel generation signal, under each clock according to code check, sampling clock,
Filter tap coefficients in the look-up table that parallel channel number and channel value were designed one select and and high code rate data
Stream carries out molding filtration computing, and last multi-channel parallel signal obtains code check and can arbitrarily set by Digital Up Convert and parallel-serial conversion
Digital intermediate frequency signal, balun is output to by DAC and sends analog signal.
The purpose of the present invention is achieved through the following technical solutions.
A kind of arbitrary bit rate digital modulation signals generation method based on SDR, step are as follows：
Step 1: high code check information source is generated using high-speed parallel pseudo-random sequence
Specific method is as follows：
Step 1.1 data generating module handles the LFSR structures parallelization of pseudo-random sequence generator, pseudo-random sequence
Generator is made up of maximum length linear feedback shift register (LFSR)；
Conventionally, each mobile bit register, a pseudo-random sequence value output can accordingly be obtained, it is assumed that
System processing clock be 150MHz, can caused by pseudo-random sequence handling capacity also with regard to 150Mbps, it is therefore desirable to using parallel
Change technology obtains higher handling capacity；
Step 1.2 judges whether subsequent module provides request of data, and carries out corresponding operating：
Wherein, subsequent module refers to address update module；
1.21 when address update module provides request of data, and to the mobile a bit registers of a high position, it is pseudo- just to produce a positions by LFSR
Random sequence is exported, and a positions output result is fed back in LFSR low a bit registers simultaneously；
Wherein a selects according to the arbitrarily adjustable upper limit of code check.Such as assume that system processing clock is F1, code check can set scope
Up to Rs, a >=Rs/F1 need to be met.
1.22 when address update module does not provide request of data, waits request of data；
Step 2: high code rate data caching and management, are specially：
High speed PRBS caused by data generating module is buffered in a FIFO by step 2.1, waits pending data please
Ask enabled, after request of data is enabled to be reached, jump to step 2.2；
Step 2.2 enables according to the request of data of rear end address update module, produces a RFD (ready for data)
Enable signal, and module request data occur to high-speed parallel pseudo-random sequence；
Step 2.3 receives the module request data of step 2.2 output, and FPGA judges whether FIFO is empty, and carries out phase
It should operate：
If 2.31 FIFO non-NULLs, rear end address update module exports the signal of an a position, is carried out for rear module
Data interpolating；
If 2.32 FIFO empties, to data generating module request data；
Step 3: according to precision and computing requirement, the S lookups for the matched filter coefficient of channel matched of generation
Table, it is respectively present in T ROM；Influence degree according to matched filter secondary lobe to performance, preferable S values are 6；For side
Just computing, T is general and S-phase etc.；
In order to facilitate computing, ROM depth is 2^n, and n typically takes 10；
Step 4: FPGA handles the parallel M passages of modulated signal；
Wherein, M selection is relevant with the sample rate of system processing clock and DAC, i.e. M=Fs/F1；
F1 is that system handles clock；Fs is DAC sample rate；
Code check caused by system requirements, Rs, Rs and passage M are designated as, the high speed code DDS of M passages are produced, wherein each channel code
DDS phase control words PiEquation below (1) can be expressed as：
Wherein, 2mFor normalization factor, m selection is relevant with precision,Expression rounds；
Step 5: FPGA updates M channel phases, the data address for interpolation, and the filtering for interpolation are obtained
Device coefficient address；
Wherein, the data address for interpolation, is designated as Data_addr；For the filter coefficient address of interpolation, it is designated as
Coe_addr；
The renewal process of M channel phases is as follows：
Phase1=2*2m；
Phasei=Phasei-1+Pi-1, i=2,3,4 ... M (2)
Wherein, Phase1Represent the phase of first passage, PhaseiRepresent the phase of i-th of passage；Phasei-1Represent
The phase of the i-th -1 passage；Pi-1It is the i-th -1 channel code DDS phase control words；The Data_addr of each passage takes Phasei
High d positions, meet 2d>=a, Coe_addr take PhaseiLow m positions in high n positions, 2^n be ROM depth；
Step 6: each passage is obtained according to the data address of the interpolation of step 5 output and filter coefficient address
Slotting input signal and filter coefficient, summation is weighted to data and coefficient, obtains the modulation output signal of every passage；
Step 7: the more phase of new tunnel 1, especially by equation below (3)：
Phase1=Phase1+PM (3)
Wherein, PMIt is m-th channel code DDS phase control words；
Step 8: producing RFD (ready for data) signal after phase of more new tunnel 1 finishes, return to
Step 2；
So far, from step 1 to step 8, a kind of arbitrary bit rate digital modulation signals generation side based on SDR is completed
Method.
The system that a kind of arbitrary bit rate digital modulation signals generation method based on SDR is relied on, including data produce mould
Block, filter coefficient look-up table, address update module, convolution module, parallel serial conversion module and DAC；
Wherein, data generating module, filter coefficient look-up table, address update module, convolution module, parallel serial conversion module
It is respectively positioned in FPGA；
The annexation of each module is as follows in system：
Data generating module link address update module and convolution module；Filter coefficient look-up table link address updates mould
Block and acoustic convolver module；Acoustic convolver module connects parallel serial conversion module；Parallel serial conversion module connects DAC.
The function of each module is as follows in system：
The function of data generating module is to produce high code rate data and be stored in RAM, updates the RAM according to request of data；Filter
The function of ripple device Coefficient Look-up Table is the filter tap coefficients that design Storage is crossed, to the convolution algorithm of molding filtration；Address
The function of update module is when calculating this according to code check, sampling clock, parallel channel number and channel value under each clock
Data address and the address of filter coefficient in a lookup table of computing are participated under clock in each channel data generation module RAM；
The function of acoustic convolver module is to carry out the convolution algorithm of molding filtration；The function of parallel serial conversion module is to enter multi-path parallel signal
Row parallel-serial conversion is input to DAC；DAC function is to convert digital signals into analog signal to be sent into balun, obtains final code
The intermediate-freuqncy signal that rate can arbitrarily be set.
Beneficial effect
The present invention devises a kind of arbitrary bit rate digital modulation signals generation method, with existing arbitrary bit rate modulated signal
Generation method is compared, and is had the advantages that：
1. the method for the invention is advantageous to the small-sized of equipment only with a FPGA and the hardware structure of a single channel DAC
Change and modularized design, beneficial to the realization of software radio, and reduce cost；
2. the method for the invention compared to conventional transformation sampling clock method has signal code check, continuously any stepping can
The advantage of tune, truly accomplishes the switching of arbitrary velocity, and adjustable extent is limited solely by DAC sampling rates；
3. using Digital Up Convert in the method for the invention, have compared to quadrature up-conversion method is simulated in conventional method
Have that caused intermediate-freuqncy signal precision is higher, the more stable advantage of performance；
Brief description of the drawings
Fig. 1 is general pseudo-random sequence LFSR circuit theory diagrams；
Fig. 2 is the Parallel Implementation flow of LFSR circuits；
Fig. 3 is the system in the present invention a kind of arbitrary bit rate digital modulation signals generation method and embodiment 1 based on SDR
Composition and method flow schematic diagram；
Fig. 4 is that DAC is direct in a kind of arbitrary bit rate digital modulation signals generation method embodiment 2 based on SDR of the present invention
The code check sent is 100Mbps, the frequency spectrum of intermediate frequency 1.2GHz signals；
Fig. 5 is that code check is in a kind of arbitrary bit rate digital modulation signals generation method embodiment 2 based on SDR of the present invention
100Mbps, the planisphere and EVM of intermediate frequency 1.2GHz signals.
Embodiment
The present invention will be further described with reference to the accompanying drawings and examples and is described in detail.
Embodiment 1
The present embodiment describes a kind of arbitrary bit rate digital modulation signals generation method based on SDR of the present invention specific real
Flow chart when applying.
Fig. 1 is the pseudorandom sequence for handling the LFSR structures parallelization of pseudo-random sequence generator in the method for the invention
The composition circuit theory diagrams of row generator；
Fig. 2 is to handle the LFSR structures parallelization of pseudo-random sequence generator in the A of the method for the invention step 1
Paralell design.
Fig. 3 is the system composition that a kind of arbitrary bit rate digital modulation signals generation method based on SDR of the present invention is relied on
With method flow diagram.
From figure 3, it can be seen that after j channel data produces, enter convolution module, wherein data address by data storage
Selection be calculated by address update module according to code check, channel information and phase information.Address update module is also controlled simultaneously
The address of filter coefficient look-up table processed.The convolution module output data of j passage is output to DAC by parallel-serial conversion.
Embodiment 2
The present embodiment 2 is entered exemplified by sending a code check as 100Mbps 8PSK signals to the specific implementation process of the present invention
Row explanation.
Step A, 8 PN codes are produced first as information flow, are mapped by design requirement, are stored in RAM, asked according to data
Seek the value in information updating RAM.
Step B, 6 look-up tables are generated, each look-up table depth is 1024, is represented with 12bit, is stored in forming filter
Tap coefficient；
Step C, according to code check, sampling rate, system processing clock, port number and channel position calculate each channel code
DDS phase control words.Code check Rs is 100Mbps in the embodiment, and sampling rate Fs is 5GHz, and system processing clock F1 is
156.25Mhz, port number M are that 32, m takes 32.
Can basisCalculating there emerged a channel phases.
Step D, can be according to Phasei=Phasei-1+Pi-1, i=2,3,4 ... M updates each channel phases, wherein initially
Value Phase1=2*2m, afterwards each clock update.
Step E, each channel phases control word being calculated according to step D, it is Data_addr to take high 4；Take low 32
In high 10 be used as Coe_addr.
Step F, taken out according to Data_addr and Coe_addr from step A RAM and step B look-up table data and
Filter coefficient, convolution algorithm is carried out, obtains the output of every passage
Step G, according to Phase1=Phase1+P32The more phase of new tunnel 1.
Step H, each channel signal is utilized into parallel DDS technologies Digital Up Convert to intermediate frequency 1.2GHz.
Step I, the output of 32 passages is subjected to parallel-serial conversion and is sent into DAC, then analog signal is exported by balun.
So far, from step A to step I, intermediate frequency 1.2GHz is completed, code check 100Mbps 8PSK signals produce.
Fig. 4 is that the code check that DAC is directly sent in the present embodiment is 100Mbps, the frequency spectrum of intermediate frequency 1.2GHz signals, is corresponded to
By the analog signal of balun output in step I.
Fig. 5 is the planisphere and EVM that signal is produced in the present embodiment step I.
Described above is presently preferred embodiments of the present invention, and the present invention should not be limited to the embodiment and accompanying drawing institute is public
The content opened.It is every not depart from the lower equivalent or modification completed of spirit disclosed in this invention, both fall within the model that the present invention protects
Enclose.
Claims (3)
1. a kind of arbitrary bit rate digital modulation signals generation method based on SDR, it is characterised in that comprise the following steps that：
Step 1: high code check information source is generated using high-speed parallel pseudo-random sequence；
Step 2: high bit rate data buffer storage and management, are specially：
High speed PRBS caused by data generating module is buffered in a FIFO by step 2.1, waits request of data to make
Can, after request of data is enabled to be reached, jump to step 2.2；
Step 2.2 enables according to the request of data of rear end address update module, and it is enabled to produce a RFD (ready for data)
Signal, and module request data occur to high-speed parallel pseudo-random sequence；
Step 2.3 receives the module request data of step 2.2 output, and FPGA judges whether FIFO is empty, and is accordingly grasped
Make：
If 2.31 FIFO non-NULLs, rear end address update module exports the signal of an a position, and data are carried out for rear module
Interpolation；
If 2.32 FIFO empties, to data generating module request data；
Step 3: according to precision and computing requirement, the S look-up tables for the matched filter coefficient of channel matched of generation, divide
Do not exist in T ROM；
Step 4: FPGA handles the parallel M passages of modulated signal；
Wherein, M selection is relevant with the sample rate of system processing clock and DAC, i.e. M=Fs/F1；
F1 is that system handles clock；Fs is DAC sample rate；
Character rate caused by system requirements, Rs, Rs and passage M are designated as, the high speed code DDS of M passages are produced, wherein each channel code
DDS phase control words PiEquation below (1) can be expressed as：
Wherein, 2mFor normalization factor,Expression rounds；
Step 5: FPGA updates M channel phases, the data address for interpolation, and the wave filter system for interpolation are obtained
Number address；
Wherein, the data address for interpolation, is designated as Data_addr；For the filter coefficient address of interpolation, Coe_ is designated as
addr；
The renewal process of M channel phases is as follows：
Phase1=2*2m；
Phasei=Phasei-1+Pi-1, i=2,3,4 ... M (2)
Wherein, Phase1Represent the phase of first passage, PhaseiRepresent the phase of i-th of passage；Phasei-1Represent i-th -1
The phase of individual passage；Pi-1It is the i-th -1 channel code DDS phase control words；The Data_addr of each passage takes PhaseiHigh d
Position, meet 2d>=a, Coe_addr take PhaseiLow m positions in high n positions, 2^n be ROM depth；
Step 6: the data address of the interpolation exported according to step 5 and filter coefficient address, which obtain each passage, is used for interpolation
Input signal and filter coefficient, summation is weighted to data and coefficient, obtains the modulation output signal of every passage；
Step 7: the more phase of new tunnel 1, especially by equation below (3)：
Phase1=Phase1+PM (3)
Wherein, PMIt is m-th channel code DDS phase control words；
Step 8: producing RFD (ready for data) signal after phase of more new tunnel 1 finishes, step is returned to
Two；
So far, from step 1 to step 8, a kind of any bit rate broadband signal generation method based on SDR is completed.
A kind of 2. system that arbitrary bit rate digital modulation signals generation method based on SDR is relied on, it is characterised in that：Including number
According to generation module, filter coefficient look-up table, address update module, convolution module, parallel serial conversion module and DAC；
Wherein, data generating module, filter coefficient look-up table, address update module, convolution module, the equal position of parallel serial conversion module
In FPGA；
The annexation of each module is as follows in system：
Data generating module link address update module and convolution module；Filter coefficient look-up table link address update module and
Acoustic convolver module；Acoustic convolver module connects parallel serial conversion module；Parallel serial conversion module connects DAC；
The function of each module is as follows in system：
The function of data generating module is to produce high bit rate data and be stored in RAM, updates the RAM according to request of data；Filtering
The function of device Coefficient Look-up Table is the filter tap coefficients that design Storage is crossed, to the convolution algorithm of molding filtration；Address is more
The function of new module is when calculating this according to bit rate, sampling clock, parallel channel number and channel value under each clock
Data address and the address of filter coefficient in a lookup table of computing are participated under clock in each channel data generation module RAM；
The function of acoustic convolver module is to carry out the convolution algorithm of molding filtration；The function of parallel serial conversion module is to enter multi-path parallel signal
Row parallel-serial conversion is input to DAC；DAC function is to convert digital signals into analog signal to be sent into balun, obtains final code
The intermediate-freuqncy signal that rate can arbitrarily be set.
3. a kind of arbitrary bit rate digital modulation signals generation method based on SDR according to claim 1, its feature exist
In：In step 3, preferable S values are 6；T and S can with it is equal can also be unequal.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108233924A (en) * | 2018-02-09 | 2018-06-29 | 龙营半导体股份有限公司 | EMI based on phase-modulation reduces device and method |
| CN108572266A (en) * | 2017-12-11 | 2018-09-25 | 深圳市鼎阳科技有限公司 | A kind of waveshape generating device |
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| CN203722632U (en) * | 2013-11-11 | 2014-07-16 | 四川安迪科技实业有限公司 | Satellite communication terminal having multiple receiving channels |
| CN105915241A (en) * | 2016-04-13 | 2016-08-31 | 信阳师范学院 | Method and system for realizing ultrahigh-speed digital orthogonal down conversion and decimation filtering in FPGA |
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| CN108572266A (en) * | 2017-12-11 | 2018-09-25 | 深圳市鼎阳科技有限公司 | A kind of waveshape generating device |
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