CN107425861B - A kind of arbitrary bit rate digital modulation signals generation method based on SDR - Google Patents
A kind of arbitrary bit rate digital modulation signals generation method based on SDR Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0008—Modulated-carrier systems arrangements for allowing a transmitter or receiver to use more than one type of modulation
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Abstract
The arbitrary bit rate digital modulation signals generation method based on SDR that the present invention relates to a kind of, belongs to signal of communication processing technology field.The present invention uses the hardware structure of a FPGA and a single channel DAC, signal is generated using the frequency-dividing clock of fixed sample clock as system processing clock parallel multi-channel, the filter tap coefficients in look-up table designed according to bit rate, sampling clock, parallel channel number and channel value one under each clock carry out selection and carry out molding filtration operation with high code rate data stream, last multi-channel parallel signal obtains the digital intermediate frequency signal that code rate can arbitrarily be set by Digital Up Convert and parallel-serial conversion, is output to balun by DAC and issues analog signal.Compared with conventional transformation sampling clock method, hardware configuration is simpler, and performance is more stable, and practicability is more preferable, and the degree of modularity is higher.
Description
Technical field
The arbitrary bit rate digital modulation signals generation method based on SDR that the present invention relates to a kind of belongs to signal of communication processing
Technical field.
Background technique
As countries in the world are in the keen competition of aerospace field, it is suitable for satellite communication, Unmanned Aerial Vehicle Data Link etc. and uses
The high speed data transmission system of family spacecraft becomes the prior development direction of countries in the world.A kind of powerful, degree of modularity
Height, universal strong, the arbitrary bit rate modulation signal occurrence device that can be used as test equipment or spacecraft load seem especially heavy
It wants.
It should be arbitrary bit rate modulation letter based on the arbitrary bit rate digital modulation signals generation method of SDR (software radio)
Key technology in number generating device.This method supports that all width are combined modulation system including BPSK, QPSK, 8PSK etc., can
Directly to generate arbitrary bit rate modulated intermediate frequency signal, code rate and IF frequency are limited solely by DAC sampling rate.
Conventional method generates the method that arbitrary bit rate signal uses transformed samples clock, also needs in addition to signal processing chip
External clock chip, multi-disc DAC (or a piece of multichannel DAC) and simulation up-conversion chip, lead to not device miniaturization；It is given birth to
At modulated signal code rate can not be continuously any adjustable, lead to not test and application scenarios suitable for all bit rate signals；
In its hardware structure, baseband signal, which need to export through multichannel DAC and simulate quadrature up-conversion, can just obtain intermediate-freuqncy signal, channel
Between imbalance and simulation quadrature carrier phase difference inaccuracy lead to not generate high-quality signal.
Summary of the invention
The purpose of the present invention is to solve the defects of above methods, propose a kind of arbitrary bit rate number based on SDR
Word modulated signal generation method.
The core idea of the invention is as follows: using the hardware structure of a FPGA and a single channel DAC, utilize fixed sample clock
Frequency-dividing clock as system processing clock parallel multi-channel generate signal, under each clock according to code rate, sampling clock,
The filter tap coefficients in look-up table that parallel channel number and channel value were designed one select and and high code rate data
Stream carries out molding filtration operation, and last multi-channel parallel signal obtains code rate and can arbitrarily set by Digital Up Convert and parallel-serial conversion
Digital intermediate frequency signal, by DAC be output to balun issue analog signal.
The purpose of the present invention is what is be achieved through the following technical solutions.
A kind of arbitrary bit rate digital modulation signals generation method based on SDR, steps are as follows:
Step 1: generating high code rate information source using high-speed parallel pseudo-random sequence
The specific method is as follows:
Step 1.1 data generating module handles the LFSR structure parallelization of pseudo-random sequence generator, pseudo-random sequence
Generator is made of maximum length linear feedback shift register (LFSR)；
Conventionally, each mobile bit register can accordingly obtain a pseudo-random sequence value output, it is assumed that
It is 150MHz that system, which handles clock, and the pseudo-random sequence handling capacity that can be generated is also with regard to 150Mbps, it is therefore desirable to using parallel
Change technology obtains higher handling capacity；
Step 1.2 judges whether subsequent module provides request of data, and carries out corresponding operating:
Wherein, subsequent module refers to address update module；
1.21 when address update module provides request of data, and LFSR just to the mobile a bit register of a high position, generates a puppets
Random sequence output feeds back a output results into the low a bit register of LFSR simultaneously；
Wherein a is selected according to the arbitrarily adjustable upper limit of code rate.Such as assume that system processing clock is F1, code rate can set range
Up to Rs need to meet a >=Rs/F1.
1.22 when address update module does not provide request of data, waits request of data；
Step 2: high code rate data caching and management, specifically:
The high speed PRBS that data generating module generates is buffered in a FIFO by step 2.1, and pending datas is waited to ask
It asks enabled, after request of data is enabled to be reached, jumps to step 2.2；
Step 2.2 is enabled according to the request of data of rear end address update module, generates a RFD (ready for data)
Enable signal, and module request data occur to high-speed parallel pseudo-random sequence；
Step 2.3 receives the module request data of step 2.2 output, and FPGA judges whether FIFO is empty, and carries out phase
It should operate:
If 2.31 FIFO non-emptys, rear end address update module exports one a signals, carries out for rear module
Data interpolating；
If 2.32 FIFO empties, to data generating module request data；
Step 3: generating the lookup of the S matched filter coefficients for channel matched according to precision and operation requirement
Table is respectively present in T ROM；According to matched filter secondary lobe to the influence degree of performance, preferred S value is 6；For side
Just operation, T is general and S is equal；
In order to facilitate operation, the depth of ROM is 2^n, and n generally takes 10；
Step 4: FPGA handles the parallel channel M of modulated signal；
Wherein, the selection of M is related with the sample rate that system handles clock and DAC, i.e. M=Fs/F1；
F1 is that system handles clock；Fs is the sample rate of DAC；
The code rate that system requirements generates is denoted as Rs, Rs and channel M, the high speed code DDS in the channel M is generated, wherein each channel code
The phase control words P of DDSiIt can be expressed as following formula (1):
Wherein, 2mSelection for normalization factor, m is related with precision,It indicates to be rounded；
Step 5: FPGA updates M channel phases, the data address for interpolation, and the filtering for interpolation are obtained
Device coefficient address；
Wherein, for the data address of interpolation, it is denoted as Data_addr；For the filter coefficient address of interpolation, it is denoted as
Coe_addr；
The renewal process of M channel phases is as follows:
Phase1=2*2m；
Phasei=Phasei-1+Pi-1, i=2,3,4 ... M (2)
Wherein, Phase1Indicate the phase in first channel, PhaseiIndicate the phase in i-th of channel；Phasei-1It indicates
The phase in (i-1)-th channel；Pi-1It is the phase control words of (i-1)-th channel code DDS；The Data_addr in each channel takes Phasei
High d, meet 2d>=a, Coe_addr take PhaseiLow m in high n, 2^n be ROM depth；
Step 6: according to step 5 output interpolation data address and filter coefficient address obtain each channel in
Slotting input signal and filter coefficient is weighted summation to data and coefficient, obtains the modulation output signal in every channel；
Step 7: the phase of more new tunnel 1, especially by following formula (3):
Phase1=Phase1+PM (3)
Wherein, PMIt is the phase control words of m-th channel code DDS；
Step 8: generating RFD (ready for data) signal after phase of more new tunnel 1 finishes, return to
Step 2；
So far, from step 1 to step 8, a kind of arbitrary bit rate digital modulation signals generation side based on SDR is completed
Method.
A kind of system that the arbitrary bit rate digital modulation signals generation method based on SDR is relied on, including data generate mould
Block, filter coefficient look-up table, address update module, convolution module, parallel serial conversion module and DAC；
Wherein, data generating module, filter coefficient look-up table, address update module, convolution module, parallel serial conversion module
It is respectively positioned in FPGA；
The connection relationship of each module is as follows in system:
Data generating module link address update module and convolution module；Filter coefficient look-up table link address updates mould
Block and acoustic convolver module；Acoustic convolver module connects parallel serial conversion module；Parallel serial conversion module connects DAC.
The function of each module is as follows in system:
The function of data generating module is to generate high code rate data and be stored in RAM, updates the RAM according to request of data；Filter
The function of wave device Coefficient Look-up Table is the filter tap coefficients that design Storage is crossed, the convolution algorithm to molding filtration；Address
The function of update module is when calculating this according to code rate, sampling clock, parallel channel number and channel value under each clock
Data address and the address of filter coefficient in a lookup table of operation are participated under clock in each channel data generation module RAM；
The function of acoustic convolver module is the convolution algorithm for carrying out molding filtration；The function of parallel serial conversion module be by multi-path parallel signal into
Row parallel-serial conversion is input to DAC；The function of DAC is to convert digital signals into analog signal to be sent into balun, obtains final code
The intermediate-freuqncy signal that rate can arbitrarily be set.
Beneficial effect
The present invention devises a kind of arbitrary bit rate digital modulation signals generation method, with existing arbitrary bit rate modulated signal
Generation method is compared, and is had the following beneficial effects:
1. the method for the invention is conducive to the small-sized of equipment only with the hardware structure of a FPGA and a single channel DAC
Change and modularized design, conducive to the realization of software radio, and reduce costs；
2. with signal code rate, continuously any stepping can compared to conventional transformation sampling clock method for the method for the invention
The advantage of tune, truly accomplishes the switching of arbitrary velocity, and adjustable extent is limited solely by DAC sampling rate；
3. using Digital Up Convert in the method for the invention, have compared to quadrature up-conversion method is simulated in conventional method
There is the intermediate-freuqncy signal precision of generation higher, the more stable advantage of performance；
Detailed description of the invention
Fig. 1 is general pseudo-random sequence LFSR circuit diagram；
Fig. 2 is the Parallel Implementation process of LFSR circuit；
Fig. 3 is the system in a kind of arbitrary bit rate digital modulation signals generation method and embodiment 1 based on SDR of the present invention
Composition and method flow schematic diagram；
Fig. 4 is that DAC is direct in a kind of arbitrary bit rate digital modulation signals generation method embodiment 2 based on SDR of the present invention
The code rate of sending is 100Mbps, the frequency spectrum of intermediate frequency 1.2GHz signal；
Fig. 5 is that code rate is in a kind of arbitrary bit rate digital modulation signals generation method embodiment 2 based on SDR of the present invention
100Mbps, the planisphere and EVM of intermediate frequency 1.2GHz signal.
Specific embodiment
The present invention will be further described with reference to the accompanying drawings and examples and detailed description.
Embodiment 1
The present embodiment describes a kind of arbitrary bit rate digital modulation signals generation method based on SDR of the present invention specific real
Flow chart when applying.
Fig. 1 is the pseudorandom sequence for handling the LFSR structure parallelization of pseudo-random sequence generator in the method for the invention
The composition circuit diagram of column generator；
Fig. 2 is to handle the LFSR structure parallelization of pseudo-random sequence generator in the A of the method for the invention step 1
Paralell design.
Fig. 3 is a kind of system that the arbitrary bit rate digital modulation signals generation method based on SDR is relied on composition of the present invention
With method flow diagram.
From figure 3, it can be seen that entering convolution module by data storage, wherein data address after j channel data generates
Selection be calculated by address update module according to code rate, channel information and phase information.Address update module is also controlled simultaneously
The address of filter coefficient look-up table processed.The convolution module output data in j channel is output to DAC by parallel-serial conversion.
Embodiment 2
The present embodiment 2 by send a code rate for the 8PSK signal of 100Mbps for, to specific implementation process of the invention into
Row explanation.
Step A, 8 PN codes are generated first as information flow, are mapped by design requirement, are stored in RAM, are asked according to data
Seek the value in information update RAM.
Step B, 6 look-up tables are generated, each look-up table depth is 1024, is indicated with 12bit, is stored in forming filter
Tap coefficient；
Step C, according to code rate, sampling rate, system processing clock, port number and channel position calculate each channel code
The phase control words of DDS.Code rate Rs is 100Mbps in the embodiment, and sampling rate Fs is 5GHz, and system processing clock F1 is
156.25Mhz, port number M are that 32, m takes 32.
It can basisCalculating there emerged a channel phases.
It step D, can be according to Phasei=Phasei-1+Pi-1, i=2,3,4 ... M updates each channel phases, wherein initially
Value Phase1=2*2m, each clock updates later.
Step E, each channel phases control word being calculated according to step D, taking high 4 is Data_addr；Take low 32
In high 10 be used as Coe_addr.
Step F, taken out from the look-up table of the RAM and step B of step A according to Data_addr and Coe_addr data and
Filter coefficient carries out convolution algorithm, obtains the output in every channel
Step G, according to Phase1=Phase1+P32The more phase of new tunnel 1.
Step H, each channel signal is utilized into parallel DDS technology Digital Up Convert to intermediate frequency 1.2GHz.
Step I, the output in 32 channels is subjected to parallel-serial conversion and is sent into DAC, export analog signal using balun.
So far, from step A to step I, intermediate frequency 1.2GHz is completed, the 8PSK signal of code rate 100Mbps generates.
Fig. 4 is that the code rate that DAC is directly issued in the present embodiment is 100Mbps, and the frequency spectrum of intermediate frequency 1.2GHz signal corresponds to
By the analog signal of balun output in step I.
Fig. 5 is the planisphere and EVM that signal is generated in the present embodiment step I.
The above is presently preferred embodiments of the present invention, and it is public that the present invention should not be limited to embodiment and attached drawing institute
The content opened.It is all not depart from the lower equivalent or modification completed of spirit disclosed in this invention, both fall within the model that the present invention protects
It encloses.
Claims (3)
1. a kind of arbitrary bit rate digital modulation signals generation method based on SDR, which is characterized in that specific step is as follows:
Step 1: generating high code rate information source using high-speed parallel pseudo-random sequence；
Step 2: high bit rate data buffer storage and management, specifically:
The high speed PRBS that data generating module generates is buffered in a FIFO by step 2.1, and request of data is waited to make
Can, after request of data is enabled to be reached, jump to step 2.2；
Step 2.2 is enabled according to the request of data of rear end address update module, and it is enabled to generate a RFD (ready for data)
Signal, and module request data occur to high-speed parallel pseudo-random sequence；
Step 2.3 receives the module request data of step 2.2 output, and FPGA judges whether FIFO is empty, and is accordingly grasped
Make:
If 2.31 FIFO non-emptys, rear end address update module exports one a signals, carries out data for rear module
Interpolation；
If 2.32 FIFO empties, to data generating module request data；
Step 3: the look-up table of the S matched filter coefficients for channel matched is generated according to precision and operation requirement, point
Do not exist in T ROM；
Step 4: FPGA handles the parallel channel M of modulated signal；
Wherein, the selection of M is related with the sample rate that system handles clock and DAC, i.e. M=Fs/F1；
F1 is that system handles clock；Fs is the sample rate of DAC；
The character rate that system requirements generates is denoted as Rs, Rs and channel M, the channel code DDS in the channel M is generated, wherein each channel code
The phase control words P of DDSiIt can be expressed as following formula (1):
Wherein, 2mFor normalization factor,It indicates to be rounded；
Step 5: FPGA updates M channel phases, the data address for interpolation, and the filter system for interpolation are obtained
Number address；
Wherein, for the data address of interpolation, it is denoted as Data_addr；For the filter coefficient address of interpolation, it is denoted as Coe_
addr；
The renewal process of M channel phases is as follows:
Phase1=2*2m；
Phasei=Phasei-1+Pi-1, i=2,3,4 ... M (2)
Wherein, Phase1Indicate the phase in first channel, PhaseiIndicate the phase in i-th of channel；Phasei-1Indicate (i-1)-th
The phase in a channel；Pi-1It is the phase control words of (i-1)-th channel code DDS；The Data_addr in each channel takes PhaseiHigh d
Position meets 2d>=a, Coe_addr take PhaseiLow m in high n, 2^n be ROM depth；
Step 6: obtaining each channel for interpolation according to the data address of the interpolation of step 5 output and filter coefficient address
Input signal and filter coefficient are weighted summation to data and coefficient, obtain the modulation output signal in every channel；
Step 7: the phase of more new tunnel 1, especially by following formula (3):
Phase1=Phase1+PM (3)
Wherein, PMIt is the phase control words of m-th channel code DDS；
Step 8: generating RFD (ready for data) signal after phase of more new tunnel 1 finishes, step is returned to
Two；
So far, from step 1 to step 8, a kind of any bit rate broadband signal generation method based on SDR is completed.
2. a kind of system of the arbitrary bit rate digital modulation signals generation method based on SDR, it is characterised in that: generated including data
Module, filter coefficient look-up table, address update module, convolution module, parallel serial conversion module and DAC；
Wherein, data generating module, filter coefficient look-up table, address update module, convolution module, the equal position of parallel serial conversion module
In FPGA；
The connection relationship of each module is as follows in system:
Data generating module link address update module and convolution module；Filter coefficient look-up table link address update module and
Acoustic convolver module；Acoustic convolver module connects parallel serial conversion module；Parallel serial conversion module connects DAC；
The function of each module is as follows in system:
The function of data generating module is to generate high bit rate data and be stored in RAM, updates the RAM according to request of data；Filtering
The function of device Coefficient Look-up Table is the filter tap coefficients that design Storage is crossed, the convolution algorithm to molding filtration；Address is more
The function of new module is when calculating this according to bit rate, sampling clock, parallel channel number and channel value under each clock
Data address and the address of filter coefficient in a lookup table of operation are participated under clock in each channel data generation module RAM；
The function of acoustic convolver module is the convolution algorithm for carrying out molding filtration；The function of parallel serial conversion module be by multi-path parallel signal into
Row parallel-serial conversion is input to DAC；The function of DAC is to convert digital signals into analog signal to be sent into balun, obtains final code
The intermediate-freuqncy signal that rate can arbitrarily be set.
3. a kind of arbitrary bit rate digital modulation signals generation method based on SDR according to claim 1, feature exist
In: in step 3, preferred S value is 6；T and S can be equal or unequal.
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| CN101119356A (en) * | 2007-07-10 | 2008-02-06 | 京信通信系统（中国）有限公司 | Multichannel digital upconversion system and digital upconversion method |
| KR20120133674A (en) * | 2011-05-31 | 2012-12-11 | 펄스텔레콤(주) | Apparatus for up-converting multichannel digital radio frequency |
| CN203722632U (en) * | 2013-11-11 | 2014-07-16 | 四川安迪科技实业有限公司 | Satellite communication terminal having multiple receiving channels |
| CN105915241A (en) * | 2016-04-13 | 2016-08-31 | 信阳师范学院 | Method and system for realizing ultrahigh-speed digital orthogonal down conversion and decimation filtering in FPGA |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101119356A (en) * | 2007-07-10 | 2008-02-06 | 京信通信系统（中国）有限公司 | Multichannel digital upconversion system and digital upconversion method |
| KR20120133674A (en) * | 2011-05-31 | 2012-12-11 | 펄스텔레콤(주) | Apparatus for up-converting multichannel digital radio frequency |
| CN203722632U (en) * | 2013-11-11 | 2014-07-16 | 四川安迪科技实业有限公司 | Satellite communication terminal having multiple receiving channels |
| CN105915241A (en) * | 2016-04-13 | 2016-08-31 | 信阳师范学院 | Method and system for realizing ultrahigh-speed digital orthogonal down conversion and decimation filtering in FPGA |
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