CN101621279B - Method and device for digital down converter and filtering extraction - Google Patents

Abstract

The invention provides a method and a device for digital down converter and filtering extraction, belonging to the field of signal and information processing. The method comprises the following steps: receiving a middle frequency digital signal, and carrying out polyphase decomposition processing with a polyphase decomposition factor of n on the middle frequency digital signal to obtain n paths of signals subjected to the polyphase decomposition processing and output the signals; receiving n paths of signals subjected to the polyphase decomposition processing, carrying out mixed frequency processing on each path of signal subjected to the polyphase decomposition processing to obtain n paths of signals subjected to the mixed frequency processing and output the signals; and receiving n paths of signals subjected to the mixed frequency processing and carrying out filtering extraction processing on the n paths of signals subjected to the mixed frequency processing according to an extraction factor m to obtain n/m paths of digital down converter signals, wherein m, n and n/m are natural numbers which are not equal to zero, and m is more than or equal to n. The device comprises a polyphase decomposition circuit, a mixed frequency circuit and a filtering extraction circuit. The scheme reduces the operation complexity, improves the stability of the processor, and effectively improves the precision and real-time property of the operation at the same time.

Description

The method and apparatus of Digital Down Convert, filtering extraction

Technical field

The present invention relates to the Signal and Information Processing field, the method and apparatus of particularly a kind of Digital Down Convert, filtering extraction.

Background technology

As everyone knows, the Signal and Information Processing technology is one of subject with the fastest developing speed in the information science in recent decades, and it is promoting the wireless communication technique fast development.How to improve the operational precision and the speed of signal processing; Be the important topic in this information science always, present main flow thinking be with modulus (A/D, Analog/Digital) and digital-to-analogue (D/A; Digital/Analog) transducer is constructed general hardware platform as far as possible near antenna.Owing to receive the restriction of hardware advances level up till now, directly also have certain difficulty from radio frequency sampling, preferred option is at intermediate-frequency section analog signal to be carried out digitlization at present.Because the sampling rate of intermediate-frequency section is than higher, and the bandwidth of the actual baseband signal that comprises information is often narrow, therefore needs advanced line of numbers down-conversion, accomplishes the sampling of frequency spectrum shift and data rate, carries out subsequent processes again.

In order to realize down-converted, prior art provides following scheme:

First kind of digital down converter that scheme provides utilizes input to receive digital intermediate frequency signal; Utilize mixting circuit to digital intermediate frequency signal is carried out Frequency mixing processing, obtain the signal of Frequency mixing processing; Utilize extraction circuit, the factor of choosing according to the characteristic of digital intermediate frequency signal extracts processing to the signal of Frequency mixing processing, obtains extracting the signal of processing; Utilize regulating circuit to regulate processing, the signal of adjusted processing to extracting the signal of handling; Utilize interpolating circuit to increase the sample size of regulating in the signal of handling; Utilize second mixting circuit to handle back signal modulated carrier with interpolating circuit.

The digital down converter that second kind of scheme provides has N independently computing branch road between signal input part and signal output part; Each computing branch road includes in order of connecting and extracts the heterogeneous branch filter circuit that heterogeneous branch mixting circuit that extraction circuit that the factor is N, one make up according to the mutually digital mixting circuit of N and a H according to N phase digital filter circuit (z) expression formula make up; The input of the extraction circuit of each computing branch road and signal input part coupling; The output of branch's filter circuit of each computing branch road outputs to this signal output part after through the add circuit addition; I computing branch road has i-1 clock cycle time-delay with respect to input signal; Said N, i are natural number, 1≤i≤N.

In first kind and second kind of scheme, because the streamline grade of this digital down converter is many, cause computational complexity high, precision is low, real-time difference and poor stability.

Summary of the invention

Technical problem to be solved by this invention provides the method and apparatus of a kind of Digital Down Convert, filtering extraction, and the prior art computational complexity is high to solve, poor stability, and operational precision is low, the problem of real-time difference.

In order to address the above problem, the invention provides the method and apparatus of a kind of Digital Down Convert, filtering extraction, concrete technical scheme is following:

A kind of method of Digital Down Convert comprises:

Receive digital intermediate frequency signal, said reception digital intermediate frequency signal is carried out the heterogeneous resolution process that heterogeneous factoring is n, obtain the signal and the output of the heterogeneous resolution process in n road;

Receive the signal of the heterogeneous resolution process in said n road, the signal of each heterogeneous resolution process in road is carried out Frequency mixing processing, obtain the signal and the output of n road Frequency mixing processing;

Receive the signal of said n road Frequency mixing processing, carry out the filtering extraction processing, obtain n/m way word down-conversion signal according to extracting the signal of factor m to said n road Frequency mixing processing;

Wherein, m, n, n/m are non-vanishing natural number, m≤n.

A kind of method of filtering extraction comprises:

Receive the signal X of n road Frequency mixing processing _{N * 1}, according to adding matrix A before the capable n row of j _{J * n}To input signal X _{N * 1}Add matrix operation before carrying out, obtain capable 1 row of j before add the signal S of matrix operation _{J * 1}, the signal X of said n road Frequency mixing processing _{N * 1}Matrix form for capable 1 row of n;

To preceding adding the signal S of matrix operation _{J * 1}Carry out Filtering Processing, obtain the signal U of the Filtering Processing of capable 1 row of j _{J * 1}

According to adding matrix B behind the capable j row of n/m _{(n/m) * j}Signal U to Filtering Processing _{J * 1}Add matrix operation after carrying out, obtain capable 1 row of n/m after add the signal Y of matrix operation _{(n/m) * 1}, with after add the signal Y of matrix operation _{(n/m) * 1}As the Digital Down Convert signal;

Wherein, m, n, n/m are non-vanishing natural number, m≤n, j>=n.

A kind of digital down converter comprises:

Heterogeneous decomposition circuit is used to receive digital intermediate frequency signal, and said reception digital intermediate frequency signal is carried out the heterogeneous resolution process that heterogeneous factoring is n, obtains the signal and the output of the heterogeneous resolution process in n road;

Mixting circuit is used to receive the signal of the heterogeneous resolution process in said n road, and the signal of each heterogeneous resolution process in road is carried out Frequency mixing processing, obtains the signal and the output of n road Frequency mixing processing;

The filtering extraction circuit is used to receive the signal of said n road Frequency mixing processing, carries out filtering extraction and handles according to extracting the signal of factor m to said n road Frequency mixing processing, obtains n/m way word down-conversion signal;

Wherein, m, n, n/m are non-vanishing natural number, m≤n.

A kind of filter comprises:

Before add the matrix operation unit, be used to receive the signal X of n road Frequency mixing processing _{N * 1}, according to adding matrix A before the capable n row of j _{J * n}To input signal X _{N * 1}Add matrix operation before carrying out, obtain capable 1 row of j before add the signal S of matrix operation _{J * 1}, the signal X of said n road Frequency mixing processing _{N * 1}Matrix form for capable 1 row of n;

Sub-filter unit is used for preceding adding the signal S of matrix operation _{J * 1}Carry out Filtering Processing, obtain the signal U of the Filtering Processing of capable 1 row of j _{J * 1}

After add the matrix operation unit, be used for according to adding matrix B behind the capable j of the n/m row _{(n/m) * j}Signal U to Filtering Processing _{J * 1}Add matrix operation after carrying out, obtain capable 1 row of n/m after add the signal Y of matrix operation _{(n/m) * 1}, with after add the signal Y of matrix operation _{(n/m) * 1}As the Digital Down Convert signal;

Wherein, m, n, n/m are non-vanishing natural number, m≤n, j>=n.

Technical scheme provided by the invention has reduced hardware processor performance demands and power consumption through signal is carried out heterogeneous resolution process; Utilize output tributary signal to be kept in the signal of filtering extraction circuit with Frequency mixing processing to carry out computing; The output tributary signal of treating extraction abandons, and obtains the Digital Down Convert signal, thereby has reduced the streamline grade; Reduced computational complexity; Improve processor stability, simultaneously, effectively improved operational precision and computing real-time.

Description of drawings

Fig. 1 is that degree of parallelism that the embodiment of the invention provides is 2 filtering extraction circuit structure diagram;

Fig. 2 is that degree of parallelism that the embodiment of the invention provides is 2 another kind of filtering extraction circuit structure diagram;

Fig. 3 is that degree of parallelism that the embodiment of the invention provides is 4 filtering extraction circuit structure diagram;

Fig. 4 is the flow chart of the method for the Digital Down Convert that provides of the embodiment of the invention;

Fig. 5 is the structure chart of the digital down converter that provides of the embodiment of the invention;

Fig. 6 is the circuit structure diagram of the digital down converter that provides of the embodiment of the invention;

Fig. 7 is the circuit structure diagram of the another kind of digital down converter that provides of the embodiment of the invention;

Fig. 8 is a kind of Filter Structures figure that the embodiment of the invention provides.

Embodiment

Core concept of the present invention is: through signal is carried out heterogeneous resolution process, reduced hardware processor performance demands and power consumption; Utilize output tributary signal to be kept in the signal of filtering extraction circuit with Frequency mixing processing to carry out computing; The output tributary signal of treating extraction abandons, thereby obtains the Digital Down Convert signal, has reduced the streamline grade; Reduced computational complexity; Improve processor stability, simultaneously, effectively improved operational precision and computing real-time.

Below in conjunction with accompanying drawing and preferred implementation technical scheme of the present invention is elaborated.

In order to realize goal of the invention of the present invention, the present invention has designed a kind of filtering extraction circuit, and the input and output equation of this filtering extraction circuit can be write as Y _{(n/m) * 1}=B _{(n/m) * j}H _{J * j}A _{J * n}X _{N * 1}Form, wherein Y _{(n/m) * 1}Expression filtering extraction circuit output signal is the matrix form that the n/m capable 1 that the signal that obtains behind the filtering extraction is write as is listed as; X _{N * 1}Be the input signal of filtering extraction circuit, can be write as the matrix form of capable 1 row of n; A _{J * n}For adding matrix before the capable n row of j, to input signal X _{N * 1}Add matrix operation A before carrying out _{J * n}X _{N * 1}, just with A _{J * n}Each the row and X _{N * 1}Carry out dot-product operation, obtain the sub-filter unit input signal of capable 1 row of j, be designated as S _{J * 1}H _{J * j}Representing sub-filter unit, is to preceding adding the output signal S of matrix operation _{J * 1}Carry out Filtering Processing, just each row is input to the sub-filtering system Filtering Processing of corresponding row, obtain the signal of the Filtering Processing of capable 1 row of j, be designated as U _{J * 1}B _{(n/m) * j}For adding matrix behind the capable j of the n/m row, according to after add the signal U of matrix to Filtering Processing _{J * 1}Add matrix operation after carrying out, just with B _{(n/m) * j}Each the row and U _{J * 1}Carry out dot-product operation, obtain the output signal Y of the filtering extraction circuit of capable 1 row of n/m _{(n/m) * 1}Here, n, m and n/m are non-vanishing natural number, preferably, and m≤n, j>=n.

Carry out detailed description by way of example in the face of the method for designing of filtering extraction circuit down, but this instance does not constitute the restriction to protection range of the present invention.

If a certain filter system unit impact response h is 2 to be decomposed into h according to factoring ₀(n) and h ₁And satisfy (n),

$\left\{\begin{array}{c}{h}_0\left(n\right)=\left\{h\left(2k\right)\right\}\\ h_1\left(n\right)=\left\{h(2k+1)\right\}\end{array}\right.,$ 0≤k≤(N-1)/2, N is non-vanishing natural number (1)

Pending signal x (n) used the same method be decomposed into

$\left\{\begin{array}{c}{x}_0\left(n\right)=\left\{x\left(2k\right)\right\}\\ x_1\left(n\right)=\left\{x(2k+1)\right\}\end{array}\right.,$ 0≤k≤(N-1)/2, N is non-vanishing natural number (2)

Result y (n) used the same method be decomposed into

$\left\{\begin{array}{c}{y}_0\left(n\right)=\left\{y\left(2k\right)\right\}\\ y_1\left(n\right)=\left\{y(2k+1)\right\}\end{array}\right.,$ 0≤k≤(N-1)/2, N is non-vanishing natural number (3)

If h ₀(n) and h ₁(n) Z-transformation is remembered into H respectively ₀And H ₁, x ₀(n) and x ₁(n) Z-transformation is remembered into X respectively ₀And X ₁, y ₀(n) and y ₁(n) Z-transformation is remembered into Y respectively ₀And Y ₁, then filter input and output equation can be written as

$\left\{\begin{array}{c}{Y}_0=H_0{X}_0+Z^{-2}{H}_1{X}_1\\ {\mathrm{<figure-callout\; id="1"\; label="Y"\; filenames="H2009101656483E00011.png,H2009101656483E00012.png"\; state="\{\{state\}\}">Y</figure-callout>}}_1=H_0{X}_1+H_1{X}_0=(H_0+H_1)(X_0+X_1)-H_0{X}_0-H_1{X}_1\end{array}\right.---\left(4\right)$

Write formula (4) as matrix form, can be obtained the input and output equation of filter

$\left[\begin{array}{c}{Y}_0\\ {\mathrm{<figure-callout\; id="1"\; label="Y"\; filenames="H2009101656483E00011.png,H2009101656483E00012.png"\; state="\{\{state\}\}">Y</figure-callout>}}_1\end{array}\right]=\begin{array}{}\end{array}\left[\begin{array}{ccc}1& 0& z^{-2}\\ -1& 1& -1\end{array}\right]\mathrm{diag}\left[\begin{array}{c}{H}_0\\ H_0+H_1\\ H_1\end{array}\right]\left[\begin{array}{cc}1& 0\\ 1& 1\\ 0& 1\end{array}\right]\left[\begin{array}{c}{X}_0\\ X_1\end{array}\right]---\left(5\right)$

According to formula (5), if the filtering extraction circuit has only kept Y ₀Branch road, then corresponding input and output equation does

$Y_0=\left[\begin{array}{ccc}1& 0& z^{-2}\end{array}\right]\mathrm{diag}\left[\begin{array}{c}{H}_0\\ H_0+H_1\\ {\mathrm{<figure-callout\; id="1"\; label="H"\; filenames="H2009101656483E00011.png,H2009101656483E00012.png"\; state="\{\{state\}\}">H</figure-callout>}}_1\end{array}\right]\left[\begin{array}{cc}1& 0\\ 1& 1\\ 0& 1\end{array}\right]\left[\begin{array}{c}{X}_0\\ X_1\end{array}\right]=\left[\begin{array}{cc}1& z^{-2}\end{array}\right]\mathrm{diag}\left[\begin{array}{c}{H}_0\\ {\mathrm{<figure-callout\; id="1"\; label="H"\; filenames="H2009101656483E00011.png,H2009101656483E00012.png"\; state="\{\{state\}\}">H</figure-callout>}}_1\end{array}\right]\left[\begin{array}{cc}1& 0\\ 0& 1\end{array}\right]\left[\begin{array}{c}{X}_0\\ X_1\end{array}\right]---\left(6\right)$

Adding matrix before in the formula (6) does

Sub-filter unit is diag

After to add matrix be [1 z ^-2], according to formula (6), can obtain degree of parallelism and be 2 filtering extraction circuit structure, as shown in Figure 1.

According to formula (5), if the filtering extraction circuit has only kept Y ₁Branch road, then corresponding input and output equation does

${\mathrm{<figure-callout\; id="1"\; label="Y"\; filenames="H2009101656483E00011.png,H2009101656483E00012.png"\; state="\{\{state\}\}">Y</figure-callout>}}_1=\left[\begin{array}{ccc}-1& 1& -1\end{array}\right]\mathrm{diag}\left[\begin{array}{c}{H}_0\\ H_0+H_1\\ H_1\end{array}\right]\left[\begin{array}{cc}1& 0\\ 1& 1\\ 0& 1\end{array}\right]\left[\begin{array}{c}{X}_0\\ X_1\end{array}\right]---\left(7\right)$

Formula (7) in front of the matrix? Sub-filtering unit for the diag?

added matrix [-1? 1? -1].According to formula (7), can obtain degree of parallelism and be 2 filtering extraction circuit structure, as shown in Figure 2.

It should be noted that factoring all is 2 with extracting the factor for better explanation filtering extraction circuit structure here, so formula (6) and formula (7) they possibly not be simplest formulas, under the simplest formula situation, preceding add matrix and after add matrix and possibly be unit matrix.

Use same quadrat method, can obtain the filtering extraction circuit structure of any degree of parallelism.For example, if be heterogeneous input form { x (4k), x (4k+1) with the pending signal decomposition of filtering extraction circuit; X (4k+2), x (4k+3) }, simultaneously; The system unit impulse response coefficient h of filter is carried out heterogeneous decomposition { h (4k), h (4k+1), h (4k+2); H (4k+3) }, y (4k) and two branch roads of y (4k+2) are abandoned, it is as shown in Figure 3 then to obtain degree of parallelism and be 4 filtering extraction circuit structure.

One embodiment of the present of invention provide a kind of method of Digital Down Convert, and are as shown in Figure 4, comprising:

401, receive digital intermediate frequency signal, carry out the heterogeneous resolution process that heterogeneous factoring is n to receiving digital intermediate frequency signal, obtain the signal and the output of the heterogeneous resolution process in n road;

402, receive the signal of the heterogeneous resolution process in n road, the signal of each heterogeneous resolution process in road is carried out Frequency mixing processing, obtain the signal and the output of n road Frequency mixing processing;

403, the signal of reception n road Frequency mixing processing carries out the filtering extraction processing according to extracting the signal of factor m to said n road Frequency mixing processing, obtains n/m way word down-conversion signal; Wherein, m, n, n/m are non-vanishing natural number, m≤n.

Further, carry out filtering extraction and handle the step that obtains n/m way word down-conversion signal and comprise according to extracting the signal of factor m said n road Frequency mixing processing:

According to adding matrix A before the capable n row of j _{J * n}Signal X to n road Frequency mixing processing _{N * 1}Add matrix operation before carrying out, obtain capable 1 row of j before add the signal S of matrix operation _{J * 1}, the signal X of this n road Frequency mixing processing _{N * 1}Be the matrix form of capable 1 row of n, j>=n, j are non-vanishing natural number;

To preceding adding the signal S of matrix operation _{J * 1}Carry out Filtering Processing, obtain the signal U of the Filtering Processing of capable 1 row of j _{J * 1}

According to adding matrix B behind the capable j row of n/m _{(n/m) * j}Signal U to Filtering Processing _{J * 1}Add matrix operation after carrying out, obtain capable 1 row of n/m after add the signal Y of matrix operation _{(n/m) * 1}, with after add the signal Y of matrix operation _{(n/m) * 1}As the Digital Down Convert signal.

Digital down converter structure chart below in conjunction with shown in Figure 5 carries out detailed description to first embodiment, but this example does not constitute the restriction to protection range of the present invention.In Fig. 5, this low-converter comprises: heterogeneous decomposition circuit, mixting circuit and filtering extraction circuit.Particularly,

The digital intermediate frequency signal of supposing input is x (n), and heterogeneous factoring is n=2.Confirm to extract factor m=2 according to the signal to noise ratio requirement of system and the disposal ability of field programmable gate array (FPGA, Field-Programmable Gate Array) chip, need guarantee to satisfy is that Qwest's sampling thheorem gets final product.

Heterogeneous decomposition circuit obtains the signal after the 2 tunnel heterogeneous resolution process after the signal x (n) of input is carried out heterogeneous resolution process:

$\left\{\begin{array}{c}{f}_{x0}\left(n\right)=x\left(2n\right)\\ f_{x1}\left(n\right)=x(2n+1)\end{array}\right.---\left(8\right)$

In this example, heterogeneous factoring is 2 just in order to describe simple usefulness, in the practical application, can utilize heterogeneous decomposition circuit to carry out factoring and be any non-vanishing natural heterogeneous resolution process.

Mixting circuit is to realize Frequency mixing processing through the signal multiplication of local oscillation signal and the output of heterogeneous decomposition circuit.If it is the heterogeneous decomposition of n that heterogeneous decomposition circuit has carried out factoring, then the local oscillation signal of each branch road of mixting circuit also will carry out the heterogeneous decomposition that factoring is n.Because the heterogeneous factoring n=2 of heterogeneous decomposition circuit, correspondingly, mixting circuit comprises 2 mixing branch circuits, and wherein, first branch circuit of mixting circuit receives first via signal f _X0(n)=and x (2n), second branch circuit of mixting circuit receives the second road signal f _X1(n)=x (2n+1).The centre frequency of supposing pending digital intermediate frequency signal is f _c, sample frequency is f _s, then 2 road local oscillation signals on I road are:

$\left\{\begin{array}{c}{f}_{\mathrm{li}0}\left(n\right)=\sin (2n\&CenterDot;2\mathrm{\&pi;}{f}_c/f_s)\\ f_{\mathrm{li}1}\left(n\right)=\sin [(2n+1)\&CenterDot;2\mathrm{\&pi;}{f}_c/f_s]\end{array}\right.---\left(9\right)$

2 road local oscillation signals on Q road do

$\left\{\begin{array}{c}{f}_{\mathrm{lq}0}\left(n\right)=\cos (2n\&CenterDot;2\mathrm{\&pi;}{f}_c/f_s)\\ f_{\mathrm{lq}1}\left(n\right)=\cos [(2n+1)\&CenterDot;2\mathrm{\&pi;}{f}_c/f_s]\end{array}\right.---\left(10\right)$

Then the mixing results of each branch road of I road does

$\left\{\begin{array}{c}{s}_{I0}=f_{x0}\left(n\right)\&CenterDot;f_{\mathrm{li}0}\left(n\right)=x\left(2n\right)\&CenterDot;\sin (2n\&CenterDot;2\mathrm{\&pi;}{f}_c/f_s)\\ s_{I1}\left(n\right)=f_{x1}\left(n\right)\&CenterDot;f_{\mathrm{li}1}\left(n\right)=x(2n+1)\&CenterDot;\sin [(2n+1)\&CenterDot;2\mathrm{\&pi;}{f}_c/f_s]\end{array}\right.---\left(11\right)$

The mixing results of each branch road of Q road does

$\left\{\begin{array}{c}{s}_{Q0}=f_{x0}\left(n\right)\&CenterDot;f_{\mathrm{lq}0}\left(n\right)=x\left(2n\right)\&CenterDot;\cos (2n\&CenterDot;2\mathrm{\&pi;}{f}_c/f_s)\\ s_{Q1}\left(n\right)=f_{x1}\left(n\right)\&CenterDot;f_{\mathrm{lq}1}\left(n\right)=x(2n+1)\&CenterDot;\cos [(2n+1)\&CenterDot;2\mathrm{\&pi;}{f}_c/f_s]\end{array}\right.---\left(12\right)$

The filtering extraction circuit carries out the filtering extraction processing to the I road signal of mixing and the Q road signal of mixing.

Particularly, the Q road signal of the I road signal of mixing and mixing being input to two same filtering extraction circuit respectively handles.Below in conjunction with formula (7) corresponding hardware structure, the application process of filtering extraction circuit is described.

Add matrix operation, the preceding matrix that adds before the I road signal of formula (11) Frequency mixing processing has carried out earlier First line display carry out computing 1s _I0(n)+0s _I1(n)=s _I0(n), the second line display computing 1s _I0(n)+1s _I1(n)=s _I0(n)+s _I1(n), the third line is represented computing 0s _I0(n)+1s _I1(n)=s _I1(n); Before add the matrix operation result and get into sub-filter unit diag again

Add 3 road signals that matrix operation obtains before being about to and pass through H respectively ₀, H ₀+ H ₁And H ₁Subfilter is carried out Filtering Processing, obtains H respectively ₀s _I0(n), (H ₀+ H ₁) (s _I0(n)+s _I1And H (n)) ₁s _I1(n) three tunnel filtered signals; Sub-filter unit is exported and is added matrix [1 1-1] after signal gets into again, has just obtained the output signal after the Digital Down Convert and has been:

-H ₀s _I0(n)+(H ₀+H ₁)(s _I0(n)+s _I1(n))-H ₁s _I1(n)＝H ₀s _I1(n)+H ₁s _I0(n) (13)

If with this filtering extraction circuit of the input of the signal after the Q road mixing of formula (12), this filtering extraction circuit is output as the Digital Down Convert signal, the result is following:

-H ₀s _q0(n)+(H ₀+H ₁)(s _q0(n)+s _q1(n))-H ₁s _q1(n)＝H ₀s _q1(n)+H ₁s _q0(n) (14)

Wherein, the structure of a complete digital down converter is as shown in Figure 6, and wherein, the heterogeneous factoring of heterogeneous decomposition circuit is 4, and the degree of parallelism of filtering extraction circuit is 2, and extracting the factor is 2, and input signal is x (4k), and down-conversion signal is y _Q0, y _Q1, y _I0And y _I1The structure of the digital down converter that another is complete is as shown in Figure 7, and wherein, the heterogeneous factoring of heterogeneous decomposition circuit is 8, and the degree of parallelism of filtering extraction circuit is 4, and extracting the factor is 2, and input signal is x (4k), and down-conversion signal is y _Q0, y _Q1, y _Q2, y _Q3And y _I0, y _I1, y _I2, y _I3

Based on the inventive concept identical with method, the embodiment of the invention provides a kind of digital down converter, and is as shown in Figure 5, comprising:

Heterogeneous decomposition circuit is used to receive digital intermediate frequency signal, carries out the heterogeneous resolution process that heterogeneous factoring is n to receiving digital intermediate frequency signal, obtains the signal and the output of the heterogeneous resolution process in n road;

Mixting circuit is used to receive the signal of the heterogeneous resolution process in said n road, and the signal of each heterogeneous resolution process in road is carried out Frequency mixing processing, obtains the signal and the output of n road Frequency mixing processing;

The filtering extraction circuit is used to receive the signal of said n road Frequency mixing processing, obtains n/m way word down-conversion signal according to extracting the signal of factor m to said n road Frequency mixing processing;

Wherein, m, n, n/m are non-vanishing natural number, m≤n.

Further, this filtering extraction circuit comprises:

Before add the matrix operation unit, be used for according to adding matrix A before the capable n of the j row _{J * n}Signal X to n road Frequency mixing processing _{N * 1}Add matrix operation before carrying out, obtain capable 1 row of j before add the signal S of matrix operation _{J * 1}, the signal X of this n road Frequency mixing processing _{N * 1}Be the matrix form j>=n of capable 1 row of n, j is non-vanishing natural number;

Sub-filter unit is used for preceding adding the signal S of matrix operation _{J * 1}Carry out Filtering Processing, obtain the signal U of the Filtering Processing of capable 1 row of j _{J * 1}

After add the matrix operation unit, be used for according to adding matrix B behind the capable j of the n/m row _{(n/m) * j}Signal U to Filtering Processing _{J * 1}Add matrix operation after carrying out, obtain capable 1 row of n/m after add the signal Y of matrix operation _{(n/m) * 1}, with after add the signal Y of matrix operation _{(n/m) * 1}As the Digital Down Convert signal.

Based on the inventive concept identical with method, the embodiment of the invention provides a kind of filter, and is as shown in Figure 8, comprising:

Before add the matrix operation unit, be used to receive the signal X of n road Frequency mixing processing _{N * 1}, according to adding matrix A before the capable n row of j _{J * n}To input signal X _{N * 1}Add matrix operation before carrying out, obtain capable 1 row of j before add the signal S of matrix operation _{J * 1}, the signal X of this n road Frequency mixing processing _{N * 1}Matrix form for capable 1 row of n;

Sub-filter unit is used for preceding adding the signal S of matrix operation _{J * 1}Carry out Filtering Processing, obtain the signal U of the Filtering Processing of capable 1 row of j _{J * 1}

After add the matrix operation unit, be used for according to adding matrix B behind the capable j of the n/m row _{(n/m) * j}Signal U to Filtering Processing _{J * 1}Add matrix operation after carrying out, obtain capable 1 row of n/m after add the signal Y of matrix operation _{(n/m) * 1}, with after add the signal Y of matrix operation _{(n/m) * 1}As the Digital Down Convert signal;

Wherein, m, n, n/m are non-vanishing natural number, m≤n, j>=n.

In the technical scheme provided by the invention,, reduced hardware processor performance demands and power consumption through signal is carried out heterogeneous resolution process; Utilize output tributary signal to be kept in the signal of filtering extraction circuit with Frequency mixing processing to carry out computing; The output tributary signal of treating extraction abandons, and obtains the Digital Down Convert signal, thereby has reduced the streamline grade; Reduced computational complexity; Improve processor stability, simultaneously, effectively improved operational precision and computing real-time.

Scheme according to the invention is not restricted to listed utilization in specification and the execution mode.Under technology of the present invention, the those of ordinary skill in field, can make various corresponding changes and distortion, and all these corresponding changes and distortion all belong to the protection range of claim of the present invention according to the present invention.

Claims (4)

1. the method for a Digital Down Convert is characterized in that, comprising:

Receive digital intermediate frequency signal, said reception digital intermediate frequency signal is carried out the heterogeneous resolution process that heterogeneous factoring is n, obtain the signal and the output of the heterogeneous resolution process in n road;

Receive the signal of the heterogeneous resolution process in said n road, the signal of each heterogeneous resolution process in road is carried out Frequency mixing processing, obtain the signal and the output of n road Frequency mixing processing;

Receive the signal of said n road Frequency mixing processing, carry out the filtering extraction processing, obtain n/m way word down-conversion signal according to extracting the signal of factor m to said n road Frequency mixing processing;

Wherein, m, n, n/m are non-vanishing natural number, m≤n;

Wherein, saidly carry out filtering extraction and handle, obtain n/m way word down-conversion signal, comprising according to extracting the signal of factor m to said n road Frequency mixing processing:

According to adding matrix A before the capable n row of j _{J * n}Signal X to n road Frequency mixing processing _{N * 1}Add matrix operation before carrying out, obtain capable 1 row of j before add the signal S of matrix operation _{J * 1}, the signal X of said n road Frequency mixing processing _{N * 1}Be the matrix form of capable 1 row of n, j>=n, j are non-vanishing natural number;

To preceding adding the signal S of matrix operation _{J * 1}Carry out Filtering Processing, obtain the signal U of the Filtering Processing of capable 1 row of j _{J * 1}

According to adding matrix B behind the capable j row of n/m _{(n/m) * j}Signal U to Filtering Processing _{J * 1}Add matrix operation after carrying out, obtain capable 1 row of n/m after add the signal Y of matrix operation _{(n/m) * 1}, with after add the signal Y of matrix operation _{(n/m) * 1}As said Digital Down Convert signal.

2. the method for a filtering extraction is characterized in that, comprising:

Receive the signal X of n road Frequency mixing processing _{N * 1}, according to adding matrix A before the capable n row of j _{J * n}To input signal X _{N * 1}Add matrix operation before carrying out, obtain capable 1 row of j before add the signal S of matrix operation _{J * 1}, the signal X of said n road Frequency mixing processing _{N * 1}Matrix form for capable 1 row of n;

To preceding adding the signal S of matrix operation _{J * 1}Carry out Filtering Processing, obtain the signal U of the Filtering Processing of capable 1 row of j _{J * 1}

According to adding matrix B behind the capable j row of n/m _{(n/m) * j}Signal U to Filtering Processing _{J * 1}Add matrix operation after carrying out, obtain capable 1 row of n/m after add the signal Y of matrix operation _{(n/m) * 1}, with after add the signal Y of matrix operation _{(n/m) * 1}As the Digital Down Convert signal;

Wherein, m, n, n/m are non-vanishing natural number, m≤n, j>=n.

3. a digital down converter is characterized in that, comprising:

Heterogeneous decomposition circuit is used to receive digital intermediate frequency signal, and said reception digital intermediate frequency signal is carried out the heterogeneous resolution process that heterogeneous factoring is n, obtains the signal and the output of the heterogeneous resolution process in n road;

Mixting circuit is used to receive the signal of the heterogeneous resolution process in said n road, and the signal of each heterogeneous resolution process in road is carried out Frequency mixing processing, obtains the signal and the output of n road Frequency mixing processing;

The filtering extraction circuit is used to receive the signal of said n road Frequency mixing processing, carries out filtering extraction and handles according to extracting the signal of factor m to said n road Frequency mixing processing, obtains n/m way word down-conversion signal;

Wherein, m, n, n/m are non-vanishing natural number, m≤n;

Wherein, said filtering extraction circuit comprises:

Before add the matrix operation unit, be used for according to adding matrix A before the capable n of the j row _{J * n}Signal X to n road Frequency mixing processing _{N * 1}Add matrix operation before carrying out, obtain capable 1 row of j before add the signal S of matrix operation _{J * 1}, the signal X of said n road Frequency mixing processing _{N * 1}Be the matrix form of capable 1 row of n, j>=n, j are non-vanishing natural number;

Sub-filter unit is used for preceding adding the signal S of matrix operation _{J * 1}Carry out Filtering Processing, obtain the signal U of the Filtering Processing of capable 1 row of j _{J * 1}

After add the matrix operation unit, be used for according to adding matrix B behind the capable j of the n/m row _{(n/m) * j}Signal U to Filtering Processing _{J * 1}Add matrix operation after carrying out, obtain capable 1 row of n/m after add the signal Y of matrix operation _{(n/m) * 1}, with after add the signal Y of matrix operation _{(n/m) * 1}As the Digital Down Convert signal.

4. a filter is characterized in that, comprising:

Before add the matrix operation unit, be used to receive the signal X of n road Frequency mixing processing _{N * 1}, according to adding matrix A before the capable n row of j _{J * n}To input signal X _{N * 1}Add square before carrying out and fall computing, obtain capable 1 row of j before add the signal S of matrix operation _{J * 1}, the signal X of said n road Frequency mixing processing _{N * 1}Matrix form for capable 1 row of n;

Sub-filter unit is used for preceding adding the signal S of matrix operation _{J * 1}Carry out Filtering Processing, obtain the signal U of the Filtering Processing of capable 1 row of j _{J * 1}

After add the matrix operation unit, be used for according to adding matrix B behind the capable j of the n/m row _{(n/m) * j}Signal U to Filtering Processing _{J * 1}Add matrix operation after carrying out, obtain capable 1 row of n/m after add the signal Y of matrix operation _{(n/m) * 1}, with after add the signal Y of matrix operation _{(n/m) * 1}As the Digital Down Convert signal;

Wherein, m, n, n/m are non-vanishing natural number, m≤n, j>=n.

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