CN109142820B - Pulse wave generating device - Google Patents
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- CN109142820B CN109142820B CN201811125028.2A CN201811125028A CN109142820B CN 109142820 B CN109142820 B CN 109142820B CN 201811125028 A CN201811125028 A CN 201811125028A CN 109142820 B CN109142820 B CN 109142820B
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
A pulse wave generating device comprises a processor, a jitter pulse width coefficient determining module, a jitter generating module and an edge data determining module; the jitter pulse width coefficient determining module can determine a jitter pulse width coefficient according to jitter pulse configuration parameters calculated by the processor according to jitter pulse parameters input by a user; the jitter generating module can determine the edge generating time of the pulse wave according to the pulse width coefficient with jitter and output the phase to the edge data determining module; the edge data determining module determines the edge data of the pulse wave corresponding to the pulse address by taking the phase as the pulse address to obtain the digital pulse wave with jitter. The jitter pulse width coefficient can be determined according to the jitter pulse parameters, and the edge generation time of the pulse wave is controlled through the jitter pulse width coefficient, so that the jitter of the pulse wave is controlled, and the jitter of the generated pulse wave can be adjusted as required.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a pulse wave generating device.
Background
In the electronic technology fields such as electronic computers, communications, radars, televisions, automatic control, remote control and measurement, radio navigation, test and measurement technologies, Pulse waves play a very important role, for example, Pulse Width Modulation (PWM) waves can be generated by Modulation in communications, and the Pulse wave can be used for testing the step response of circuits, can be used as a radio Pulse wave of radars, and the like.
The jitter of a signal is generally defined as the short-term deviation of the signal from its ideal position at a specific time, and the jitter diagram of the signal can be seen in fig. 1, where the deviations e 1-e 6 of the real pulse wave from the ideal pulse wave are the jitter of the signal. The jitter of the signal is usually caused by noise or other interference factors in the system, and may cause the processor to acquire an erroneous signal in the signal acquisition and processing process, thereby reducing the transmission performance of the digital signal. The performance of the system under different signal qualities can be simulated by adding jitter to the signal, and the method has important significance in the aspects of research and development, test and the like of electronic devices, but the jitter of the pulse wave cannot be adjusted according to actual requirements at present.
Disclosure of Invention
The application provides a pulse wave generating device to generate a pulse wave with adjustable jitter.
The pulse wave generating device comprises a processor, a jitter pulse width coefficient determining module, a jitter generating module and an edge data determining module;
the processor is used for calculating jitter pulse configuration parameters according to jitter pulse parameters input by a user and configuring the jitter pulse configuration parameters to the jitter pulse width coefficient determining module, the jitter generating module and the edge data determining module;
the jitter pulse width coefficient determining module is used for determining a jitter-carrying pulse width coefficient according to the jitter pulse configuration parameters and outputting the jitter-carrying pulse width coefficient to the jitter generating module;
the jitter generating module is used for determining the edge generating time of a pulse wave according to the jitter pulse configuration parameters and the jittered pulse width coefficient, and outputting a phase to the edge data determining module at the edge generating time;
and the edge data determining module is used for determining edge data of the pulse wave according to the phase output by the jitter generating module and the configuration parameters of the jitter pulse to obtain the digital pulse wave with jitter.
According to the pulse wave generating device of the embodiment, the jitter pulse width coefficient determining module can determine the jitter pulse width coefficient according to the jitter pulse configuration parameters, and then the jitter generating module determines the edge generating time of the pulse wave according to the jitter pulse width coefficient and the edge data determining module determines the edge data of the pulse wave at the time, so that the deviation of the pulse wave relative to the ideal position of the pulse wave can be controlled by controlling the edge generating time, namely the jitter of the pulse wave is controlled; the jitter pulse configuration parameters are obtained by calculating the jitter pulse parameters input by the user, so that the jitter degree of the pulse wave can be adjusted according to the jitter pulse parameters input by the user, and the jitter of the generated pulse wave can be adjusted.
Drawings
FIG. 1 is a diagram illustrating jitter of a signal;
FIG. 2 is a diagram illustrating relevant parameters of a pulse wave;
FIG. 3 is a schematic diagram of a DDS generating a pulse wave in the prior art;
FIG. 4 is a schematic structural diagram of a pulse wave generator according to an embodiment of the present application;
FIG. 5 is a schematic structural diagram of a pulse wave generator according to an embodiment of the present application;
FIG. 6 is a flow chart of a method of generating a pulse wave according to an embodiment of the present application.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning.
In this context, the description of the relevant parameters of the pulse wave can be seen in fig. 2, as shown in fig. 2, a represents the rising edge time of the pulse wave, B represents the falling edge time of the pulse wave, C represents the pulse width (also referred to as duty ratio) of the pulse wave, and D represents the period of the pulse wave, which reflects the frequency of the pulse, which can represent the pulse frequency.
At present, a Direct Digital Synthesis (DDS) technique is generally used to generate pulse waves, a schematic diagram of the pulse waves generated can be seen in fig. 3, a frequency control register stores a frequency control word FTW input by a user, a phase accumulator performs phase accumulation in each clock cycle according to the FTW to obtain a phase value, then high bits of the phase value are intercepted as an address of a waveform memory to obtain an output of the waveform memory, and the output is converted by a Digital-to-analog converter (DAC) to generate the required pulse waves. When the pulse wave is generated by adopting the technology, the jitter of one system clock period exists, and the jitter degree can not be controlled.
In the embodiment of the invention, a jitter pulse configuration parameter is calculated according to a jitter pulse parameter input by a user, a pulse width coefficient with jitter is determined according to the jitter pulse configuration parameter, then the edge generation time of a pulse wave is determined according to the jitter pulse configuration parameter and the pulse width coefficient with jitter, the edge data of the pulse wave at the time is determined, and the pulse wave with jitter required by the user is obtained.
The first embodiment is as follows:
referring to fig. 4, fig. 4 is a schematic structural diagram of a pulse wave generator according to an embodiment of the present application, where the pulse wave generator includes a processor 1, a jitter pulse width coefficient determining module 2, a jitter generating module 3, and an edge data determining module 4.
Specifically, the processor 1 is configured to calculate a jitter pulse configuration parameter according to a jitter pulse parameter input by a user, and configure the jitter pulse configuration parameter to the jitter pulse width coefficient determining module 2, the jitter generating module 3, and the edge data determining module 4. The jitter pulse parameters input by the user may include a frequency f of the pulse wave, a pulse width, a rising time rise, a falling time fall, a jitter period standard deviation dev, and a jitter distribution mode, where dev and the jitter distribution mode are jitter parameters for controlling jitter of the pulse wave. The jitter pulse configuration parameters calculated by the processor 1 according to the pulse parameters comprise frequency control words FTW1, FTW2, FTW3, a first pulse width parameter P and a random number coefficient R, and a jitter distribution mode is also used as the jitter pulse configuration parameters, wherein FTW1 is proportional to f, the ratio of FTW1 to FTW2 is proportional to rise and inversely proportional to 1/(2 f), the ratio of FTW1 to FTW3 is proportional to fall and inversely proportional to 1/(2 f), P is calculated according to f, width, rise and fall, and R is proportional to dev.
In one embodiment, FTW1, FTW2, FTW3, P, and R can be calculated from the following equations:
the formula for FTW1 is:
where M is the system bit width, fclkA system clock;
the formula for FTW2 is:
the formula for FTW3 is:
the formula for P is:
wherein, N represents a period, represents a second pulse width parameter, and the value of the second pulse width parameter can be designed according to the actual requirement, but the rising edge and the falling edge of the pulse wave can be ensured to be generated;
the formula for R is: R-K dev, where K is a system parameter, depends on the actual design of the system, such as the scaling of the devices used in the design.
The jitter pulse width coefficient determining module 2 is configured to determine a jitter-carrying pulse width coefficient according to the jitter pulse configuration parameters FTW1, FTW2, FTW3, P, and R obtained by the processor 1, for example, the jitter pulse configuration parameters may be calculated through a certain logic operation to obtain the jitter-carrying pulse width coefficient, and then the jitter-carrying pulse width coefficient is output to the jitter generating module 3.
The jitter generating module 3 is configured to determine an edge generation time of the pulse wave according to the jitter pulse configuration parameter and the pulse width coefficient with jitter, that is, a rising edge time or a falling edge time of the pulse wave, and output a phase to the edge data determining module 4 at the edge generation time. The edge data determining module 4 is configured to determine edge data of the pulse wave according to the phase output by the jitter generating module 3 and the jitter pulse configuration parameter configured by the processor 1, so as to obtain a digital pulse wave with jitter.
Specifically, taking the signal jitter diagram shown in fig. 1 as an example, for an ideal pulse wave, it starts to generate a rising edge at time t 1. When the pulse wave generating device of the invention is adopted to generate pulse waves, a user inputs jitter pulse parameters according to needs, the processor 1 calculates jitter pulse configuration parameters according to the jitter pulse parameters, the jitter pulse width coefficient determining module 2 determines a pulse width coefficient with jitter according to the jitter pulse configuration parameters and outputs the pulse width coefficient with jitter to the jitter generating module 3, at this time, the jitter generating module 3 determines the edge generating time of the pulse waves according to the pulse width coefficient with jitter, as shown in fig. 1, the pulse waves start to generate a rising edge at the time t2, at this time, for actually generated pulse waves, the time of the rising edge generating time has a time delay of t2-t1 relative to ideal pulse waves, at this time, the edge data determining module 4 determines the edge data of the pulse waves, and further, the generated pulse waves have short-term deviation of e2 relative to ideal positions, namely, the actually generated pulse waves have jitter, and the degree of the jitter is determined by the pulse width coefficient with the jitter.
Therefore, when the jitter pulse parameters input by the user are changed, the configuration parameters of the jitter pulse are changed, and the determined pulse width coefficient with jitter is also changed, so that the generation time of the edge of the pulse wave is also changed, and the pulse wave with the needed jitter is generated. Therefore, the generation time of the edge of the pulse wave can be controlled according to the jitter pulse parameters input by a user, the pulse wave with the needed jitter is obtained, the jitter degree of the pulse wave is changed along with the change of the jitter pulse parameters, and the adjustment of the jitter of the pulse wave is realized.
The pulse wave generator provided in this embodiment can determine the pulse width coefficient with jitter according to the jitter pulse parameter input by the user, further determine the edge generation time of the pulse wave according to the pulse width coefficient with jitter, and control the deviation of the pulse wave relative to the ideal position thereof by controlling the edge generation time, that is, control the generation of the pulse wave jitter and the size of the jitter by controlling the edge generation time, so as to change the jitter degree of the pulse wave by adjusting the jitter pulse parameter, generate the pulse wave with the required jitter, and implement control and adjustment of the jitter of the pulse wave.
Example two:
based on the first embodiment, fig. 5 shows the structure of a pulse wave generation apparatus of a specific embodiment, which includes a processor 1, a jitter pulse width coefficient determination module 2, a jitter generation module 3, and an edge data determination module 4. The working mode of the processor 1 is the same as that in the first embodiment, and is not described herein again; the jitter generating module 3 comprises a first phase accumulator 31 and a comparator 32.
The first phase accumulator 31 is configured to start operating with FTW1 as a frequency control word after receiving the jitter pulse configuration parameter calculated by the processor 1, and output a phase accumulation value to a first terminal of the comparator 32.
The second end of the comparator 32 is connected to the output end of the jitter pulse width coefficient determining module 2, and the comparator 32 is configured to compare the input of the first end with the input of the second end thereof, determine a time when the input of the first end is greater than the input of the second end thereof as an edge generation time of the pulse wave, that is, a rising edge time or a falling edge time of the pulse wave, and output a phase to the edge data determining module 4, that is, output a comparison result of the edge generation time to the edge data determining module 4.
Specifically, the edge data determination block 4 includes a first multiplier 41, a second phase accumulator 42, and an edge data memory 43. The comparator 32 is specifically configured to input the comparison result to the first end of the first multiplier 41; the comparator 32 controls the output of the jitter pulse width coefficient determining module 2 to alternately switch between the first jitter pulse width coefficient and the second jitter pulse width coefficient each time when the input of the first end of the comparator is larger than the input of the second end of the comparator, controls the second end input of the first multiplier 41 to alternately switch between FTW3/FTW1 and FTW2/FTW1, and controls the frequency control word of the second phase accumulator 42 to alternately switch between FTW3 and FTW 2; meanwhile, the comparator 32 is further configured to control the phase accumulated value of the first phase accumulator 31 to decrease by the second pulse width parameter N when the input of the second end of the comparator is switched to the second dither pulse width coefficient; the first jitter pulse width coefficient and the second jitter pulse width coefficient are both the jitter pulse width coefficients determined by the jitter pulse width coefficient determining module 2. Specifically, the comparator 32 is configured to compare an input at a first end thereof with an input at a second end thereof, and output an excess portion as a comparison result to the first end of the first multiplier 41 when the input at the first end is greater than the first jitter pulse width coefficient or the second jitter pulse width coefficient output by the jitter pulse width coefficient determining module 2; that is, the comparator 32 compares the phase accumulated value of the first phase accumulator 31 with the dither pulse width coefficient output from the dither pulse width coefficient determining module 2, and outputs a portion of the phase accumulated value exceeding the dither pulse width coefficient to the first terminal of the first multiplier 41 as a comparison result.
The first multiplier 41 is configured to multiply the inputs of the first terminal and the second terminal thereof, and output the operation result to the second phase accumulator 42.
The second phase accumulator 42 is used to output a phase to the edge data memory 43 every clock cycle, with FTW3 or FTW2 as a frequency control word, and with the operation result of the first multiplier 41 as an initial phase. The edge data memory 43 determines the edge data of the pulse wave corresponding to the pulse address by using the phase output from the second phase accumulator 42 as the pulse address, and obtains a digital pulse wave with jitter.
In practical applications, the edge data memory 43 may store a corresponding relationship between the pulse address and the pulse wave edge data in advance, so that the phase output by the second phase accumulator 42 may be used as the pulse address, and the edge data corresponding to the address may be found from the corresponding relationship, where the corresponding relationship may be configured by the processor 1.
In the above apparatus, the jitter pulse width coefficient determining module 2 includes a pulse width modulation coefficient generating module 21, a register 22 and an adder 23, and the second end of the comparator 32 is connected to the output end of the jitter pulse width coefficient determining module 2, specifically: a second terminal of comparator 32 is connected to an output of adder 23.
The pulse width modulation coefficient generating module 21 is configured to generate a pulse width modulation coefficient R according to a jitter distribution pattern in jitter pulse configuration parameters and a random number coefficient R after receiving the jitter pulse configuration parameters calculated by the processor 1, and output R to a first end of the adder 23; the comparator 32 controls the pwm coefficient generation block 21 to update r once every time the input at the first end is greater than the input at the second end. Specifically, when the comparator 32 compares that the accumulated value of the phase input at the first end is greater than the first jitter pulse width coefficient or the second jitter pulse width coefficient input at the second end, the pwm coefficient generating module 21 is controlled to update r once.
An output of register 22 is coupled to a second input of adder 23, register 22 being arranged to store P and N and to alternate the output of its output between P and N each time the input at the first terminal of comparator 32 is greater than the input at the second terminal of comparator 32.
The adder 23 is configured to add the inputs of the first terminal and the second terminal thereof, and input the operation result to the second terminal of the comparator 32.
The first jitter pulse width coefficient is P + r, and the second jitter pulse width coefficient is N + r. Where N is less than or equal to half of the upper phase limit of the first phase accumulator 31 to ensure that the pulse wave generating means can generate the rising and falling edges of the pulse wave. In practical applications, the upper phase limit of the first phase accumulator 31 may be 720 degrees, and the value of N may be 360 degrees.
Based on this, when the register 22 outputs P, the adder 23 adds r generated by the pwm coefficient generating module 21 to P, so as to obtain a first jitter pulse width coefficient (i.e. a pulse width coefficient with jitter) P + r, which is input to the comparator 32; when the comparator 32 compares that the phase accumulated value output by the first phase accumulator 31 is greater than P + r, the part of the phase accumulated value exceeding P + r is output to the first multiplier 41 as a comparison result, and the register 22 is controlled to output N and update r once; at this time, the adder 23 outputs the second dither pulse width coefficient N + r. When the comparator 32 compares that the phase accumulated value output by the first phase accumulator 31 is greater than N + r, the part of the phase accumulated value exceeding N + r is output to the first multiplier 33 as a comparison result, and meanwhile, the phase accumulated value of the first phase accumulator 31 is controlled to be reduced by N, the register 22 is controlled to output P, and r is updated once; when the comparator 32 compares that the accumulated value of the phase output by the first phase accumulator 31 is greater than P + r or N + r, the comparator 32 controls the second end input of the first multiplier 41 to alternately switch between FTW3/FTW1 and FTW2/FTW1, and controls the frequency control word of the second phase accumulator 42 to alternately switch between FTW3 and FTW 2; thereafter, the process is cycled as such. In this process, since FTW2 is proportional to the rise time rise of the pulse wave and FTW3 is proportional to the fall time fall of the pulse wave, the rise time and the fall time of the pulse wave can be controlled by FTW2 and FTW3, respectively; further, the comparator 32 compares the phase accumulated value output from the first phase accumulator 31 with the P + r or N + r output from the adder 23, and determines the generation timing of the rising edge or the falling edge of the pulse wave according to the comparison result, so as to control the generation of the rising edge and the falling edge of the pulse wave, and further control the pulse width of the pulse wave according to the generation timing of the rising edge and the falling edge, for example, if the first rising edge is generated at the time of 0 second and the first falling edge is generated at the time of 1 second, the pulse width of the pulse wave is 1 second.
In a specific embodiment, the pwm coefficient generation block 21 includes a random number generation block 211 and a second multiplier 212. The random number generating module 211 is configured to generate a random number a according to a jitter distribution pattern after receiving the jitter pulse configuration parameter, and output the random number a to a first end of the second multiplier 212; a second terminal of the second multiplier 212 receives the input R, and the second multiplier 212 is configured to multiply the input of the first terminal and the input of the second terminal to obtain a pulse width modulation coefficient R (i.e., R ═ a × R), and output the obtained R to the first terminal of the adder 23. At this time, when the comparator 32 compares that the accumulated value of the phase output by the first phase accumulator 31 is greater than P + r or N + r, the comparator 32 controls the pwm coefficient generating module 21 to update r once, which is: the comparator 32 controls the random number generation module 211 to regenerate a random number according to the jitter distribution pattern, which is equivalent to updating a.
In practical applications, the random number generation module 211 may generate various random data distributed according to different rules according to a set jitter distribution pattern, for example, random data distributed according to a gaussian distribution, and the size of the generated random numbers may be distributed between 0 and 1 according to the jitter distribution pattern.
Based on the pulse wave generating apparatus shown in fig. 5, fig. 6 shows a flowchart of a method of generating a pulse wave, which may include the steps of:
step 101: and calculating the jitter pulse configuration parameters.
The processor 1 calculates the jitter pulse configuration parameters according to the jitter pulse parameters f, width, rise, fall, dev and the jitter distribution pattern input by the user by using the calculation formulas of the jitter pulse configuration parameters FTW1, FTW2, FTW3, P and R, for example, the jitter pulse configuration parameters are calculated by using the calculation formulas described in the first embodiment, and the jitter distribution pattern is also used as the jitter pulse configuration parameters. After the processor 1 calculates the jitter pulse configuration parameters, the jitter pulse configuration parameters are configured to the jitter pulse width coefficient determining module 2, the jitter generating module 3 and the edge data determining module 4.
Step 102: the first phase accumulator operates.
After the jitter generation module 3 receives the configuration parameters of the jitter pulses, the first phase accumulator 31 starts to operate with FTW1 as a frequency control word, 0 as an initial phase and a preset upper phase limit a, accumulates FTW1 under the action of the system clock and outputs a phase accumulated value to the first end of the comparator 32, for example, if the output phase of the first phase accumulator 31 at the current time is a1, the next system clock outputs a1+ FTW 1; in practical applications, the upper phase limit a may be 720 degrees.
Step 103: resulting in a pulse width modulation factor r.
The random number generation module 211 receives a command for controlling jitter distribution, that is, receives a jitter distribution pattern in the jitter pulse configuration parameters, outputs a random number a having a distribution rule, such as gaussian distribution, and a size of 0 to 1 according to the jitter distribution pattern, and inputs the random number a to the first end of the second multiplier 212; at this time, the second multiplier 212 multiplies the random number a by a random number coefficient R in the dither pulse arrangement parameter to obtain a pulse width modulation coefficient R, i.e., R ═ a × R, and then inputs R to the first end of the second multiplier 212.
Step 104: a first dither pulse width coefficient is calculated.
The register 22 outputs P to the adder 23, the adder 23 adds P and r output by the second multiplier 212 to obtain a pulse width coefficient P + r with jitter, i.e. a first jitter pulse width coefficient, and then the P + r is input to the second end of the comparator 32.
Step 105: the comparator performs comparison control according to a first preset rule.
Specifically, the comparator 32 compares the phase accumulated value output by the first phase accumulator 31 with P + r output by the adder 23, when the phase accumulated value is greater than P + r, the comparator 32 outputs the part of the phase accumulated value exceeding P + r as the comparison result to the first multiplier 41, meanwhile, the random number generation module 211 is controlled to update the random number a according to the jitter distribution pattern, the control register 22 outputs N to the adder 23, the second end input of the first multiplier 41 is controlled to be FTW3/FTW1, and the frequency control word of the second phase accumulator 42 is controlled to be FTW 3. At this time, the second multiplier 212 outputs a new value r, the data input from the adder 23 to the second end of the comparator 32 is switched to N + r, and the comparator 32 starts to compare the accumulated value of the phase output from the first phase accumulator 31 with the N + r output from the adder 23. In practical applications, the value of N is less than or equal to half of the upper phase limit of the first phase accumulator 31. In one embodiment, the upper phase limit of the first phase accumulator 31 may be 720 degrees, and N may be 360 degrees.
Step 106: an initial phase of the second phase accumulator is calculated.
The first multiplier 33 multiplies an input at a first terminal thereof by an input at a second terminal thereof, and outputs the operation result to the second phase accumulator 42 as an initial phase of the second phase accumulator 42.
Step 107: the pulse address is determined.
The second phase accumulator 42 starts operation with the operation result output from the first multiplier 41 as an initial phase and the frequency control word determined by the comparator 32 as a frequency control word, and starts operation at the system clock fclkThe phase of each clock output is output as a pulse address to the edge data memory 43.
Step 108: edge data is acquired.
The edge data memory 43 reads out edge data of a pulse wave corresponding to the pulse address with the phase output from the second phase accumulator 42 as the pulse address, and obtains a digital pulse wave with jitter. Specifically, the edge data memory 43 may store a corresponding relationship between pulse addresses and pulse wave edge data in advance, for example, the edge data memory 43 stores a set of rising edge data and a set of falling edge data, and the storage mode is that each pulse address corresponds to one edge data; when the second phase accumulator 42 operates with the operation result of the first multiplier 41 as the initial phase, one phase is output to the edge data memory 43 every clock cycle, the edge data memory 43 searches one edge data corresponding to the phase from the above correspondence, and the second phase accumulator 42 outputs a plurality of phases in the process from the initial phase to the phase upper limit, and the plurality of phases correspond to the plurality of edge data, so that rising edge data or falling edge data of the pulse wave can be obtained. In practical application, the edge data memory 43 may store only one set of rising edge data, and the set of rising edge data is a set of falling edge data after being arranged in reverse order, so that every two pulse addresses correspond to one rising edge data, which is equivalent to every pulse address corresponding to one edge data; similarly, only one set of falling edge data may be stored in the edge data memory 43.
Step 109: and the comparator performs comparison control according to a second preset rule.
Specifically, when the comparator 32 compares that the phase accumulated value output by the first phase accumulator 31 is greater than N + r output by the adder 23, the part of the phase accumulated value exceeding N + r is output to the first multiplier 41 as the comparison result, and at the same time, the phase accumulated value of the first phase accumulator 31 is controlled to decrease by N, the random number generation module 211 is controlled to update the random number a according to the jitter distribution pattern, the control register 22 outputs P to the adder 23, the second end input of the first multiplier 33 is controlled to be FTW2/FTW1, and the frequency control word of the second phase accumulator 42 is controlled to be FTW 2. At this time, the second multiplier 212 outputs a new value r, the data input from the adder 23 to the second end of the comparator 32 is switched to P + r, and the comparator 32 compares the accumulated value of the phase output from the first phase accumulator 31 with the P + r output from the adder 23.
Step 110: step 106 to step 108 are executed.
Thereafter, the process of step 103 to step 110 is executed in a loop.
According to the generation process of the pulse wave, the pulse width coefficient with jitter can be determined according to jitter pulse parameters input by a user, the edge generation time of the pulse wave is further determined according to the pulse width coefficient with jitter, the deviation of the pulse wave relative to the ideal position of the pulse wave is controlled by controlling the edge generation time, namely the generation of the jitter of the pulse wave and the size of the jitter are controlled by controlling the edge generation time, so that the pulse wave with the needed jitter is obtained, and the jitter is adjustable. In the process, on one hand, the larger the initial phase of the second phase accumulator is, the larger the first point of the edge of the generated pulse wave is, the more ahead the waveform of the pulse wave in one clock cycle is, and similarly, the smaller the initial phase is, the more behind the waveform of the pulse wave in one clock cycle is, the waveform jitter of one clock cycle existing in the pulse wave generated by adopting the DDS principle in the prior art can be offset by using the advance amount or the delay amount, so that the jitter of the finally generated pulse wave is the jitter required by a user, and the jitter degree of the pulse wave can be better changed by adjusting the jitter pulse parameter. On the other hand, the rising edge time and the falling edge time of the pulse wave can be controlled by FTW2 and FTW3, respectively, and simultaneously the phase accumulated value output by the first phase accumulator is compared with the pulse width coefficient with jitter by using a comparator, and the generation timing of the rising edge or the falling edge of the pulse wave is determined by the comparison result, so that the generation of the rising edge and the falling edge of the pulse wave is controlled, and further the pulse width can be controlled by the generation timing of the rising edge and the falling edge. And moreover, the pulse width coefficient with jitter is obtained by adding a pulse width modulation coefficient and a pulse width parameter, the pulse width modulation coefficient is proportional to a random number, so that the pulse width coefficient with jitter is randomly adjustable, the generation time of a rising edge and a falling edge of a pulse wave is adjustable, adjustable random jitter is generated, the distribution rule of jitter is controlled by adjusting a jitter distribution mode to enable a random number generation module to generate random numbers with various distribution rules, and the jitter of the pulse wave can be adjusted according to the requirements of users. In addition, the upper limit of the jitter range of the pulse wave is determined by the period of the pulse wave, which is generally not more than 1/4 of the period, and the lower limit of the jitter and the adjusted step value are determined by the advance of the minimum rising edge or the minimum falling edge of the pulse wave, which can be realized by adjusting the initial phase of the second phase accumulator, and the step amount of the jitter can reach ps (picosecond) magnitude.
In practical application, the processor in each of the above embodiments may be an embedded processor, and mainly implements functions such as user interaction, setting of jitter pulse parameters, and calculation of jitter pulse configuration parameters. The jitter pulse width coefficient determining module, the jitter generating module and the edge data determining module may be implemented by a Field-Programmable Gate Array (FPGA).
In practical applications, the pulse wave generator according to each of the above embodiments further includes a digital-to-analog converter (DAC) and an analog channel, after obtaining the digital pulse wave with jitter, the edge data determining module sends the digital pulse wave with jitter to the DAC, and after the DAC converts the digital pulse wave with jitter into an analog signal (i.e., the analog pulse wave with jitter), the analog channel outputs the analog pulse wave with jitter.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.
Claims (9)
1. The pulse wave generating device is characterized by comprising a processor, a jitter pulse width coefficient determining module, a jitter generating module and an edge data determining module;
the processor is used for calculating jitter pulse configuration parameters according to jitter pulse parameters input by a user and configuring the jitter pulse configuration parameters to the jitter pulse width coefficient determining module, the jitter generating module and the edge data determining module; the jitter pulse parameters comprise frequency f, pulse width, rise time rise, fall time fall, jitter period standard deviation dev and a jitter distribution mode;
the jitter pulse width coefficient determining module is used for determining a jitter-carrying pulse width coefficient according to the jitter pulse configuration parameters and outputting the jitter-carrying pulse width coefficient to the jitter generating module;
the jitter generating module is used for determining the edge generating time of a pulse wave according to the jitter pulse configuration parameters and the jittered pulse width coefficient, and outputting a phase to the edge data determining module at the edge generating time;
the jitter pulse configuration parameters comprise a frequency control word FTW1, a frequency control word FTW2, a frequency control word FTW3, a first pulse width parameter P, a random number coefficient R and the jitter distribution pattern;
wherein the frequency control word FTW1 is proportional to the frequency f;
the ratio of the frequency control word FTW1 and the frequency control word FTW2 is proportional to the rise time rise and inversely proportional to 1/(2 f), f being the frequency in the jittered pulse parameter;
the ratio of the frequency control word FTW1 to the frequency control word FTW3 is directly proportional to the fall time fall and inversely proportional to 1/(2 f);
the first pulse width parameter P is calculated according to the frequency f, the pulse width, the rise time rise and the fall time fall;
the random number coefficient R is in direct proportion to the standard deviation dev of the jitter period;
and the edge data determining module is used for determining edge data of the pulse wave according to the phase output by the jitter generating module and the configuration parameters of the jitter pulse to obtain the digital pulse wave with jitter.
2. The pulse wave generating apparatus according to claim 1, wherein the jitter generating module includes a first phase accumulator and a comparator;
the first phase accumulator is used for starting to run by taking the frequency control word FTW1 as a frequency control word after receiving the jitter pulse configuration parameter, and outputting a phase accumulated value to a first end of the comparator;
and the second end of the comparator is connected with the output end of the jitter pulse width coefficient determining module, the comparator is used for comparing the input of the first end with the input of the second end, determining the moment when the input of the first end is greater than the input of the second end as the edge generation moment of the pulse wave, and outputting the comparison result of the edge generation moment to the edge data determining module.
3. The pulse wave generating apparatus according to claim 2, wherein the edge data determining block includes a first multiplier, a second phase accumulator, and an edge data memory;
the comparator is specifically used for inputting the comparison result to the first end of the first multiplier, the comparator controls the output of the jitter pulse width coefficient determining module to alternately switch between the first jitter pulse width coefficient and the second jitter pulse width coefficient each time when the input of the first end of the comparator is greater than the input of the second end of the comparator, and controls the second end input of the first multiplier to alternately switch between FTW3/FTW1 and FTW2/FTW1, and the frequency control word controlling the second phase accumulator is alternately switched between the frequency control word FTW3 and the frequency control word FTW2, the comparator controls the phase accumulation value of the first phase accumulator to decrease by a second pulse width parameter N when the input of the second end of the comparator is switched to a second dither pulse width coefficient, the first and second dither pulse width coefficients are the dither pulse width coefficients;
the first multiplier is used for performing multiplication operation on the input of the first end and the input of the second end of the first multiplier and outputting an operation result to the second phase accumulator;
the second phase accumulator is used for operating by taking the frequency control word FTW3 or FTW2 as the frequency control word and taking the operation result of the first multiplier as an initial phase, and outputting the phase to the edge data memory at each clock cycle;
and the edge data memory is used for determining the edge data of the pulse wave corresponding to the pulse address by taking the phase output by the second phase accumulator as the pulse address to obtain the digital pulse wave with jitter.
4. The pulse wave generating apparatus according to claim 3, wherein the dither pulse width coefficient determining module includes a pulse width modulation coefficient generating module, a register, and an adder;
the pulse width modulation coefficient generating module is used for generating a pulse width modulation coefficient R according to the jitter distribution mode and the random number coefficient R after receiving the jitter pulse configuration parameters, and outputting the pulse width modulation coefficient R to the first end of the adder; when the input of the first end of the comparator is larger than the input of the second end of the comparator each time, the comparator controls the pulse width modulation coefficient generation module to update the pulse width modulation coefficient r once;
the register comprises an output end which is connected with the second end of the adder, and is used for storing the first pulse width parameter P and the second pulse width parameter N and alternately switching the output of the output end of the register between the first pulse width parameter P and the second pulse width parameter N when the input of the first end of the comparator is greater than the input of the second end of the comparator each time;
and the adder is used for performing addition operation on the input of the first end and the input of the second end of the adder and outputting an operation result to the second end of the comparator.
5. The pulse wave generating apparatus according to claim 4, wherein the pulse width modulation coefficient generating module includes a random number generating module and a second multiplier;
the random number generation module is used for generating a random number according to the jitter distribution mode after receiving the jitter pulse configuration parameters and outputting the random number to the first end of the second multiplier; when the input of the first end of the comparator is greater than the input of the second end of the comparator each time, the comparator controls the random number generation module to regenerate a random number once;
the second multiplier comprises a first end and a second end, the random number coefficient R is input into the second end, and the second multiplier is used for multiplying the input of the first end and the input of the second end to obtain a pulse width modulation coefficient R and outputting the pulse width modulation coefficient R to the first end of the adder.
6. The pulse wave generation apparatus of claim 5, wherein the random number generation module generates a random number having a size between 0 and 1.
7. The pulse wave generator as claimed in claim 4 or 5, wherein the first dither pulse width factor is P + r and the second dither pulse width factor is N + r, where P is the first pulse width parameter, N is the second pulse width parameter, and r is the pulse width modulation factor.
8. The pulse wave generator of claim 7, wherein the second pulse width parameter N is less than or equal to one-half of an upper phase limit of the first phase accumulator.
9. The pulse wave generating apparatus according to claim 1, further comprising a digital-to-analog converter and an analog channel;
the digital-to-analog converter is used for receiving the digital pulse wave with jitter output by the edge data determining module and converting the digital pulse wave with jitter into an analog pulse wave with jitter;
and the analog channel is used for outputting the analog pulse wave with jitter obtained by the digital-to-analog converter.
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| CN110768647B (en) * | 2019-11-12 | 2023-05-09 | 中电科思仪科技股份有限公司 | Method and system for reducing pulse signal jitter based on edge control |
| CN111007765A (en) * | 2019-12-13 | 2020-04-14 | 贵州航天计量测试技术研究所 | Fast-edge pulse signal generating device with adjustable pulse parameters |
| CN113691241B (en) * | 2021-08-11 | 2022-03-15 | 电子科技大学 | High-precision digital jitter injection device based on amplitude conversion time sequence |
| CN114594825B (en) * | 2022-03-28 | 2024-04-12 | 深圳市爱普泰科电子有限公司 | System and method for generating jittered clock signal |
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