CN104090160A - High-precision frequency measuring device - Google Patents
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Abstract
Description
技术领域 technical field
本发明属于电测量技术领域，具体涉及一种高精度频率测量装置。 The invention belongs to the technical field of electrical measurement, and in particular relates to a high-precision frequency measurement device.
背景技术 Background technique
随着科学技术的飞速发展，频率计作为一种测量工具已经成为科研、实验、教学工作中不可缺少的工具。市售的数字频率计都是由专门的频率测量芯片组装而成，其精度高、功能强，但价格昂贵且操作复杂。 With the rapid development of science and technology, the frequency meter as a measurement tool has become an indispensable tool in scientific research, experiment and teaching. Commercially available digital frequency meters are all assembled by special frequency measurement chips, which have high precision and strong functions, but are expensive and complicated to operate.
用于频率测量的方法有很多，频率测量的准确度主要取决于所测量的频率范围和被测对象的特点。测量的精度不仅仅取决于作为标准器使用的频率源的精度，也取决于所用的测量设备和测量方法。目前常用的频率测量方法有：直接测频法、多周期同步测频法、模拟内插法、时间-幅度转换法和游标法等。 There are many methods for frequency measurement, and the accuracy of frequency measurement mainly depends on the measured frequency range and the characteristics of the measured object. The accuracy of measurement depends not only on the accuracy of the frequency source used as a standard, but also on the measurement equipment and measurement methods used. At present, the commonly used frequency measurement methods are: direct frequency measurement method, multi-cycle synchronous frequency measurement method, analog interpolation method, time-amplitude conversion method and vernier method.
目前，基于群相位的频率测量方法是测量方法的研究热点，其是建立在被测信号fx与频标信号f0存在一定关系即频率关系固定且存在一定频差的基础之上的，这种情况下，相位量子的变化规律具有一定的线性特征，运用群相位关系实现频率的高分辨率测量。 At present, the frequency measurement method based on the group phase is a research focus of the measurement method, which is based on the fact that there is a certain relationship between the measured signal fx and the frequency standard signal f0, that is, the frequency relationship is fixed and there is a certain frequency difference. Under the condition, the change law of phase quantum has a certain linear characteristic, and the high-resolution measurement of frequency can be realized by using the group phase relationship.
申请人向国家知识产权局提交的申请号为CN201110279368的发明专利申请提出一种基于频率与相位关系辅助处理的频率和相位差精密测量方法，铯钟输出的10MHz频标先经过整形电路和可调脉冲产生电路生成脉冲信号，再由DDS自动合成频率f0，f0的值取决于经过单片机粗测过的fx，使得fx与f0的群周期的整数倍等于测量闸门的时间值，并且fx与f0的群相位量子的值等于群相位重合检测电路的分辨率，然后将f0，fx送入异频相位重合检测电路产生实际测量闸门，控制计数器工作，MCU根据计数结果计算出fx的值，最终由LCD显示输出。 The application number CN201110279368 submitted by the applicant to the State Intellectual Property Office proposes a precision measurement method for frequency and phase difference based on auxiliary processing of the relationship between frequency and phase. The pulse generation circuit generates a pulse signal, and then the frequency f0 is automatically synthesized by the DDS. The value of f0 depends on the fx roughly measured by the single-chip microcomputer, so that the integer multiple of the group period of fx and f0 is equal to the time value of the measurement gate, and the value of fx and f0 The value of the group phase quantum is equal to the resolution of the group phase coincidence detection circuit, and then f0 and fx are sent to the different frequency phase coincidence detection circuit to generate the actual measurement gate to control the operation of the counter. The MCU calculates the value of fx according to the counting result, and finally the LCD Show output.
然而，上述方案使用了多个计数器和两个闸门，并利用了多周期同步测频法进行测量，其测量精度受到计数器和闸门控制精度的制约。而且，在测量初始阶段，由于被测信号本身的原因产生振荡或自激。 However, the above-mentioned solution uses multiple counters and two gates, and uses the multi-period synchronous frequency measurement method for measurement, and its measurement accuracy is restricted by the control accuracy of the counters and gates. Moreover, in the initial stage of measurement, oscillation or self-excitation occurs due to the measured signal itself.
发明内容 Contents of the invention
为了克服现有技术的不足，同时仍然确保频率测量的高精度和高稳定度效果，本发明提出了一种高精度频率测量装置。 In order to overcome the deficiencies of the prior art while still ensuring the effect of high precision and high stability of frequency measurement, the present invention proposes a high precision frequency measurement device.
为了达到上述目的，采用如下的技术方案：一种高精度频率测量装置，包括铯钟标准频率发生器、第一整形电路、第二整形电路、倍频电路、相控跟随电路、高频基准频率发生器、闸门信号产生器、第一数字频率乘法器、第二数字频率乘法器、第一DDS、第二DDS、第三DDS和MCU，其中，所述铯钟标准频率发生器产生的标准频率输入到第一整形电路，第一整形电路的输出端分别连接到倍频电路和相控跟随电路，倍频电路的输出端分别连接高频基准频率发生器的输入端和第一数字频率乘法器的输入端，被测频率端经第二整形电路的输出以及相控跟随电路的输出输入到第一数字频率乘法器，第一数字频率乘法器的输出端连接闸门信号产生器，闸门信号产生器的输出端与被测频率端的输出端口共同连接到第一DDS的输入端，被测频率端经过第二整形电路连接到第二数字频率乘法器的一个输入端以及相控跟随电路，第二数字频率乘法器的另外两个输入端分别连接第一DDS的输出端和高频基准频率发生器的输出端，第二数字频率乘法器具有两个输出端，其中一个连接第二DDS的输入端，另一个连接第三DDS的输入端，第二DDS的输出端以及第三DDS的输出端连接MCU，MCU输出被测频率的测量结果。 In order to achieve the above purpose, the following technical solution is adopted: a high-precision frequency measurement device, including a cesium clock standard frequency generator, a first shaping circuit, a second shaping circuit, a frequency multiplier circuit, a phase control follower circuit, and a high-frequency reference frequency Generator, gate signal generator, first digital frequency multiplier, second digital frequency multiplier, first DDS, second DDS, third DDS and MCU, wherein, the standard frequency that described cesium clock standard frequency generator produces Input to the first shaping circuit, the output ends of the first shaping circuit are respectively connected to the frequency multiplication circuit and the phase control follower circuit, and the output ends of the frequency multiplication circuit are respectively connected to the input end of the high-frequency reference frequency generator and the first digital frequency multiplier The input terminal of the measured frequency terminal is input to the first digital frequency multiplier through the output of the second shaping circuit and the output of the phase control follower circuit, and the output terminal of the first digital frequency multiplier is connected to the gate signal generator, and the gate signal generator The output terminal of the measured frequency terminal is connected to the input terminal of the first DDS together with the output port of the measured frequency terminal, and the measured frequency terminal is connected to an input terminal of the second digital frequency multiplier and a phase control follower circuit through the second shaping circuit, and the second digital The other two input terminals of the frequency multiplier are respectively connected to the output terminal of the first DDS and the output terminal of the high-frequency reference frequency generator, and the second digital frequency multiplier has two output terminals, one of which is connected to the input terminal of the second DDS, The other is connected to the input terminal of the third DDS, the output terminal of the second DDS and the output terminal of the third DDS are connected to the MCU, and the MCU outputs the measurement result of the measured frequency.
进一步地，所述第一整形电路和第二整形电路分别包括放大器和滤波器。 Further, the first shaping circuit and the second shaping circuit include amplifiers and filters respectively.
进一步地，所述第二整形电路还包括数字化整形单元。 Further, the second shaping circuit further includes a digital shaping unit.
进一步地，所述数字化整形单元为IIR滤波器。 Further, the digital shaping unit is an IIR filter.
进一步地，所述倍频电路还可以是占空比可调整的分频电路。 Further, the frequency multiplication circuit may also be a frequency division circuit with an adjustable duty cycle.
本发明的有益效果如下： The beneficial effects of the present invention are as follows:
（1）采用多个DDS进行频率数字化处理，能够提高频率信号的稳定性，减少了模拟频率的测量。 (1) Multiple DDSs are used for frequency digital processing, which can improve the stability of frequency signals and reduce the measurement of analog frequencies.
（2）采用相控跟随器和数字频率乘法器共同作为反馈环节的核心，能够对被测频率产生数字化的反馈。 (2) The phase control follower and digital frequency multiplier are used as the core of the feedback link, which can generate digital feedback to the measured frequency.
（3）减少了闸门电路和计数器电路，使频率测量更容易从数字域的角度实现高精度、高稳定度的测量。 (3) The gate circuit and counter circuit are reduced, making frequency measurement easier to achieve high-precision and high-stability measurement from the perspective of the digital domain.
（4）倍频电路或分频电路、多个数字频率乘法器的使用使得测量精度、测量速度是可控的和可调的，从而在不需要最高精度运行的情况下可以使用，使得本发明的装置具有广泛的测量场景，适用性强。 (4) The use of frequency multiplication circuit or frequency division circuit and multiple digital frequency multipliers makes the measurement accuracy and measurement speed controllable and adjustable, so that it can be used when the highest precision operation is not required, making the present invention The device has a wide range of measurement scenarios and has strong applicability.
附图说明 Description of drawings
图1为本发明实施例的结构框图。 Fig. 1 is a structural block diagram of an embodiment of the present invention.
图2为本发明实施例的相控跟随电路的原理框图。 FIG. 2 is a functional block diagram of a phase control follower circuit according to an embodiment of the present invention.
具体实施方式 Detailed ways
实施例一 Embodiment one
如图1所示，一种高精度频率测量装置，包括铯钟标准频率发生器、第一整形电路、第二整形电路、倍频电路、相控跟随电路、高频基准频率发生器、闸门信号产生器、第一数字频率乘法器、第二数字频率乘法器、第一DDS、第二DDS、第三DDS和MCU，其中，所述铯钟标准频率发生器产生的标准频率输入到第一整形电路，第一整形电路的输出端分别连接到倍频电路和相控跟随电路，所述倍频电路的输出端分别连接高频基准频率发生器的输入端和第一数字频率乘法器的输入端，被测频率端经第二整形电路的输出以及相控跟随电路的输出被输入到第一数字频率乘法器，第一数字频率乘法器的输出端连接闸门信号产生器，闸门信号产生器的输出端与被测频率端的输出端共同连接到第一DDS的输入端，被测频率端经过第二整形电路连接到第二数字频率乘法器的一个输入端以及相控跟随电路，第二数字频率乘法器的另外两个输入端分别连接第一DDS的输出端和高频基准频率发生器的输出端，第二数字频率乘法器具有两个输出端，其中一个连接第二DDS的输入端，另一个连接第三DDS的输入端，第二DDS的输出端以及第三DDS的输出端连接MCU，MCU输出被测频率的测量结果。 As shown in Figure 1, a high-precision frequency measurement device includes a cesium clock standard frequency generator, a first shaping circuit, a second shaping circuit, a frequency multiplier circuit, a phase control follower circuit, a high-frequency reference frequency generator, and a gate signal generator, the first digital frequency multiplier, the second digital frequency multiplier, the first DDS, the second DDS, the third DDS and MCU, wherein the standard frequency generated by the cesium clock standard frequency generator is input to the first shaping circuit, the output terminals of the first shaping circuit are respectively connected to the frequency multiplication circuit and the phase control follower circuit, and the output terminals of the frequency multiplication circuit are respectively connected to the input terminals of the high-frequency reference frequency generator and the input terminals of the first digital frequency multiplier , the measured frequency end is input to the first digital frequency multiplier through the output of the second shaping circuit and the output of the phase control follower circuit, the output end of the first digital frequency multiplier is connected to the gate signal generator, and the output of the gate signal generator The terminal and the output terminal of the measured frequency terminal are commonly connected to the input terminal of the first DDS, and the measured frequency terminal is connected to an input terminal of the second digital frequency multiplier and a phase control follower circuit through the second shaping circuit, and the second digital frequency multiplier The other two input terminals of the device are respectively connected to the output terminal of the first DDS and the output terminal of the high-frequency reference frequency generator, and the second digital frequency multiplier has two output terminals, one of which is connected to the input terminal of the second DDS, and the other The input terminal of the third DDS is connected, the output terminal of the second DDS and the output terminal of the third DDS are connected to the MCU, and the MCU outputs the measurement result of the measured frequency.
所述第一整形电路包括放大器，所述第二整形电路包括模拟信号滤波器和IIR滤波器。本高精度频率测量装置增加了信号反馈部分，其包括相控跟随电路、第一数字频率乘法器、闸门信号产生器、第一DDS和第二整形电路。 The first shaping circuit includes an amplifier, and the second shaping circuit includes an analog signal filter and an IIR filter. The high-precision frequency measurement device adds a signal feedback part, which includes a phase control follower circuit, a first digital frequency multiplier, a gate signal generator, a first DDS and a second shaping circuit.
本发明的原理如下： Principle of the present invention is as follows:
铯钟标准频率发生器产生10MHz的标准频率f0，经过放大器后得到的幅度的放大。假定放大倍数为A，则放大后的输出频率信号的幅度为A|f0|，其中|f0|表示标准频率f0的幅值。该幅度为A|f0|的频率信号被分成两路，一路输入到相控跟随电路，另一路经过倍频电路变为例如20MHz的频率信号，该20MHz的频率信号传输到高频基准频率发生器和第一数字频率乘法器两个单元。 The cesium clock standard frequency generator generates a standard frequency f0 of 10MHz, which is amplified after passing through the amplifier. Assuming that the amplification factor is A, the amplitude of the amplified output frequency signal is A|f0|, where |f0| represents the amplitude of the standard frequency f0. The frequency signal with an amplitude of A|f0| is divided into two paths, one path is input to the phase control follower circuit, and the other path passes through the frequency multiplication circuit to become, for example, a 20MHz frequency signal, and the 20MHz frequency signal is transmitted to the high frequency reference frequency generator and the first digital frequency multiplier two units.
高频基准频率发生器产生1GHz的高频频率，该频率发生器采用外部高精度的20MHz频率进行频率校准。这种高频频率能够提高在第二数字频率乘法器进行频率相乘时的频率精度，下面将会更详细地说明其精度原理。 The high-frequency reference frequency generator produces a high-frequency frequency of 1GHz, and the frequency generator uses an external high-precision 20MHz frequency for frequency calibration. Such a high frequency can improve the frequency accuracy when the second digital frequency multiplier performs frequency multiplication, and the principle of the accuracy will be described in more detail below.
被测频率经由被测频率端（一般为频率探头）输入到第一DDS和第二整形电路中。这种将信号分为一路经过信号整形以后再使用而另一路不经过整形就直接使用的方式，能够最大限度地保留被测信号的成分，使得第二数字频率乘法器能够尽可能地得到更丰富的频率资源。 The measured frequency is input into the first DDS and the second shaping circuit through the measured frequency terminal (usually a frequency probe). This method of dividing the signal into one channel for use after signal shaping and the other channel for direct use without shaping can preserve the components of the signal under test to the greatest extent, so that the second digital frequency multiplier can be enriched as much as possible. frequency resources.
其中，经过模拟滤波器输出的被测频率信号滤除了超高频带、超低频带等频带的频率。经过模拟滤波器滤波后的信号分别输出到相控跟随电路和第一数字频率乘法器。 Wherein, the measured frequency signal outputted through the analog filter filters out frequencies in frequency bands such as ultra-high frequency bands and ultra-low frequency bands. The signals filtered by the analog filter are respectively output to the phase control follower circuit and the first digital frequency multiplier.
该相控跟随电路主要是由CD4046集成锁相环构成的PLL锁相环电路，包括鉴相器PD、压控振荡器VCO和外接R、C构成的无源低通滤波器LPF，如图2所示。锁相环电路的基本工作原理是通过比较输入信号和压控振荡器输出信号之间的相位差，调节VCO输出频率来达到输入、输出信号同相位的目的。 The phase-controlled follower circuit is mainly a PLL phase-locked loop circuit composed of a CD4046 integrated phase-locked loop, including a phase detector PD, a voltage-controlled oscillator VCO and a passive low-pass filter LPF composed of external R and C, as shown in Figure 2 shown. The basic working principle of the phase-locked loop circuit is to adjust the VCO output frequency to achieve the same phase of the input and output signals by comparing the phase difference between the input signal and the output signal of the voltage-controlled oscillator.
u0为实际负载电压相位信号，u0经采样整形电路产生延时d1，得到方波信号u1。u1经RC调整延时产生延时补偿d2，得到负载电压相位方波信号u，在传统锁相环相位跟踪电路中u和u’为同一信号，作为鉴相器PD的一路输入。 u0 is the actual load voltage phase signal, and u0 generates a delay d1 through the sampling shaping circuit to obtain a square wave signal u1. U1 is adjusted by RC to generate delay compensation d2, and the load voltage phase square wave signal u is obtained. In the traditional phase-locked loop phase tracking circuit, u and u' are the same signal, which is used as an input of the phase detector PD. the
i0为开关器件开关换流相位信号，可由VCO输出的开关器件开关驱动信号i1代替，d0是开关器件开关换流时间，也就是i1和i0之间的实际延时差值。i1经过RC调整延时产生延时补偿d3，得到开关器件开关换流电流相位方波信号i，作为鉴相器PD的另一路输入。 i0 is the switching commutation phase signal of the switching device, which can be replaced by the switching device switching drive signal i1 output by the VCO, and d0 is the switching commutation time of the switching device, that is, the actual delay difference between i1 and i0. After i1 is adjusted by RC to generate delay compensation d3, a square wave signal i of the switching commutation current phase of the switching device is obtained, which is used as another input of the phase detector PD. the
由于PLL锁相环电路的锁相作用，使得u(或u’)和i两个方波信号保持同相位，相位差为零。d4则为u0的过零点与i0的过零点之间的时间间隔，即u0和i0之间的相位差，显然d4＝(d3-d2)-d1-d0。 Due to the phase-locking effect of the PLL phase-locked loop circuit, the two square wave signals u (or u') and i maintain the same phase, and the phase difference is zero. d4 is the time interval between the zero-crossing point of u0 and the zero-crossing point of i0, that is, the phase difference between u0 and i0, obviously d4=(d3-d2)-d1-d0. the
对于人为调整好的R1、R2，则电源工作时d2、d3是固定不变的，因此d4的大小由d0和d1决定。若d4＝0，负载工作在准谐振状态，开关器件可实现零电流关断(ZCS)和最低电压下开通；若d4＜0，负载工作在感性状态(i0的过零点落后于u0的过零点)，此时流出相开关器件是硬关断的，且由于回路存在引线电感，使开关器件关断时产生一个尖峰电压；若d4＞0，负载工作在容性状态(i0的过零点超前于u0的过零点)，此时流入相开关器件导通时电压较高，有导通冲击电流，同时与流出相开关器件串联的二极管换流后会承受反压，反压越大，反向恢复电流越大，二极管功耗也越大。 As for the artificially adjusted R1 and R2, d2 and d3 are fixed when the power supply is working, so the size of d4 is determined by d0 and d1. If d4=0, the load works in a quasi-resonant state, and the switching device can realize zero-current shutdown (ZCS) and turn-on at the lowest voltage; if d4<0, the load works in an inductive state (the zero-crossing point of i0 lags behind the zero-crossing point of u0 ), at this moment, the outgoing phase switching device is hard-off, and due to the lead inductance in the loop, a peak voltage is generated when the switching device is turned off; if d4>0, the load works in a capacitive state (the zero-crossing point of i0 is ahead of The zero crossing point of u0), at this time, the voltage of the inflow switching device is relatively high when it is turned on, and there is a conduction surge current. The greater the current, the greater the power dissipation in the diode.
同时，被测频率经过IIR滤波器后输出到第一数字频率乘法器，与倍频电路的输出进行相乘，产生经过铯钟标准频率发生器输出的标准信号校准的频率信号。至此，如果被测频率端得到的待测频率信号有一定的波动，或者刚开始测量时产生不稳定情况，则该不稳定的频率信号将被相控跟随电路和第一数字频率乘法器进行混合，并反馈回闸门信号产生器的输入端，通过闸门信号的控制，输入到第一DDS进行数字化，从而提高了频率信号的稳定性，尽可能地消除了自激、振荡等情况对于频率测量的干扰。 At the same time, the measured frequency is output to the first digital frequency multiplier after being passed through the IIR filter, and multiplied with the output of the frequency multiplication circuit to generate a frequency signal calibrated by the standard signal output by the cesium clock standard frequency generator. So far, if the measured frequency signal obtained by the measured frequency terminal fluctuates to a certain extent, or the instability occurs at the beginning of the measurement, the unstable frequency signal will be mixed by the phase control follower circuit and the first digital frequency multiplier , and fed back to the input terminal of the gate signal generator, through the control of the gate signal, it is input to the first DDS for digitization, thereby improving the stability of the frequency signal and eliminating self-excitation, oscillation, etc. as much as possible for frequency measurement. interference.
闸门信号产生器采用数字化计数器，例如多位二进制输出串行计数器，常用的有CD4024、CD4040和CD4060等，它们都是由T型触发器组成的二进制计数器，不同之处在于其位数。多位二进制计数器在此主要用于定时。在预定的时刻输出第一数字频率乘法器的输出信号给第一DDS。 The gate signal generator adopts a digital counter, such as a multi-bit binary output serial counter, commonly used are CD4024, CD4040 and CD4060, etc., they are all binary counters composed of T-type flip-flops, the difference lies in the number of bits. Multi-bit binary counters are mainly used here for timing. Outputting the output signal of the first digital frequency multiplier to the first DDS at a predetermined moment.
第一DDS的输出信号与前述1GHz的信号，以及经过IIR滤波器滤波的数字化的被测频率共同被输入到第二数字频率乘法器。由于1GHz这种高频信号的作用，使得在进行乘法运算的过程中，被测量的频率信号的低频和高频均被尽可能地放大。第二DDS和第三DDS分别用于处理低频信号和高频信号，当信号输出到第二DDS和第三DDS时，将被分为低频DDS和高频DDS适用的两部分信号，分别进行处理时，有利于提高最终测量结果的精确度。 The output signal of the first DDS, the aforementioned 1 GHz signal, and the digitized measured frequency filtered by the IIR filter are jointly input to the second digital frequency multiplier. Due to the effect of the 1GHz high-frequency signal, the low frequency and high frequency of the measured frequency signal are amplified as much as possible during the multiplication operation. The second DDS and the third DDS are used to process low-frequency signals and high-frequency signals respectively. When the signals are output to the second DDS and the third DDS, they will be divided into two parts suitable for low-frequency DDS and high-frequency DDS, and processed separately It is beneficial to improve the accuracy of the final measurement results.
第二DDS和第三DDS的输出信号均被输入到MCU的两个输入引脚，其中例如采用PIC16F690-I/S0单片机作为MCU。处理过程中，对两个输入引脚的信号分别进行计数，并在计数后相加。最终相加的结果即为被测量的频率。 Both the output signals of the second DDS and the third DDS are input to two input pins of the MCU, wherein, for example, a PIC16F690-I/S0 microcontroller is used as the MCU. During processing, the signals at the two input pins are counted separately and added after counting. The result of the final addition is the measured frequency.
表1 信号频率测量实验结果 Table 1 Signal frequency measurement experiment results
上述数据表明，改进后的系统不论被测信号与频标信号的关系是简单还是比较复杂，测量稳定度均能达10-12量级，实际测量精度可达到10-13/s量级，实现了对任意频率信号的等精度测量。 The above data show that, regardless of whether the relationship between the measured signal and the frequency standard signal is simple or complex, the measurement stability of the improved system can reach the order of 10 -12 , and the actual measurement accuracy can reach the order of 10 -13 /s, realizing It provides equal precision measurement for any frequency signal.
实施例二 Embodiment two
一种高精度频率测量装置，包括铯钟标准频率发生器、第一整形电路、第二整形电路、分频电路、相控跟随电路、高频基准频率发生器、闸门信号产生器、第一数字频率乘法器、第二数字频率乘法器、第一DDS、第二DDS、第三DDS和MCU。所述分频电路是占空比可调整的，第二整形电路中的模拟滤波器滤除的是高频信号和超高频信号。 A high-precision frequency measurement device, including a cesium clock standard frequency generator, a first shaping circuit, a second shaping circuit, a frequency division circuit, a phase control follower circuit, a high-frequency reference frequency generator, a gate signal generator, a first digital A frequency multiplier, a second digital frequency multiplier, a first DDS, a second DDS, a third DDS and an MCU. The frequency dividing circuit is adjustable in duty ratio, and the analog filter in the second shaping circuit filters out high frequency signals and ultra high frequency signals.
其他电路的连接方式、发明的测量原理与实施例一相同。 The connection mode of other circuits and the measurement principle of the invention are the same as those in the first embodiment.
在利用上述第一和第二数字频率乘法器时，可以通过在其中设置预设值作为乘法运算的一个乘数并调节该预设值，达到对反馈和计算结果的可控性和可调节性。 When using the above-mentioned first and second digital frequency multipliers, the controllability and adjustability of feedback and calculation results can be achieved by setting a preset value in it as a multiplier of the multiplication operation and adjusting the preset value .
上面以文字和附图说明的方式阐释了本发明一些具体实施方式的结构，并非详尽无遗或限制于上述所述具体形式。应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。 The structures of some specific embodiments of the present invention have been explained above in the form of text and drawings, but are not exhaustive or limited to the above-mentioned specific forms. It should be pointed out that those skilled in the art can make some improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention.
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