CN2213342Y

CN2213342Y - Digital frequency indicator for doubling circuit made of phase locked loop

Info

Publication number: CN2213342Y
Application number: CN 94217782
Authority: CN
Inventors: 杨东明
Original assignee: Individual
Current assignee: Individual
Priority date: 1994-03-31
Filing date: 1994-08-03
Publication date: 1995-11-22
Anticipated expiration: 2004-08-03

Abstract

The utility model relates to a digital frequency indicator for a doubling circuit formed from a phase locked loop, and comprises a pulse sampling circuit, a shaping circuit, a frequency multiplier circuit, a time control and counting circuit, a latching circuit, a decoding circuit, a display circuit and a power supply circuit, wherein, the frequency multiplier circuit is composed of a phase locked loop integrated circuit and an N-scale counter circuit. When the phase locked loop is locked, frequency multiplication output signals which are N times of the measured pulse signals are obtained at the clock input end of the counter circuit; thus the measuring precision of the frequency indicator is enhanced by N times relatively. The utility model is composed of a general-purpose digital integrated circuit which is simple in structure, low in cost, convenient and easy in manufacture and use and easy to extend other functions.

Description

Digital frequency indicator for doubling circuit made of phase locked loop

The utility model relates to a kind of electronic gauge apparatus, exactly, relates to a kind of digital frequency meter that constitutes frequency multiplier circuit with phaselocked loop.

In electric system, it is more frequent that present Applied Digital power frequency table is monitored the 50HZ alternating current, also very convenient.But this instrument is to utilize the principle of single chip microcomputer to make, and after analog to digital conversion in the machine, can be accurate to one of percentage hertz demonstration reading value.This instrument is worked out loading routine with specific purpose tool again because of using single-chip microcomputer and ROM chip, so cost is more expensive, to user's technical requirement height, maintenance difficulty is also big.

The digital integrated device of a kind of usefulness that provides of the purpose of this utility model is parts, constitutes the digital frequency meter of frequency multiplier circuit with phaselocked loop, and this instrument measurement accuracy height, cost are low, and be not high to user's technical requirement.

The utility model by casing and by pulse sampling, shaping, frequency multiplication, time control and count, latch, decipher, control circuits such as demonstration and power supply are formed, it is characterized in that: wherein frequency multiplier circuit advances counter circuit by phase-locked loop intergrated circuit and N and is formed, counter is inserted between the VCO output and comparer in the phase-locked loop circuit chip, when pll lock, can obtain N frequency multiplication output signal at the input end of clock of counter circuit to the measured pulse signal; Wherein the measured signal shaping circuit is made up of diode, two phase inverters and middle integrating circuit thereof; Wherein time control circuit then by crystal oscillator, amplification, two phase inverters and middle differentiating circuit thereof and diode, phase inverter with derivative time distributor circuit formed, therefrom draw " zero clearing " signal and " latching " signal respectively.Above-mentioned phase-locked loop circuit can be selected CMOS CD4046 chip for use.The product Nfi of the frequency of the frequency f i of measured signal and frequency multiplier circuit in the utility model (being that N advances counter) should be not more than the maximum operation frequency of phase-locked loop circuit chip.Integration circuit time constant parameter in the above-mentioned measured signal sampling shaping circuit should be looked the frequency of measured signal and be adjusted it.

Thereby the utility model is to utilize phaselocked loop and N to advance counter to form a kind of digital frequency meter that frequency multiplier circuit improves frequency measurement accuracy.When pll lock, the measured signal frequency f i of phaselocked loop input equates with this counter output signal frequency, this moment, the clock pulse input terminal (VCO output terminal) at counter can draw frequency multiplication output signal fo=Nfi, pass through time control circuit again, above-mentioned signal send into counting, latch, decoding, display circuit, make the shown measured signal of frequency meter expand as mnfiHZ(wherein n be that the N of frequency multiplier circuit advances counter, m is several a second of timing time), the precision of frequency measurement is also corresponding to have improved mn doubly thereby make.According to above-mentioned principle as can be known, this device can be according to the signal frequency that will measure, and the carry rate of choose reasonable counter improves the measurement accuracy of frequency and enlarges its measurement range.In addition, nearly all be to adopt digital integrated circuit to make at the utility model control circuit, circuit structure is simple, has the advantages that cost is lower, easy to manufacture, working service convenient and be easy to expand other functions.

Fig. 1 is a functional-block diagram of the present utility model.

Fig. 2 is an embodiment electrical schematic diagram of the present utility model.

As shown in Figure 1, the utility model by pulse sampling, shaping, frequency multiplication, time control and count, latch, decipher, control circuits such as demonstration and power supply form.Wherein frequency multiplier circuit advances counter circuit by phase-locked loop intergrated circuit and N and is formed (the with dashed lines frame goes out among the figure).

Referring to Fig. 2, this is that the utility model is used to test that 50HZ, time are controlled to be 1 second, the embodiment schematic diagram of 100 frequency multiplier circuits.Show among the figure, constitute 100 frequency multiplier circuits with phase-locked loop circuit CD4046 and counter circuit CD4518, counter circuit CD4518 is inserted between the voltage controlled oscillator VCO output and comparer of phase-locked loop circuit chip CD4046, when pll lock, can draw N frequency multiplication output signal (fo=100fi) at the input end of clock (1 pin) of CD4518 to measured pulse signal fi.After the measured pulse sample of signal, by diode D5, two phase inverter G1, G2 and middle integrating circuit R5, C3 filtering interfering thereof and signal is carried out shaping, the R5 here, C3 time constant parameter will be adjusted it according to the frequency of measured signal, so that its work is more effective.

Present embodiment uses the pulse per second (PPS) of quartzy clock as time reference signal, behind amplification, phase inverter G3 shaping and C4, R6 differentiating circuit, from very narrow time pulse of phase inverter G4 output, the distributor circuit of forming through C5, D1～D4, R7, R8 derivative time is again held respectively output latch and is put " O " pulse signal from phase inverter G5, G6.The counting of this embodiment, latch, decipher display circuit part and can select the CMOS-LED combinational circuit ZCL102 of domestic production for use, also can select for use CD4518 counting, CD4511 to latch driving, show with the LED of common cathode.Because of being conventional current techique, repeat no more herein.Accompanying drawing also only picture frame figure to show it.

It is to be noted: because the maximum operation frequency of phase-locked loop circuit CD4046 is 1.2MHZ, so, the product Nfi of the frequency f i of measured signal and the frequency of frequency multiplier circuit (being that N advances counter), should be not more than the maximum operation frequency of phase-locked loop circuit chip, otherwise the device cisco unity malfunction.The frequency of input pulse in the foregoing description (i.e. the measurement range of this frequency meter) is 1～200HZ, and frequency is 100.Can reduce the time constant of R1C1 if will enlarge the frequency range of measured signal, and will improve measuring accuracy, then can improve the overtones band of frequency multiplier circuit, as above-mentioned embodiment is 100 frequencys multiplication, measurement accuracy is 1/100HZ, is 10000 as frequency multiplication, and then measurement accuracy can reach 1/10000HZ.The signal amplitude of sample circuit will be between 3.5～5 volts.

In Fig. 2 embodiment, R1=R6=10K Ω, R3=R10=R11=1M Ω, R4=R5=100K Ω, R7=R8=1K Ω, R9=2K Ω.C1＝C5＝2200pF，C2＝2.2μF，C3＝C4＝330pF。D1～D5 2CP type, D6, D7 2AP type.The utility model has been tested enforcement, measures effect and has realized the goal of the invention requirement.

Claims

1, a kind of digital frequency meter that constitutes frequency multiplier circuit with phaselocked loop, by casing and by pulse sampling, shaping, frequency multiplication, time control and count, latch, decipher, control circuits such as demonstration and power supply are formed, it is characterized in that: wherein frequency multiplier circuit advances counter circuit by phase-locked loop intergrated circuit and N and is formed, counter is inserted between the VCO output and comparer in the phase-locked loop circuit chip, when pll lock, can obtain N frequency multiplication output signal at the input end of clock of counter circuit to the measured pulse signal; Wherein the measured signal shaping circuit is made up of diode, two phase inverters and middle integrating circuit thereof; Wherein time control circuit then by crystal oscillator, amplification, two phase inverters and middle differentiating circuit thereof and diode, phase inverter with derivative time distributor circuit formed, therefrom draw " zero clearing " signal and " latching " signal respectively.

2, digital frequency meter as claimed in claim 1 is characterized in that: above-mentioned phase-locked loop circuit can be selected CMOS CD4046 chip for use.

3, digital frequency meter as claimed in claim 1 or 2 is characterized in that: the product Nfi of the frequency f i of measured signal and the frequency of frequency multiplier circuit (being that N advances counter) should be not more than the maximum operation frequency of phase-locked loop circuit chip.

4, digital frequency meter as claimed in claim 1 is characterized in that: the integration circuit time constant parameter in the above-mentioned measured signal sampling shaping circuit should be looked the frequency of measured signal and be adjusted it.