CN201680883U

CN201680883U - Novel double-timing-method counter

Info

Publication number: CN201680883U
Application number: CN2010201882711U
Authority: CN
Inventors: 王伟; 刘丽; 沈昱明; 杨征兵
Original assignee: University of Shanghai for Science and Technology
Current assignee: University of Shanghai for Science and Technology
Priority date: 2010-05-10
Filing date: 2010-05-10
Publication date: 2010-12-22
Anticipated expiration: 2020-05-10

Abstract

The utility model relates to a novel double-timing-method counter. An input end of a CPLD programmable logic machine is connected with a key portion, a clock circuit and a shaping circuit, an output end of the CPLD programmable logic machine is connected with a communication buffer interface, a display drive and a communication interface, the communication buffer interface is connected with an MCU single chip microcomputer, the display drive is connected with a display portion and an indication lamp, and the communication interface is connected with an RS232 and RS485 interfaces. Based on the joint realization of CPLD and MCU matching with a relative function circuit, the counter provides more powerful functions on the basis of original double-timing-method pulse interpolation counters, not only can accurately measure pulse number with two decimals, but also can shorten calibration time and reduce calibration equipment volume under the premise of ensuring calibration accuracy, and realizes simplicity, reliable performance and low cost.

Description

Novel plesichronous method counter

Technical field

The utility model relates to a kind of counter, particularly a kind of novel plesichronous method counter.

Background technology

Counter is the main modular of acquisition stream value in the flow calibration equipment, current, volumetric method is adopted in the demarcation of flowmeter more, its principle is to calculate the fluid volume (being obtained by the umber of pulse conversion of gathering) that flows through tested flowmeter in the certain hour, and compare, thereby draw calibration result with the volume that records in the volumetric standard.Generally speaking, when having the flowmeter of pulse output with the flow standard device normalization, internal counter only calculates the fluid flow of complete pulse signal representative, and does not calculate the flow of incomplete square wave representative, thereby has caused error in dipping.Certainly, this error can be offset by collecting more umber of pulse usually, and the umber of pulse that common flowmeter unit volume is produced is limited, and this just means in some occasion, the volume of flow calibration equipment is had to make very hugely, and the nominal time is also longer relatively at interval.

Summary of the invention

The utility model is the problem that can't measure incomplete square wave at the counter in the existing flow calibration equipment, a kind of novel plesichronous method counter has been proposed, can record the pulse number that is accurate to 2 decimals, need not guarantee precision by gathering a large amount of umber of pulses, therefore can finish one time calibration process fast.

The technical solution of the utility model is: a kind of novel plesichronous method counter, comprise the CPLD programmable logic device, the button part, clock circuit, shaping circuit, the communication buffer interface, display driver, communication interface, the communication buffer interface, the MCU single-chip microcomputer, display driver, display part and pilot lamp, RS232 and RS485 interface, the input end of CPLD programmable logic device connects the button part, clock circuit, shaping circuit, output terminal connects the communication buffer interface, display driver, communication interface, the communication buffer interface connects the MCU single-chip microcomputer, display driver connects display part and pilot lamp, and communication interface connects RS232 and RS485 interface.

The input signal of described shaping circuit comes from from the input interface circuit signal selects circuit, photoelectric isolating circuit through thresholding successively, sends into shaping circuit at last.

The beneficial effects of the utility model are: the novel plesichronous method of the utility model counter, unite realization based on CPLD and MCU, cooperate the correlation function circuit, on original plesichronous method pulse interpolation formula counter basis, provide more strong functions, can not only accurately record pulse number with 2 decimals, and can shorten the nominal time under the prerequisite of stated accuracy, dwindle the calibration facility volume guaranteeing, realize that simple, dependable performance, cost are low.

Description of drawings

Fig. 1 is the utility model plesichronous method counter structure block diagram;

Fig. 2 is the utility model plesichronous method counter communication buffer interface circuit figure;

Fig. 3 is the utility model plesichronous method counter clock circuit diagram;

Fig. 4 is the utility model plesichronous method counter RS232 interface schema;

Fig. 5 is the utility model plesichronous method counter RS485 interface schema.

Embodiment

Novel as shown in Figure 1 plesichronous method counter structure block diagram, the input end of CPLD programmable logic device 1 connects button part 2, clock circuit 3, shaping circuit 7, output terminal connects communication buffer interface 8, display driver 10, communication interface 9, described communication buffer interface 8 (circuit diagram is shown in 2) connects MCU single-chip microcomputer 11, described display driver 10 connects display part and pilot lamp 12, and described communication interface 9 connects RS232 and RS485 interface 13.Input interface circuit 4 signals are selected circuit 5, photoelectric isolating circuit 6 through thresholding successively, send into shaping circuit 7 at last.

The utility model is a core with CPLD programmable logic device 1 and MCU single-chip microcomputer 11, has connected button part 2, clock circuit 3 and serial communication RS232 and RS485 interface circuit 13 around it successively.Wherein button part 2 comprises 4 buttons, is respectively: system reset, and T1/T2 switches, and n/n ' switches and 2 kinds of gates are selected.Clock circuit such as Fig. 3, for CPLD work provides stable sequential, the crystal oscillator degree of stability is ± 1ppm.RS232 and RS485 communication module such as Fig. 4,5, the information of its output can be confessed and decide detection.

To be measured and the gate-control signal of the compatible multiple level of novel plesichronous method counter; Support the gate-control signal of 2 kinds of modes; Timing length bring up to 99 minutes and 59 seconds 999 milliseconds 999 delicate; Timing signal is not measured the frequency of input pulse, and precision is 0.1hz.

Claims

1. novel plesichronous method counter, it is characterized in that, comprise the CPLD programmable logic device, the button part, clock circuit, shaping circuit, the communication buffer interface, display driver, communication interface, the communication buffer interface, the MCU single-chip microcomputer, display driver, display part and pilot lamp, RS232 and RS485 interface, the input end of CPLD programmable logic device connects the button part, clock circuit, shaping circuit, output terminal connects the communication buffer interface, display driver, communication interface, the communication buffer interface connects the MCU single-chip microcomputer, display driver connects display part and pilot lamp, and communication interface connects RS232 and RS485 interface.

2. according to the described novel plesichronous method counter of claim 1, it is characterized in that the input signal of described shaping circuit comes from from the input interface circuit signal selects circuit, photoelectric isolating circuit through thresholding successively, sends into shaping circuit at last.