CN200993665Y - Small digitalized prase-comparing measuring device - Google Patents

Abstract

The utility model discloses a small size digitalized phase comparison measurement device, which comprises a DDS frequency division processing module. A measured signal and a reference clock signal of the DDS frequency division processing module are connected to a phase offset collector; a signal of the phase offset collector is connected to a microprocessor; after the phase comparison in the microprocessor, the signal is inputted into an integrating circuit and an A/D module. The utility model adopts a LPC930 series singlechip with integrated A/D module and a digitalized phase comparison device built with DDS technology. The LPC930 series singlechip, which is configured with an 8-digit MCU, has a processing speed sixfold of the ordinary 80C51. In addition, the mature DDS frequency synthesis technology ensures excellent signal to noise ratio for the output signal. On the basis of satisfying the precision for phase comparison measurement, the utility model broadens the measurement scope for the frequency of measured signal and realizes the small-size and digitalization of the whole measuring device, thus meeting with the requirements on performance and price in actual measurement.

Description

Small-sized digitizing is than phase measurement mechanism

Technical field

The utility model belongs to the long-time quality that is used for various high precision frequency sources (atomic frequency standard, high stability crystal oscillator etc.) and assesses measurement, is specifically related to a kind of digitized than phase measurement mechanism.

Background technology

Traditional forms than circuitry phase and a mechanical record instrument by one than phase instrument, and it is not high to exist precision, operation, data recording inconvenience, problem such as bulky.

Summary of the invention

It is a kind of small-sized digitized than phase measurement mechanism that the purpose of this utility model is to provide, to address the above problem.

The technical solution of the utility model is: small-sized digitizing is than phase measurement mechanism, it comprises DDS frequency division processing module, measured signal and reference clock signal that DDS frequency division processing module is handled are connected to the phase differential collector, phase differential collector signal is connected to microprocessor, and microprocessor ratio back signal mutually is input to integrating circuit and A/D module.As shown in Figure 1.

With tested frequency source signal f ₁And reference frequency source signal f ₂Deliver to the DDS processing module respectively, by the DDS digital synthesis technology obtain the two-way frequency close the square wave fractional frequency signal, through microprocessor the phase differential of two paths of signals is gathered with the processing mode that the signal rising edge triggers then, microprocessor output simultaneously characterizes the digital square-wave of the change in duty cycle of two paths of signals phase differential, and become corresponding DC voltage after sending into integrating circuit, the A/D modular converter that the microprocessor chip integration becomes is gathered DC voltage, by the RS232 serial communication interface measurement data is passed to computing machine at last, after machine data is handled as calculated, give user side with measurement result and the real-time curve display of measuring.

Described phase differential collector, microprocessor and A/D module adopt integrated LPC930 series monolithic.

This device employing chip integration becomes to have the LPC930 series monolithic of A/D module, and the DDS technique construction digitizing of existing comparative maturity is than phase measurement mechanism.The LPC930 series monolithic is 8 MCU, and 6 times to common 80C51 single-chip microcomputer processing speed, and the synthetic treatment technology of the digitizing DDS frequency signal of comparative maturity makes output signal and input signal have good signal-to-noise at present.On the basis of satisfying than phase measuring accuracy, widened the frequency measurement scope of measured signal, and made entire measuring device be able to small-sized digitizing, on performance and price, satisfy the demand of actual measurement.

Description of drawings

The small-sized digitizing of Fig. 1 is than the schematic diagram of phase measurement mechanism

Fig. 2 DDS frequency division processing module synoptic diagram

Fig. 3 DDS1 module diagram

Fig. 4 DDS2 module diagram

Fig. 5 phase differential is gathered and integration A/D handles synoptic diagram

Fig. 6 processing procedure schematic diagram

Fig. 7 handling procedure process flow diagram

Fig. 8 test curve figure

Embodiment

As shown in Figure 2, DDS frequency division processing module:

Reference clock signal f ₂Behind isolated amplifier 1, be sent to away hour counter 1, walk 1 couple of f of hour counter ₂Carry out frequency counting, the count value of walking hour counter 1 by 1 pair of single-chip microcomputer enable latch is sampled and is latched, thereby obtains the frequency F2 of concrete reference clock signal.Tested frequency signal f ₁One tunnel external clock input end that is sent to DDS1 (as Fig. 3) wherein behind isolated amplifier 2 is as DDS1 work reference clock, the external data PORT COM of while DDS1 (sheet choosing), SCLK (write pulse), SDIO (data) are connected to single-chip microcomputer respectively, in order to accept from the control word order of single-chip microcomputer and the transmission of data.

The actual DDS chip internal of selecting for use has 2 48 bit frequency control registers (F0, F1), installs tested frequency signal f for this ₁, when not using the inner PLL double frequency function of DDS1, during 48 frequency control register F0 full packing 1, it is f that DDS1 has frequency ₁Clock signal output, but in actual applications, in order to widen than the measurement range of installing mutually to tested frequency signal, as getting 10MHz when the reference clock signal frequency, and the measured signal frequency is up to a hundred even during the hundreds of hertz, just need make frequency division earlier and handle, in the frequency that guarantees to reduce under the impregnable prerequisite of original signal frequency stability measured signal tested frequency signal.In this device, intend adopting to measured signal f ₁Make 1/100 frequency division and handle, by single-chip microcomputer concrete frequency division numerical value is sent to DDS1 and realizes the signal frequency split processing, the computing method of its numerical value frequency division value are as follows:

$D=\frac{2^{48}\×f}{f_1}---\left(1\right)$

Wherein, D is the concrete frequency division numerical value of required calculating, f ₁Be the measured signal frequency, f is needed concrete fractional frequency signal frequency, for f=(1/100) f ₁Situation, frequency division numerical value D should be 2 ⁴⁸* 10 ^-2Communication between single-chip microcomputer and the DDS1 adopts the sequential of serial communication to carry out:

When

During for high level, SCLK, SDIO pin are high-impedance state.When

During for low level, DDS1 will be in communication state, this moment is when importing a rising edge pulse when single-chip microcomputer to pin SCLK, to make a divider ratio Value Data that hangs on the data bus SDIO write the DDS1 data buffer with binary representation, after final scale-of-two frequency division rate score data write, the internal comparator by DDS1 was handled and will be obtained desired fractional frequency signal output.

The frequency signal f that will obtain after DDS1 module 1/100 frequency division is handled delivers to away hour counter 2, walk 2 couples of f of hour counter and carry out frequency counting, the count value of walking hour counter 2 by 2 pairs of single-chip microcomputer enable latch is sampled and is latched, single-chip microcomputer by to latch 2 enumeration datas read and take advantage of 100 to handle after just can obtain the frequency value F 1 of concrete measured signal.Through type (2), the frequency division parameter that is sent to DDS2 that the single-chip microcomputer decision is concrete:

$\mathrm{Data}=\frac{2^{48}\×(F2-\mathrm{\Δf})}{F1}---\left(2\right)$

In the formula, F1, F2 are by walking hour counter 2 and walking 1 couple of measured signal f of hour counter ₁And reference clock signal f ₂Carry out the concrete frequency values that sample count obtains, Δ f is a difference frequency numerical value that presets, and its size has determined finally to enter the measured signal f that phase place is gathered _xWith reference clock signal f ₀Between frequency-splitting.

Another road of measured signal behind isolated amplifier 2 is sent to the external clock input end of DDS2 (as shown in Figure 4), as DDS2 work reference clock, the external data PORT COM of DDS2 simultaneously (sheet choosing), SCLK (write pulse), SDIO (data) are connected to single-chip microcomputer respectively, in order to accept from the control word order of single-chip microcomputer and the transmission of data.

Through DDS2 to measured signal by after presetting frequency division numerical value Data frequency division and handling, obtain required f _xMeasured signal output after delivering to filtration module then and carrying out low-pass filtering treatment, is directly exported.

Phase differential is gathered and integration A/D handles:

We adopt the LPC930 series microprocessor to be used as the processing unit of core, and it is the microcontroller of a monolithic encapsulation, contains multiple packing forms cheaply.It has adopted high performance processor structure, and inner integrated many system-level functions can significantly reduce the number and the board area of element like this and reduce the cost of system.

Its key property is as follows:

When operating frequency was 18MHz, except that multiplication and divide instruction, be 111～222ns the instruction time of high speed 80C51CPU.Under the same clock frequency, its speed is 6 times of standard 80C51 device.Only need lower clock frequency can reach same performance, reduced power consumption so undoubtedly; Inner integrated 10 accuracy A/D converters; 2 16 bit timings/counters; Enhancement mode UART.Having Baud rate generator, detection at interval, frame error-detecting and automatic address detection can; User data EEPROM memory block in 512 chunks can be used to deposit measurement data or parameter etc. is set.

We adopt the clock signal that 16 bit timing devices are gathered as phase differential in the LPC930 series microprocessor sheet, 10 accuracy A/D are as registering instrument, the measurement data result is passed to Computer Processing by the RS232 serial line interface, data deposit hard disk in, will measure curve simultaneously and draw on display.

As shown in Figure 5: in phase differential was gathered link, measured signal fx and reference clock signal fo delivered to the pin P1.3 and the P1.4 end of single-chip microcomputer respectively, and the output of P1.6 pin is directly as than back integrating circuit level input end mutually.For making the single-chip microcomputer can normal and stable operation, one road external clock CLK signal be delivered to the single-chip microcomputer input end of clock simultaneously.The time adopted software to judge the collection of finishing phase differential in design, and reflected concrete phase difference value by pin P1.6 output duty cycle square wave, the principle of realization as shown in Figure 6, specific implementation process following (as shown in Figure 7):

One 16 bit timing device to single-chip microcomputer inside in the program is provided with minimum timing, the most-significant byte and the least-significant byte that are about to 16 bit timing devices all are arranged to 0xFF, when treating that the next CPU performance period arrives, will apply for that timer overflows interruption, in corresponding interrupt service routine, judge measured signal fx and reference clock signal fo rising edge arrival situation.For reference clock signal fo, when rising edge arrived, it was high level that phase differential output pin P1.6 is set, and at this moment the subsequent integration circuit will add up to integral voltage; For measured signal fx, when rising edge arrived, P1.6 will be changed to low level, and at this moment the integral voltage of integrating circuit will keep no change.In the timing cycle of 16 bit timing device minimums, promptly overflow in the interrupt service routine at a complete timer, as fx, when the fo rising edge arrives simultaneously, represent a complete end than phase cycle, put 0 with the integrator integral voltage this moment.

By last we know:

The timing of timer is the smaller the better, single-chip microcomputer for concrete employing, its corresponding external clock input CLK signal frequency and frequency stability are high more good more, the time that makes single-chip microcomputer carry out a machine cycle code so on the one hand shortens, on the other hand when the frequency stability of outside input clock signal when higher, the time of overflowing interrupt response for each timer is just relatively more accurate, thereby can improve the resolution that differs collection of measured signal fx and reference clock signal fo.

The relation that differs that reflects two paths of signals in the program by the duty cycle square wave of P1.6 pin output signal, when the phasic difference of two paths of signals phase is big, high level will be in the great majority in the P1.6 output square wave, corresponding integral voltage increase will be very fast when being connected to the incoming level end of integrating circuit, when the two paths of signals phase differential hour, low level will be in the great majority in the P1.6 output square wave, corresponding integral voltage increase will be slower when being connected to the incoming level end of integrating circuit, and when the phasic difference of two paths of signals phase is 0 in the timer minimum timing cycle, will cause integral voltage total in the integrating circuit to put 0, promptly finish a complete ratio phase cycle.

Deliver to the A/D sampling pin P0.0 of single-chip microcomputer inside through what integrating circuit obtained than phase integral voltage.It in the single-chip microcomputer sheet 10 accuracy A/D modular converter, can the numeric value represented scope be 0-1023, be that numerical value 0 and 1023 is being represented 0 ° and 360 ° of phase differential respectively, She Ji ratio phase instrument minimum resolution probably is about 360 °/1024=0.4 ° so, promptly can exist at the actual specific phase time ± about 0.4 ° measuring error.When actual measurement, usually the frequency of reference clock signal fo and measured signal fx is arranged to differ collection and the integral voltage processing that a certain less difference frequency Δ f carries out phase differential according to formula (2), single-chip microcomputer is by the integral voltage of inner integrated A/D acquired integrated circuit, and the result that will collect is sent to PC by inside integrated enhancement mode UART interface TX, RX with the RS232 serial communication mode, and other whole being brought in by PC than phase result treatment finished.With 10 accuracy A of the single-chip microcomputer/D sampling module of reality, sampling time T=10 second, test curve is illustrated in figure 8 as example, the PC end actual treatment whole than phase outcome procedure in, it is as follows to calculate " hour degree of stability ":

The PC end sends the integral voltage data of coming by receiving single-chip microcomputer, gets wherein the 1st, the 360th, the 720th ... (supposition A/D acquisition range is 0～V) to A/D sampled voltage numerical value, is translated into phase value  ₁,  ₂...  _i, concrete conversion formula is:

After formula (3) arrangement:

Wherein N is 360 ° of complete number of cycles that i is experienced in 3600 seconds, V ₁, V ₂Be respectively i-1 and i-2 pairing A/D sampled voltage of 3600 seconds moment, φ _iBe i total phase value that was experienced in 3600 seconds being asked, then i 3600 seconds difference frequency data Δ f _iBe calculated as:

Corresponding Δ f has been arranged _iValue then can will be calculated the correspondent frequency degree of stability in its substitution formula (6) Allan variance or formula (7) the Hadamard variance computing formula.

${\mathrm{\σ}}_y(2,\mathrm{\τ},\mathrm{\τ},f_h)=\sqrt{\frac{1}{2(N-1)}\underset{i=1}{\overset{N-1}{\mathrm{\Σ}}}{[f\left({\mathrm{\τ}}_{i+1}\right)-f\left({\mathrm{\τ}}_i\right)]}^2}---\left(6\right)$

$H{\mathrm{\σ}}_y(3,\mathrm{\τ})=\sqrt{\frac{1}{6(m-2)}\underset{k=1}{\overset{m-2}{\mathrm{\Σ}}}{(y_{k+2}-{2y}_{k+1}+y_k)}^2}---\left(7\right)$

τ is sampling time and sampling period in formula (6) and the formula (7), is 10 seconds in this example.N, m are for measuring number of times, f (τ _i) and y _kRepresent i or k difference frequency numerical value.It should be noted that: final frequency stability result by formula (6) or (7) calculate value measure divided by N or m time again in the mean value of difference frequency.

PC end is shown to the user with the frequency stability result who calculates, and also needs integral voltage data that single-chip microcomputer is sent simultaneously, shows whole real-time measurement curve than phase process by the time domain X-Y scheme.

Claims (2)

1, a kind of small-sized digitizing is than phase measurement mechanism, it comprises DDS frequency division processing module, it is characterized in that, measured signal and reference clock signal that DDS frequency division processing module is handled are connected to the phase differential collector, phase differential collector signal is connected to microprocessor, and microprocessor ratio back signal mutually is input to integrating circuit and A/D module.

2, small-sized according to claim 1 digitizing is characterized in that than phase measurement mechanism phase differential collector, microprocessor and A/D module adopt integrated LPC930 series monolithic.

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