CN102970093B - The synchro system of compatible multiple clock and synchronous method thereof - Google Patents
The synchro system of compatible multiple clock and synchronous method thereof Download PDFInfo
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- CN102970093B CN102970093B CN201210431943.0A CN201210431943A CN102970093B CN 102970093 B CN102970093 B CN 102970093B CN 201210431943 A CN201210431943 A CN 201210431943A CN 102970093 B CN102970093 B CN 102970093B
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Abstract
The invention discloses a kind of synchro system and synchronous method thereof of compatible multiple clock, this system comprises the unit such as external clock coupling amplifying unit, external clock coupling amplifying unit and the first multi-harmonic-oscillations 10MHz frequency-selecting unit, clock driver cell connects, one 10MHz band pass filter amplifying unit and the first multi-harmonic-oscillations 10MHz frequency-selecting unit, inside and outside reference clock selected cell connects, internal timebase signal generation unit is connected with the second multi-harmonic-oscillations 10MHz frequency-selecting unit, 2nd 10MHz band pass filter amplifying unit and the second multi-harmonic-oscillations 10MHz frequency-selecting unit, inside and outside reference clock selected cell connects, clock driver cell and control unit, inside and outside reference clock selected cell connects.The present invention can input by compatible 1MHz, 2MHz, 5MHz and 10MHz multiple clock, provides acquiescence 10MHz clock to export, exports, solve the problem that different clock frequencies cannot be synchronous according to optional 1MHz, 2MHz, 5MHz clock of outside input clock frequency.
Description
Technical field
The present invention relates to a kind of synchro system, particularly relate to a kind of synchro system and synchronous method thereof of compatible multiple clock.
Background technology
Along with the development of measuring technology, the situation that multiple measuring instrument uses together gets more and more, the situation utilizing various measuring instrument establishment test macro to carry out testing also gets more and more, in order to ensure precision and the accuracy of measurement, the measure error that elimination is asynchronous due to each measuring instrument clock and introduce, often needs the clock signal of measuring instrument used to carry out synchronously.But the standard clock frequency selected due to each apparatus manufacture is different, therefore its provide the clock signal of output to be also not quite similar, if any the 1MHz clock that provides export, the 5MHz clock that provides had exports, the 10MHz clock that provides had exports, and the clock input of instrument mostly is 10MHz, this will cause clock between each instrument cannot be synchronous, thus increases measure error.
Existing solution can be summarized as two kinds substantially, and the first scheme is frequency multiplication frequency-dividing clock synchronization scenario, and the first scheme passes through the method for frequency multiplication or frequency division, realizes the synchronous of interior external clock.Be specially when the standard time clock selected is lower than 10MHz, in order to provide the 10MHz output clock of standard, clock system is standing counts into frequency multiplier circuit, as depicted in figs. 1 and 2.When the standard time clock selected is 1MHz, need, through 10 multiplier unit, to produce the output clock of 10MHz.When the standard time clock selected is 5MHz, need, through 2 multiplier unit, to produce the output clock of 10MHz.Simultaneously in order to can with the clock synchronous of instrument outside, also to design corresponding frequency dividing circuit, produce the inner clock signal used.
First scheme is the scheme that when directly selecting 10MHz, base carries out clock synchronous, disregards cost exactly, directly selects 10MHz clock as the standard time clock of instrument internal, so just can directly provide 10MHz reference clock to export.
The shortcoming of the first scheme is as follows: poor compatibility, can only synchronous 10MHz clock, when external reference be 1MHz, 2MHz, 5MHz commonly use clock frequency time still cannot realize the problem of clock synchronous.
First scheme shortcoming is as follows: cost is high, and when instrument does not need will select 10MHz standard when using 10MHz clock yet, base is as the reference clock of inside, and during 10MHz standard the price of base than the price about 30% ~ 50% of base during 5MHz or 1MHz.Also there is the problem of the poor compatibility identical with the first scheme simultaneously, can only synchronous 10MHz clock, cannot the conventional clock of synchronous other frequencies.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of synchro system and synchronous method thereof of compatible multiple clock, it can input by compatible 1MHz, 2MHz, 5MHz and 10MHz multiple clock, acquiescence 10MHz clock is provided to export, export according to optional 1MHz, 2MHz, 5MHz clock of outside input clock frequency, solve the problem that different clock frequencies cannot be synchronous, thus ensure the precision of apparatus measures, eliminate and that introduce measure error asynchronous due to clock.
The present invention solves above-mentioned technical problem by following technical proposals: a kind of synchro system of compatible multiple clock, is characterized in that, it comprises external clock coupling amplifying unit, internal timebase signal generation unit, first multi-harmonic-oscillations 10MHz frequency-selecting unit, second multi-harmonic-oscillations 10MHz frequency-selecting unit, one 10MHz band pass filter amplifying unit, 2nd 10MHz band pass filter amplifying unit, inside and outside reference clock selected cell, clock driver cell and control unit, external clock coupling amplifying unit and the first multi-harmonic-oscillations 10MHz frequency-selecting unit, clock driver cell connects, a 10MHz band pass filter amplifying unit and the first multi-harmonic-oscillations 10MHz frequency-selecting unit, inside and outside reference clock selected cell connects, and internal timebase signal generation unit is connected with the second multi-harmonic-oscillations 10MHz frequency-selecting unit, the 2nd 10MHz band pass filter amplifying unit and the second multi-harmonic-oscillations 10MHz frequency-selecting unit, inside and outside reference clock selected cell connects, clock driver cell and control unit, inside and outside reference clock selected cell connects.
Preferably; the function of described external clock coupling amplifying unit by the frequency that instrument outside provides be mainly 1,2,5 or 10MHz clock signal carry out every straight, impedance matching; input saturation protective circuit carries out amplitude limit simultaneously, then enters the two-stage amplifying circuit be made up of triode and amplifies.
Preferably, described first multi-harmonic-oscillations 10MHz frequency-selecting unit with input after limited range enlargement 1,2,5 or 10MHz clock signal for trigger, through the 10MHz frequency-selective network be made up of lc circuit, 1,2,5 or 10MHz clock signal are all converted to 10MHz clock signal.
Preferably, a described 10MHz band pass filter amplifying unit is by the LC band-pass filter of the 10MHz external timing signal after the first multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting through being made up of inductance capacitance, then triode is utilized to carry out two-stage amplification, make 10MHz clock signal meet the requirement changed to Transistor-Transistor Logic level by sine, be supplied to inside and outside reference clock selected cell.
Preferably, base detecting unit, the first NAND gate, the second NAND gate, the 3rd NAND gate when described inside and outside reference clock selected cell comprises, time base detecting unit be connected with the first NAND gate, the second NAND gate, the 3rd NAND gate is connected with the first NAND gate, the second NAND gate.
The present invention also provides a kind of synchronous method of synchro system of compatible multiple clock, it is characterized in that, the synchronous method of the synchro system of described compatible multiple clock adopts the synchro system of above-mentioned compatible multiple clock, and the synchronous method of the synchro system of described compatible multiple clock comprises the following steps:
S1, external clock coupling amplifying unit by frequency be 1,2,5 or 10MHz clock signal carry out every straight, impedance matching, amplitude limit, amplification;
1,2,5 or 10MHz clock signal after external clock is mated amplifying unit process by S2, the first multi-harmonic-oscillations 10MHz frequency-selecting unit are all converted to 10MHz external timing signal;
10MHz external timing signal after first multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting is carried out filtering and amplification by S3, a 10MHz band pass filter amplifying unit, is supplied to inside and outside reference clock selected cell after filtering and amplification;
S4, internal timebase signal generation unit need to select 1MHz, 2MHz, 5MHz or 10MHz crystal oscillator accurate as the time disjunction mark of inside;
S5, the second multi-harmonic-oscillations 10MHz frequency-selecting unit all convert 1MHz, 2MHz, 5MHz or 10MHz clock signal of internal timebase signal generation unit to 10MHz internal clock signal;
10MHz internal clock signal after second multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting is carried out filtering and amplification by S6, the 2nd 10MHz band pass filter amplifying unit, is supplied to inside and outside reference clock selected cell after filtering and amplification;
S7, inside and outside reference clock selected cell are selected to select 10MHz external timing signal or 10MHz internal clock signal as required;
Clock signal after the selection of S8, inside and outside reference clock selected cell becomes multipath clock and exports after clock driver cell drives;
S9, be 1,2 or the 5MHz clock that 10MHz clock or outside provide for what be supplied to that the outside clock used selects to export by the control of control unit.
Positive progressive effect of the present invention is: one, the present invention can the clock input signal of compatible 1MHz, 2MHz, 5MHz and 10MHz tetra-kinds of different frequencies, the clock signal simultaneously provided is except 10MHz, can also according to outside input clock signal select output to be 1MHz, 2MHz or 5MHz clock, solve cannot be synchronous between different clock frequencies signal problem.That two, no matter internal timebase of the present invention is selected is 1MHz, 2MHz, 5MHz or 10MHz, and all can produce 10MHz clock signal by the synchro system of the compatible multiple clock of the present invention and synchronous method thereof, circuit is simple, cost is low, compatibility is good.
Accompanying drawing explanation
The theory diagram of the inside and outside clock system that Fig. 1 is existing internal clocking when being 1MHz.
The theory diagram of the inside and outside clock system that Fig. 2 is existing internal clocking when being 5MHz.
Fig. 3 is the theory diagram of the synchro system of the compatible multiple clock of the present invention.
Fig. 4 is the theory diagram of peripheral clock matches amplifying unit of the present invention.
Fig. 5 is the theory diagram of the first multi-harmonic-oscillations 10MHz frequency-selecting unit in the present invention.
Fig. 6 is the theory diagram of a 10MHz band pass filter amplifying unit in the present invention.
Fig. 7 is the theory diagram of inside and outside reference clock selected cell in the present invention.
Fig. 8 is the theory diagram of clock driver cell and control unit in the present invention.
Embodiment
Present pre-ferred embodiments is provided, to describe technical scheme of the present invention in detail below in conjunction with accompanying drawing.
As shown in Figure 3, the synchro system of the compatible multiple clock of the present invention comprises external clock coupling amplifying unit, internal timebase signal generation unit, first multi-harmonic-oscillations 10MHz frequency-selecting unit, second multi-harmonic-oscillations 10MHz frequency-selecting unit, one 10MHz band pass filter (Band-PassFilter, BPF) amplifying unit, 2nd 10MHz band pass filter amplifying unit, inside and outside reference clock selected cell, clock driver cell and control unit, external clock coupling amplifying unit and the first multi-harmonic-oscillations 10MHz frequency-selecting unit, clock driver cell connects, a 10MHz band pass filter amplifying unit and the first multi-harmonic-oscillations 10MHz frequency-selecting unit, inside and outside reference clock selected cell connects, and internal timebase signal generation unit is connected with the second multi-harmonic-oscillations 10MHz frequency-selecting unit, the 2nd 10MHz band pass filter amplifying unit and the second multi-harmonic-oscillations 10MHz frequency-selecting unit, inside and outside reference clock selected cell connects, clock driver cell and control unit, inside and outside reference clock selected cell connects.
The frequency that instrument outside mainly provides by the function of external clock coupling amplifying unit is 1, 2, 5 or 10MHz clock signal (clock signal is sinusoidal signal or the square-wave signal that amplitude is greater than 0.6Vp-p) as shown in Figure 4, external clock coupling amplifying unit comprises every straight unit, impedance matching unit, limiter protection circuit and amplifying circuit, every straight unit, impedance matching unit, limiter protection circuit is connected successively with amplifying circuit, specific works process is as follows: first carry out every directly, impedance matching, input saturation protective circuit carries out amplitude limit simultaneously, to prevent input signal amplitude excessive.Then enter the two-stage amplifying circuit be made up of triode to amplify, to meet the input request signal of the first multi-harmonic-oscillations 10MHz frequency-selecting unit.With incoming frequency 1MHz, the sinusoidal signal of amplitude 0.6Vp-p is example, after external clock coupling is amplified, become the sinusoidal signal that amplitude is 2.4Vp-p, and meeting the first multi-harmonic-oscillations 10MHz frequency-selecting unit high level minimum is the triggering requirement of 2V.
External clock is mated 1 after amplifying unit process by the first multi-harmonic-oscillations 10MHz frequency-selecting unit, 2, 5 or 10MHz clock signal all convert 10MHz external timing signal to, as shown in Figure 5, first multi-harmonic-oscillations 10MHz frequency-selecting unit comprises multi-harmonic-oscillations unit and frequency-selecting unit, multi-harmonic-oscillations unit is connected with frequency-selecting unit, specific works process is as follows: with input after limited range enlargement 1, 2, 5 or 10MHz clock signal for trigger, one-shot multivibrator (model is 74LS221) is selected to be designed to multi-harmonic-oscillations unit, the harmonic signal of the signal that multi-harmonic-oscillations unit exports to be pulse duration the be a series of external timing signal frequency of 50ns, through the 10MHz frequency-selective network be made up of lc circuit, by 1, 2, 5 or 10MHz clock signal be all converted to 10MHz clock signal.First multi-harmonic-oscillations 10MHz frequency-selecting unit can be made up of multivibrator.
As shown in Figure 6, a 10MHz band pass filter amplifying unit comprises LC band pass filter and triode.The function of the one 10MHz band pass filter amplifying unit is as follows: a 10MHz band pass filter amplifying unit is by the LC band-pass filter of the 10MHz external timing signal after the first multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting through being made up of inductance capacitance, then triode is utilized to carry out two-stage amplification, make 10MHz clock signal meet the requirement changed to Transistor-Transistor Logic level by sine, be supplied to inside and outside reference clock selected cell.
Internal timebase signal generation unit appliance requires can select 1MHz, 2MHz, 5MHz or 10MHz crystal oscillator accurate as the time disjunction mark of inside.Then the same with external timing signal, enter the second multi-harmonic-oscillations 10MHz frequency-selecting unit, second multi-harmonic-oscillations 10MHz frequency-selecting unit all converts 1MHz, 2MHz, 5MHz or 10MHz clock signal of internal timebase signal generation unit to 10MHz internal clock signal, again through enter the 2nd 10MHz band pass filter amplifying unit filtering and amplify after, be supplied to inside and outside reference clock selected cell.The Nei Shiji passage of internal timebase signal generation unit adopts the processing mode identical with external timing passage, utilize the multiplier unit that the second multi-harmonic-oscillations 10MHz frequency-selecting unit replaces in Fig. 1 and Fig. 2 implementation, advantage to utilize crystal oscillator that low price, frequency are lower as internal timebase reference, the internal timebase of different frequency, utilize circuit kit, just can realize 10MHz with reference to exporting, simple, compatible good, the highly versatile of circuit.The theory diagram of the second multi-harmonic-oscillations 10MHz frequency-selecting unit is the same with the theory diagram of the first multi-harmonic-oscillations 10MHz frequency-selecting unit shown in Fig. 5, and the theory diagram of the 2nd 10MHz band pass filter amplifying unit is the same with the theory diagram of the 10MHz band pass filter amplifying unit shown in Fig. 6.
Inside and outside reference clock selected cell is selected to select 10MHz external timing signal or 10MHz internal clock signal as required, the theory diagram of inside and outside reference clock selected cell as shown in Figure 7, base detecting unit when inside and outside reference clock selected cell comprises, first NAND gate U1-A, second NAND gate U1-B, 3rd NAND gate U1-C, time base detecting unit and the first NAND gate U1-A, second NAND gate U1-B connects, 3rd NAND gate U1-C and the first NAND gate U1-A, second NAND gate U1-B connects, first inside and outside reference clock selected cell converts sinusoidal signal to TTL signal, the external timing signal sended over by a 10MHz band pass filter amplifying unit becomes TTL signal and TTL signal is divided into two-way, one tunnel is as an input of the second NAND gate U1-B, base detecting unit when another road is given.Time base detecting unit utilize and the multivibrator (model is 74LS123) of repeated trigger can form automatic detection circuit, the width design of trigger impulse is 1.2 μ s, and external clock becomes the signal that pulse duration is 50ns after conversion.When there being external timing signal to input, the Q end of multivibrator exports as high level, and/Q end exports as low level; When not having external timing signal to input, Q holds output low level, and/Q end exports as high level.Time base detecting unit Q end output signal receive another input of the second NAND gate U1-B, control the output of NAND gate.Internal timebase signal becomes an input as 2 input the first NAND gate U1-A after Transistor-Transistor Logic level, another of the first NAND gate U1-A input from time base detecting unit /Q holds output.When there being external timing signal, time base detecting unit Q end export as high level ,/Q end exports as low level, and the output of NAND gate U1-A is high level, and internal clock signal is prohibited, and external timing signal is effective, can output to the 3rd NAND gate U1-C; Otherwise, time base detecting unit Q end export as low level ,/Q end exports as high level, the output of the second NAND gate U1-B is high level, and external timing signal is prohibited, and internal clock signal is effective, the 3rd NAND gate U1-C can be outputted to, thus realize the automatic switchover of inside and outside clock signal.
The major function of clock driver cell the clock signal (i.e. 10MHz signal) after inside and outside reference clock selected cell selection is become multipath clock after clock driver cell drives export, and is supplied to instrument internal respectively and uses and the use of instrument outside.NOR gate line drive (such as 74128 models) can as clock driver cell.As shown in Figure 8, clock driver cell can comprise the first NOR gate U2-A, the second NOR gate U2-B, the 3rd NOR gate U2-C.
10MHz clock for what be supplied to that the outside clock used can select to export by the control of control unit, or 1,2 or 5MHz clock that outside provides.As shown in Figure 8, control unit comprise first with door U3-A, second and door U3-B and four nor gate U2-D, first is all connected with four nor gate U2-D with door U3-B with door U3-A, second.First control signal CTRL1 and the second control signal CTRL2 is from central processing unit (CPU), when the first control signal CTRL1 is high level, when second control signal CTRL2 is low level, first is 10MHz with the output of door U3-A, second is low level with the output of door U3-B, therefore when the clock of four nor gate U2-D exports as 10MHz.When the first control signal CTRL1 is low level, when second control signal CTRL2 is high level, first is low level with the output of door U3-A, and second is outside 1MHz, 2MHz or 5MHz of input with the output of door U3-B, thus the clock of four nor gate U2-D to export be 1MHz, 2MHz or 5MHz.Thus achieve and provide acquiescence 10MHz clock to export, according to the function that optional 1MHz, 2MHz or 5MHz clock of outside input clock exports.
The synchronous method of the synchro system of the compatible multiple clock of the present invention comprises the following steps:
S1, external clock coupling amplifying unit by frequency be 1,2,5 or 10MHz clock signal carry out every straight, impedance matching, amplitude limit, amplification;
1,2,5 or 10MHz clock signal after external clock is mated amplifying unit process by S2, the first multi-harmonic-oscillations 10MHz frequency-selecting unit are all converted to 10MHz external timing signal;
10MHz external timing signal after first multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting is carried out filtering and amplification by S3, a 10MHz band pass filter amplifying unit, is supplied to inside and outside reference clock selected cell after filtering and amplification;
S4, internal timebase signal generation unit need to select 1MHz, 2MHz, 5MHz or 10MHz crystal oscillator accurate as the time disjunction mark of inside;
S5, the second multi-harmonic-oscillations 10MHz frequency-selecting unit all convert 1MHz, 2MHz, 5MHz or 10MHz clock signal of internal timebase signal generation unit to 10MHz internal clock signal;
10MHz internal clock signal after second multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting is carried out filtering and amplification by S6, the 2nd 10MHz band pass filter amplifying unit, is supplied to inside and outside reference clock selected cell after filtering and amplification;
S7, inside and outside reference clock selected cell are selected to select 10MHz external timing signal or 10MHz internal clock signal as required;
Clock signal after the selection of S8, inside and outside reference clock selected cell becomes multipath clock and exports after clock driver cell drives;
S9, be 1,2 or the 5MHz clock that 10MHz clock or outside provide for what be supplied to that the outside clock used selects to export by the control of control unit.
Operation principle of the present invention is as follows: when the clock signal of outside input is 1MHz, 2MHz, 5MHz or 10MHz, first after coupling is amplified, enter into the first multi-harmonic-oscillations 10MHz frequency-selecting unit, the harmonic signal of the output signal of the first multi-harmonic-oscillations 10MHz frequency-selecting unit to be pulse duration the be a series of external timing signal of 50ns.As external clock be 1MHz time, the output signal of the first multi-harmonic-oscillations 10MHz frequency-selecting unit is exactly be made up of the first-harmonic of 1MHz and each harmonic, and wherein 10 subharmonic are exactly 10MHz signal; When external clock is 2MHz, the output of the first multi-harmonic-oscillations 10MHz frequency-selecting unit is exactly be made up of the first-harmonic of 2MHz and each harmonic, and wherein 5 subharmonic are exactly 10MHz signal; When external clock is 5MHz, the output of the first multi-harmonic-oscillations 10MHz frequency-selecting unit is made up of the first-harmonic of 5MHz and each harmonic, and wherein 2 subharmonic are exactly 10MHz; When outside is input as 10MHz, the output of the first multi-harmonic-oscillations 10MHz frequency-selecting unit is exactly be made up of the first-harmonic of 10MHz and each harmonic, and wherein first-harmonic is exactly 10MHz; Like this through the frequency-selecting unit of 10MHz, 10MHz signal is just retained, and remaining harmonic signal is all attenuated, thus achieves 1MHz, 2MHz, 5MHz or 10MHz signal has all been transformed into 10MHz signal.Inside and outside reference clock selected cell is delivered to after the filter and amplification of a 10MHz band pass filter amplifying unit.Internal timebase signal generation unit need to select 1,2,5 or 10MHz crystal oscillator accurate as the time disjunction mark of inside, identical with the clock that outside inputs, after the second multi-harmonic-oscillations 10MHz frequency-selecting unit, also all become 10MHz signal, after the filter and amplification of the 2nd 10MHz band pass filter amplifying unit, deliver to inside and outside reference clock selected cell.As shown in Figure 7, when have external clock 10MHz signal (this 10MHz be through multi-harmonic-oscillations frequency-selecting amplify after 10MHz) time, time base detecting unit Q end export as high level 1, the output that/Q end exports as low level 0, U1-C is external clock; When there is no external clock, time base detecting unit Q end export as low level 0 ,/Q end exports as high level 1, and the output of the 3rd NAND gate U1-C is internal clocking.After interior External Reference is selected, be supplied to drive circuit, after driving, become multiple signals be supplied to instrument internal and outside use respectively.As shown in Figure 8, being supplied to the outside signal used, to control to realize output through the first control signal CTRL1 and the second control signal CTRL2 be 10MHz or 1,2 or 5MHz.When the first control signal CTRL1 is high level 1, when the second control signal CTRL2 is low level 0, the clock of four nor gate U2-D exports as 10MHz; When the first control signal CTRL1 is low level 0, to be high level 1 be the second control signal CTRL2, and it is 1,2 or 5MHz that the clock of four nor gate U2-D exports.Therefore the present invention can realize compatible 1,2,5 or the reference of 10MHz external clock, provides acquiescence 10MHz clock to export, according to clock optional 1,2 or the output of 5MHz clock of outside input.In sum, the present invention can the clock input signal of compatible 1MHz, 2MHz, 5MHz and 10MHz tetra-kinds of different frequencies, and the clock signal of output, except 10MHz, also can be selected to be 1MHz, 2MHz or 5MHz clock according to the clock of outside input.That no matter internal timebase is selected is 1MHz, 2MHz, 5MHz or 10MHz, and the synchro system of the compatible multiple clock of the present invention and synchronous method thereof all can be utilized to produce 10MHz clock signal.
Those skilled in the art can carry out various remodeling and change to the present invention.Therefore, present invention covers the various remodeling in the scope falling into appending claims and equivalent thereof and change.
Claims (6)
1. the synchro system of a compatible multiple clock, it is characterized in that, it comprises external clock coupling amplifying unit, internal timebase signal generation unit, first multi-harmonic-oscillations 10MHz frequency-selecting unit, second multi-harmonic-oscillations 10MHz frequency-selecting unit, one 10MHz band pass filter amplifying unit, 2nd 10MHz band pass filter amplifying unit, inside and outside reference clock selected cell, clock driver cell and control unit, external clock coupling amplifying unit and the first multi-harmonic-oscillations 10MHz frequency-selecting unit, clock driver cell connects, one 10MHz band pass filter amplifying unit and the first multi-harmonic-oscillations 10MHz frequency-selecting unit, inside and outside reference clock selected cell connects, internal timebase signal generation unit is connected with the second multi-harmonic-oscillations 10MHz frequency-selecting unit, 2nd 10MHz band pass filter amplifying unit and the second multi-harmonic-oscillations 10MHz frequency-selecting unit, inside and outside reference clock selected cell connects, clock driver cell and control unit, inside and outside reference clock selected cell connects,
External clock coupling amplifying unit by frequency be 1,2,5 or 10MHz clock signal carry out every straight, impedance matching, amplitude limit, amplification;
1,2,5 or 10MHz clock signal after external clock is mated amplifying unit process by the first multi-harmonic-oscillations 10MHz frequency-selecting unit are all converted to 10MHz external timing signal;
10MHz external timing signal after first multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting is carried out filtering and amplification by the one 10MHz band pass filter amplifying unit, is supplied to inside and outside reference clock selected cell after filtering and amplification;
Internal timebase signal generation unit needs to select 1MHz, 2MHz, 5MHz or 10MHz crystal oscillator accurate as the time disjunction mark of inside;
Second multi-harmonic-oscillations 10MHz frequency-selecting unit all converts 1MHz, 2MHz, 5MHz or 10MHz clock signal of internal timebase signal generation unit to 10MHz internal clock signal;
10MHz internal clock signal after second multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting is carried out filtering and amplification by the 2nd 10MHz band pass filter amplifying unit, is supplied to inside and outside reference clock selected cell after filtering and amplification;
Inside and outside reference clock selected cell is selected to select 10MHz external timing signal or 10MHz internal clock signal as required;
Clock signal after inside and outside reference clock selected cell selection becomes multipath clock and exports after clock driver cell drives;
1,2 or the 5MHz clock that 10MHz clock or outside provide for what be supplied to that the outside clock used selects to export by the control of control unit.
2. the synchro system of compatible multiple clock as claimed in claim 1; it is characterized in that; the function of described external clock coupling amplifying unit by the frequency that instrument outside provides be mainly 1,2,5 or 10MHz clock signal carry out every straight, impedance matching; input saturation protective circuit carries out amplitude limit simultaneously, then enters the two-stage amplifying circuit be made up of triode and amplifies.
3. the synchro system of compatible multiple clock as claimed in claim 2, it is characterized in that, described first multi-harmonic-oscillations 10MHz frequency-selecting unit with input after limited range enlargement 1,2,5 or 10MHz clock signal for trigger, through the 10MHz frequency-selective network be made up of lc circuit, 1,2,5 or 10MHz clock signal are all converted to 10MHz clock signal.
4. the synchro system of compatible multiple clock as claimed in claim 1, it is characterized in that, a described 10MHz band pass filter amplifying unit is by the LC band-pass filter of the 10MHz external timing signal after the first multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting through being made up of inductance capacitance, then triode is utilized to carry out two-stage amplification, make 10MHz clock signal meet the requirement changed to Transistor-Transistor Logic level by sine, be supplied to inside and outside reference clock selected cell.
5. the synchro system of compatible multiple clock as claimed in claim 1, it is characterized in that, base detecting unit, the first NAND gate, the second NAND gate, the 3rd NAND gate when described inside and outside reference clock selected cell comprises, time base detecting unit be connected with the first NAND gate, the second NAND gate, the 3rd NAND gate is connected with the first NAND gate, the second NAND gate.
6. the synchronous method of the synchro system of a compatible multiple clock, it is characterized in that, the synchronous method of the synchro system of described compatible multiple clock adopts the synchro system of compatible multiple clock according to claim 1, and the synchronous method of the synchro system of described compatible multiple clock comprises the following steps:
S1, external clock coupling amplifying unit by frequency be 1,2,5 or 10MHz clock signal carry out every straight, impedance matching, amplitude limit, amplification;
1,2,5 or 10MHz clock signal after external clock is mated amplifying unit process by S2, the first multi-harmonic-oscillations 10MHz frequency-selecting unit are all converted to 10MHz external timing signal;
10MHz external timing signal after first multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting is carried out filtering and amplification by S3, a 10MHz band pass filter amplifying unit, is supplied to inside and outside reference clock selected cell after filtering and amplification;
S4, internal timebase signal generation unit need to select 1MHz, 2MHz, 5MHz or 10MHz crystal oscillator accurate as the time disjunction mark of inside;
S5, the second multi-harmonic-oscillations 10MHz frequency-selecting unit all convert 1MHz, 2MHz, 5MHz or 10MHz clock signal of internal timebase signal generation unit to 10MHz internal clock signal;
10MHz internal clock signal after second multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting is carried out filtering and amplification by S6, the 2nd 10MHz band pass filter amplifying unit, is supplied to inside and outside reference clock selected cell after filtering and amplification;
S7, inside and outside reference clock selected cell are selected to select 10MHz external timing signal or 10MHz internal clock signal as required;
Clock signal after the selection of S8, inside and outside reference clock selected cell becomes multipath clock and exports after clock driver cell drives;
S9, be 1,2 or the 5MHz clock that 10MHz clock or outside provide for what be supplied to that the outside clock used selects to export by the control of control unit.
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| CN102970093A (en) | 2013-03-13 |
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