CN102970093A - Synchronizing system compatible with various clocks and synchronizing method thereof - Google Patents
Synchronizing system compatible with various clocks and synchronizing method thereof Download PDFInfo
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Abstract
The invention discloses a synchronizing system compatible with various clocks and a synchronizing method thereof. The synchronizing system comprises an external clock matching and amplifying unit and other units. The external clock matching and amplifying unit is connected with a first multivibrator 10MHz frequency-selecting unit and a clock driving unit, a first 10MHz band-pass filter amplifying unit is connected with the first multivibrator 10MHz frequency-selecting unit and an internal and external reference clock selecting unit, a internal time base signal generating unit is connected with a second multivibrator 10MHz frequency-selecting unit, a second 0MHz band-pass filter amplifying unit is connected with connected with the second multivibrator 10MHz frequency-selecting unit and the internal and external reference clock selecting unit, and the clock driving unit is connected with a control unit and the internal and external reference clock selecting unit. The synchronizing system can be compatible with various 1MHz, 2MHz, 5MHz and 10MHz clock inputs, provides a 10MHz clock output and can select 1MHz, 2MHz, 5MHzclock outputs according to external input clock frequency to solve the problem that different clock frequencies cannot be synchronized.
Description
Technical field
The present invention relates to a kind of synchro system, particularly relate to a kind of synchro system and method for synchronous thereof of compatible multiple clock.
Background technology
Development along with measuring technology, the situation that multiple measuring instrument uses together is more and more, the situation of utilizing various measuring instruments establishment test macros to test is also more and more, for precision and the accuracy that guarantees to measure, eliminate owing to the asynchronous measure error of introducing of each measuring instrument clock, often the clock signal of used measuring instrument need to be carried out synchronously.But because the standard time clock frequency that each apparatus manufacture is selected is different, so the clock signal of its output that provides also is not quite similar, if any 1MHz clock output is provided, the 5MHz clock that provides that has is exported, the 10MHz clock that provides that has is exported, and the input of the clock of instrument mostly is 10MHz, and this will cause between each instrument, and clock can't be synchronous, thereby increased measure error.
Existing solution can be summarized as two kinds substantially, and the first scheme is frequency multiplication frequency-dividing clock synchronization scenario, and the first scheme realizes the synchronous of interior external clock by the method for frequency multiplication or frequency division.Be specially when the standard time clock of selecting is lower than 10MHz, for the 10MHz output clock of standard can be provided, clock system is standing counts into frequency multiplier circuit, as depicted in figs. 1 and 2.When the standard time clock of selecting is 1MHz, need to through 10 frequency multiplication unit, produce the output clock of 10MHz.When the standard time clock of selecting is 5MHz, need to through 2 frequency multiplication unit, produce the output clock of 10MHz.Simultaneously for can with the clock synchronous of instrument outside, also to design corresponding frequency dividing circuit, produce the inner clock signal of using.
First scheme is the scheme that base carries out clock synchronous when directly selecting 10MHz, disregards exactly cost, directly selects the 10MHz clock as the standard time clock of instrument internal, and the output of 10MHz reference clock so just can directly be provided.
The shortcoming of the first scheme is as follows: poor compatibility, synchronous 10MHz clock still can't be realized the problem of clock synchronous when external reference is 1MHz, 2MHz, 5MHz clock frequency commonly used.
The first scheme shortcoming is as follows: cost is high, in the time of when instrument does not need to use the 10MHz clock, also will selecting the 10MHz standard base as inner reference clock, and the price about 30%～50% of base when the price of base is than 5MHz or 1MHz during the 10MHz standard.The problem that also has simultaneously the poor compatibility identical with the first scheme, synchronously 10MHz clock, the synchronously clock commonly used of other frequencies.
Summary of the invention
Technical problem to be solved by this invention provides a kind of synchro system and method for synchronous thereof of compatible multiple clock, it can compatible 1MHz, 2MHz, 5MHz and the input of 10MHz multiple clock, the output of acquiescence 10MHz clock is provided, according to the optional 1MHz of outside input clock frequency, 2MHz, the output of 5MHz clock, solve the problem that different clock frequencies can't be synchronous, thereby guarantee the precision of apparatus measures, eliminate the measure error of introducing owing to clock is asynchronous.
The present invention solves above-mentioned technical problem by following technical proposals: a kind of synchro system of compatible multiple clock, it is characterized in that, it comprises external clock coupling amplifying unit, internal timebase signal generation unit, the first multi-harmonic-oscillations 10MHz frequency-selecting unit, the second multi-harmonic-oscillations 10MHz frequency-selecting unit, the one 10MHz band pass filter amplifying unit, the 2nd 10MHz band pass filter amplifying unit, inside and outside reference clock selected cell, clock driver element and control unit, external clock coupling amplifying unit and the first multi-harmonic-oscillations 10MHz frequency-selecting unit, the clock driver element connects, the one 10MHz band pass filter amplifying unit and the first multi-harmonic-oscillations 10MHz frequency-selecting unit, inside and outside reference clock selected cell connects, internal timebase signal generation unit is connected with the second multi-harmonic-oscillations 10MHz frequency-selecting unit, the 2nd 10MHz band pass filter amplifying unit and the second multi-harmonic-oscillations 10MHz frequency-selecting unit, inside and outside reference clock selected cell connects clock driver element and control unit, inside and outside reference clock selected cell connects.
Preferably; the function of described external clock coupling amplifying unit mainly be with the frequency that the instrument outside provides be 1,2,5 or the 10MHz clock signal carry out every straight, impedance matching; the input saturation protective circuit is carried out amplitude limit simultaneously, then enters the two-stage amplifying circuit that is comprised of triode and amplifies.
Preferably, 1,2,5 or 10MHz clock signal that described the first multi-harmonic-oscillations 10MHz frequency-selecting unit is inputted behind the limited range enlargement are as triggering, through the 10MHz frequency-selective network that is formed by lc circuit, with 1,2,5 or the 10MHz clock signal all converted the 10MHz clock signal to.
Preferably, the LC band-pass filter of the 10MHz external timing signal of a described 10MHz band pass filter amplifying unit after with the first multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting through being formed by inductance capacitance, then utilizing triode to carry out two-stage amplifies, the 10MHz clock signal is satisfied by the requirement of sine to the Transistor-Transistor Logic level conversion, offer inside and outside reference clock selected cell.
Preferably, base detecting unit, the first NAND gate, the second NAND gate, the 3rd NAND gate when described inside and outside reference clock selected cell comprises, the time base detecting unit be connected with the first NAND gate, the second NAND gate, the 3rd NAND gate is connected with the first NAND gate, the second NAND gate.
The present invention also provides a kind of method for synchronous of synchro system of compatible multiple clock, it is characterized in that, the method for synchronous of the synchro system of described compatible multiple clock adopts the synchro system of above-mentioned compatible multiple clock, and the method for synchronous of the synchro system of described compatible multiple clock may further comprise the steps:
S1, external clock coupling amplifying unit with frequency be 1,2,5 or the 10MHz clock signal carry out every straight, impedance matching, amplitude limit, amplification;
S2, the first multi-harmonic-oscillations 10MHz frequency-selecting unit have all converted 1,2,5 or the 10MHz clock signal that external clock mates after amplifying unit is processed to the 10MHz external timing signal;
S3, the 10MHz band pass filter amplifying unit 10MHz external timing signal after with the first multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting carries out filtering and amplification, filtering and amplify after offer inside and outside reference clock selected cell;
S4, internal timebase signal generation unit select 1MHz, 2MHz, 5MHz or 10MHz crystal oscillator accurate as the time disjunction mark of inside as required;
S5, the second multi-harmonic-oscillations 10MHz frequency-selecting unit all convert 1MHz, 2MHz, 5MHz or the 10MHz clock signal of internal timebase signal generation unit to the 10MHz internal clock signal;
S6, the 2nd 10MHz band pass filter amplifying unit 10MHz internal clock signal after with the second multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting carries out filtering and amplification, filtering and amplify after offer inside and outside reference clock selected cell;
S7, inside and outside reference clock selected cell selective basis need to be selected 10MHz external timing signal or 10MHz internal clock signal;
Clock signal after S8, inside and outside reference clock selected cell are selected becomes multipath clock output after the clock drive unit drives;
S9, what select to export by the control of control unit for the clock that offers outside usefulness is 10MHz clock or outside 1,2 or the 5MHz clock that provides.
Positive progressive effect of the present invention is: one, the present invention can compatible 1MHz, 2MHz, the clock input signal of 5MHz and four kinds of different frequencies of 10MHz, the clock signal that provides simultaneously is except 10MHz, can also select output according to the clock signal of outside input is 1MHz, 2MHz or 5MHz clock, solved can't be synchronous between the different clock frequencies signal problem.That two, no matter internal timebase of the present invention is selected is 1MHz, 2MHz, 5MHz or 10MHz, all can produce the 10MHz clock signal with synchro system and the method for synchronous thereof of the compatible multiple clock of the present invention, and circuit is simple, cost is low, the compatibility is good.
Description of drawings
The theory diagram of the inside and outside clock system when Fig. 1 is 1MHz for existing internal clocking.
The theory diagram of the inside and outside clock system when Fig. 2 is 5MHz for existing internal clocking.
Fig. 3 is the theory diagram of the synchro system of the compatible multiple clock of the present invention.
Fig. 4 is the theory diagram of peripheral clock coupling amplifying unit of the present invention.
Fig. 5 is the theory diagram of the first multi-harmonic-oscillations 10MHz frequency-selecting unit among the present invention.
Fig. 6 is the theory diagram of a 10MHz band pass filter amplifying unit among the present invention.
Fig. 7 is the theory diagram of inside and outside reference clock selected cell among the present invention.
Fig. 8 is the theory diagram of clock driver element and control unit among the present invention.
Embodiment
Provide preferred embodiment of the present invention below in conjunction with accompanying drawing, to describe technical scheme of the present invention in detail.
As shown in Figure 3, the synchro system of the compatible multiple clock of the present invention comprises external clock coupling amplifying unit, internal timebase signal generation unit, the first multi-harmonic-oscillations 10MHz frequency-selecting unit, the second multi-harmonic-oscillations 10MHz frequency-selecting unit, the one 10MHz band pass filter (Band-Pass Filter, BPF) amplifying unit, the 2nd 10MHz band pass filter amplifying unit, inside and outside reference clock selected cell, clock driver element and control unit, external clock coupling amplifying unit and the first multi-harmonic-oscillations 10MHz frequency-selecting unit, the clock driver element connects, the one 10MHz band pass filter amplifying unit and the first multi-harmonic-oscillations 10MHz frequency-selecting unit, inside and outside reference clock selected cell connects, internal timebase signal generation unit is connected with the second multi-harmonic-oscillations 10MHz frequency-selecting unit, the 2nd 10MHz band pass filter amplifying unit and the second multi-harmonic-oscillations 10MHz frequency-selecting unit, inside and outside reference clock selected cell connects clock driver element and control unit, inside and outside reference clock selected cell connects.
The function of external clock coupling amplifying unit mainly is to be 1 with the frequency that the instrument outside provides; 2; 5 or 10MHz clock signal (clock signal is that amplitude is greater than sinusoidal signal or the square-wave signal of 0.6Vp-p) as shown in Figure 4; external clock coupling amplifying unit comprises every straight unit; impedance matching unit; limiter protection circuit and amplifying circuit; every straight unit; impedance matching unit; limiter protection circuit is connected with amplifying circuit and is connected; the specific works process is as follows: at first carry out every directly; impedance matching; the input saturation protective circuit is carried out amplitude limit simultaneously, and is excessive to prevent input signal amplitude.Then enter the two-stage amplifying circuit that is formed by triode and amplify, to satisfy the input request signal of the first multi-harmonic-oscillations 10MHz frequency-selecting unit.With incoming frequency 1MHz, the sinusoidal signal of amplitude 0.6Vp-p is example, and having become amplitude after the external clock coupling is amplified is the sinusoidal signal of 2.4Vp-p, and satisfying the first multi-harmonic-oscillations 10MHz frequency-selecting unit high level minimum is the triggering requirement of 2V.
After the first multi-harmonic-oscillations 10MHz frequency-selecting unit mates external clock amplifying unit and processes 1,2,5 or the 10MHz clock signal all convert the 10MHz external timing signal to, as shown in Figure 5, the first multi-harmonic-oscillations 10MHz frequency-selecting unit comprises multi-harmonic-oscillations unit and frequency-selecting unit, the multi-harmonic-oscillations unit is connected with the frequency-selecting unit, the specific works process is as follows: with input behind the limited range enlargement 1,2,5 or the 10MHz clock signal for triggering, select one-shot multivibrator (model is 74LS221) to be designed to the multi-harmonic-oscillations unit, the signal of multi-harmonic-oscillations unit output is that pulse duration is the harmonic signal of a series of external timing signal frequency of 50ns, through the 10MHz frequency-selective network that is formed by lc circuit, with 1,2,5 or the 10MHz clock signal all converted the 10MHz clock signal to.The first multi-harmonic-oscillations 10MHz frequency-selecting unit can be made of multivibrator.
As shown in Figure 6, a 10MHz band pass filter amplifying unit comprises LC band pass filter and triode.The function of the one 10MHz band pass filter amplifying unit is as follows: the LC band-pass filter of the 10MHz external timing signal of a 10MHz band pass filter amplifying unit after with the first multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting through being comprised of inductance capacitance, then utilizing triode to carry out two-stage amplifies, the 10MHz clock signal is satisfied by the requirement of sine to the Transistor-Transistor Logic level conversion, offer inside and outside reference clock selected cell.
Internal timebase signal generation unit can select 1MHz, 2MHz, 5MHz or 10MHz crystal oscillator accurate as the time disjunction mark of inside according to appliance requires.Then the same with external timing signal, enter the second multi-harmonic-oscillations 10MHz frequency-selecting unit, the second multi-harmonic-oscillations 10MHz frequency-selecting unit all converts 1MHz, 2MHz, 5MHz or the 10MHz clock signal of internal timebase signal generation unit to the 10MHz internal clock signal, after filtering through entering the 2nd 10MHz band pass filter amplifying unit and the amplification, offer inside and outside reference clock selected cell again.The Nei Shiji passage of internal timebase signal generation unit adopts the processing mode identical with the external timing passage, utilize the frequency multiplication unit in the second multi-harmonic-oscillations 10MHz frequency-selecting unit replacement Fig. 1 and Fig. 2 implementation, advantage is to utilize the lower crystal oscillator of low price, frequency as the internal timebase reference, the internal timebase of different frequency, utilize circuit kit, just can realize 10MHz with reference to output, simple, compatible good, the highly versatile of circuit.The theory diagram of the second multi-harmonic-oscillations 10MHz frequency-selecting unit is the same with the theory diagram of the first multi-harmonic-oscillations 10MHz frequency-selecting unit shown in Figure 5, and the theory diagram of the 2nd 10MHz band pass filter amplifying unit is the same with the theory diagram of a 10MHz band pass filter amplifying unit shown in Figure 6.
Inside and outside reference clock selected cell selective basis need to be selected 10MHz external timing signal or 10MHz internal clock signal, the theory diagram of inside and outside reference clock selected cell as shown in Figure 7, base detecting unit when inside and outside reference clock selected cell comprises, the first NAND gate U1-A, the second NAND gate U1-B, the 3rd NAND gate U1-C, time base detecting unit and the first NAND gate U1-A, the second NAND gate U1-B connects, the 3rd NAND gate U1-C and the first NAND gate U1-A, the second NAND gate U1-B connects, inside and outside reference clock selected cell at first converts sinusoidal signal to the TTL signal, being about to the external timing signal that a 10MHz band pass filter amplifying unit sends over becomes the TTL signal and the TTL signal is divided into two-way, one tunnel input as the second NAND gate U1-B, base detecting unit when give on another road.But the multivibrator (model is 74LS123) of time base detecting unit utilization repeated trigger consists of automatic detection circuit, and the width design of trigger impulse is 1.2 μ s, and external clock has become pulse duration after conversion be the signal of 50ns.When the external timing signal input was arranged, the Q end of multivibrator was output as high level, and/Q end is output as low level; When not having the external timing signal input, Q holds output low level, and/Q end is output as high level.The Q end output signal of time base detecting unit is received another input of the second NAND gate U1-B, controls the output of NAND gate.The internal timebase signal becomes behind the Transistor-Transistor Logic level input as 2 inputs the first NAND gate U1-A, another input of the first NAND gate U1-A from the time base detecting unit /Q holds output.When external timing signal was arranged, the Q of time base detecting unit end was output as high level, and/Q end is output as low level, and NAND gate U1-A is output as high level, and internal clock signal is under an embargo, and external timing signal is effective, can output to the 3rd NAND gate U1-C; Otherwise the Q end of time base detecting unit is output as low level, and/Q end is output as high level, the second NAND gate U1-B is output as high level, and external timing signal is under an embargo, and internal clock signal is effective, can output to the 3rd NAND gate U1-C, thereby realize the automatic switchover of inside and outside clock signal.
The major function of clock driver element is that the clock signal (being the 10MHz signal) after selecting through inside and outside reference clock selected cell is become multipath clock output after the clock drive unit drives, offers respectively the outside use of instrument internal use and instrument.NOR gate line drive (for example 74128 models) can be used as the clock driver element.As shown in Figure 8, the clock driver element can comprise the first NOR gate U2-A, the second NOR gate U2-B, the 3rd NOR gate U2-C.
What can select to export by the control of control unit for the clock that offers outside usefulness be the 10MHz clock, or outside 1,2 or the 5MHz clock that provides.As shown in Figure 8, control unit comprise first with a door U3-A, second with door U3-B and four nor gate U2-D, first all is connected with four nor gate U2-D with a U3-B with a U3-A, second.The first control signal CTRL1 and the second control signal CTRL2 are from central processing unit (CPU), when the first control signal CTRL1 is high level, when the second control signal CTRL2 is low level, first with the door U3-A be output as 10MHz, second with the door U3-B be output as low level, so when the clock of four nor gate U2-D is output as 10MHz.When the first control signal CTRL1 is low level, when the second control signal CTRL2 is high level, first is output as low level with a door U3-A, and second is output as 1MHz, 2MHz or the 5MHz of outside input with door U3-B, so the clock of four nor gate U2-D is output as 1MHz, 2MHz or 5MHz.Thereby realized providing the output of acquiescence 10MHz clock, according to the function of the optional 1MHz of outside input clock, 2MHz or the output of 5MHz clock.
The method for synchronous of the synchro system of the compatible multiple clock of the present invention may further comprise the steps:
S1, external clock coupling amplifying unit with frequency be 1,2,5 or the 10MHz clock signal carry out every straight, impedance matching, amplitude limit, amplification;
S2, the first multi-harmonic-oscillations 10MHz frequency-selecting unit have all converted 1,2,5 or the 10MHz clock signal that external clock mates after amplifying unit is processed to the 10MHz external timing signal;
S3, the 10MHz band pass filter amplifying unit 10MHz external timing signal after with the first multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting carries out filtering and amplification, filtering and amplify after offer inside and outside reference clock selected cell;
S4, internal timebase signal generation unit select 1MHz, 2MHz, 5MHz or 10MHz crystal oscillator accurate as the time disjunction mark of inside as required;
S5, the second multi-harmonic-oscillations 10MHz frequency-selecting unit all convert 1MHz, 2MHz, 5MHz or the 10MHz clock signal of internal timebase signal generation unit to the 10MHz internal clock signal;
S6, the 2nd 10MHz band pass filter amplifying unit 10MHz internal clock signal after with the second multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting carries out filtering and amplification, filtering and amplify after offer inside and outside reference clock selected cell;
S7, inside and outside reference clock selected cell selective basis need to be selected 10MHz external timing signal or 10MHz internal clock signal;
Clock signal after S8, inside and outside reference clock selected cell are selected becomes multipath clock output after the clock drive unit drives;
S9, what select to export by the control of control unit for the clock that offers outside usefulness is 10MHz clock or outside 1,2 or the 5MHz clock that provides.
Operation principle of the present invention is as follows: when the clock signal of outside input is 1MHz, 2MHz, 5MHz or 10MHz, at first after coupling is amplified, enter into the first multi-harmonic-oscillations 10MHz frequency-selecting unit, the output signal of the first multi-harmonic-oscillations 10MHz frequency-selecting unit is that pulse duration is the harmonic signal of a series of external timing signal of 50ns.When being 1MHz such as external clock, the output signal of the first multi-harmonic-oscillations 10MHz frequency-selecting unit is exactly that first-harmonic and each harmonic by 1MHz forms, and wherein 10 subharmonic are exactly the 10MHz signal; When external clock was 2MHz, the output of the first multi-harmonic-oscillations 10MHz frequency-selecting unit was exactly that first-harmonic and each harmonic by 2MHz forms, and wherein 5 subharmonic are exactly the 10MHz signal; When external clock was 5MHz, the output of the first multi-harmonic-oscillations 10MHz frequency-selecting unit was comprised of first-harmonic and the each harmonic of 5MHz, and wherein 2 subharmonic are exactly 10MHz; When the outside was input as 10MHz, the output of the first multi-harmonic-oscillations 10MHz frequency-selecting unit was exactly that first-harmonic and each harmonic by 10MHz forms, and wherein first-harmonic is exactly 10MHz; Through the frequency-selecting unit of 10MHz, the 10MHz signal just is retained like this, and remaining harmonic signal all is attenuated, thereby has realized 1MHz, 2MHz, 5MHz or 10MHz signal all have been transformed into the 10MHz signal.Behind the filter and amplification of a 10MHz band pass filter amplifying unit, deliver to inside and outside reference clock selected cell.Internal timebase signal generation unit can select as required 1,2,5 or the 10MHz crystal oscillator accurate as the time disjunction mark of inside, identical with the clock of outside input, behind the second multi-harmonic-oscillations 10MHz frequency-selecting unit, also all become the 10MHz signal, behind the filter and amplification of the 2nd 10MHz band pass filter amplifying unit, delivered to inside and outside reference clock selected cell.As shown in Figure 7, when external clock 10MHz signal (10MHz after this 10MHz is to amplify through the multi-harmonic-oscillations frequency-selecting) is arranged, the time base detecting unit the Q end be output as high level 1 ,/Q end is output as low level 0, U1-C is output as external clock; When not having external clock, the Q of time base detecting unit end is output as low level 0, and/Q end is output as high level 1, the three NAND gate U1-C and is output as internal clocking.After interior External Reference is selected, offer drive circuit, after driving, become multiple signals and offered respectively instrument internal and outside the use.As shown in Figure 8, offer the outside signal that uses and to realize that through the first control signal CTRL1 and the second control signal CTRL2 control output is 10MHz or 1,2 or 5MHz.When the first control signal CTRL1 is high level 1, the second control signal CTRL2 when being low level 0, the clock of four nor gate U2-D is output as 10MHz; When the first control signal CTRL1 is that low level 0, the second control signal CTRL2 is that high level 1 is, the clock of four nor gate U2-D is output as 1,2 or 5MHz.Therefore the present invention can realize compatibility 1,2,5 or the reference of 10MHz external clock, and the output of acquiescence 10MHz clock is provided, according to clock optional 1,2 or the output of 5MHz clock of outside input.In sum, the present invention can compatible 1MHz, 2MHz, the clock input signal of 5MHz and four kinds of different frequencies of 10MHz, and the clock signal of output is except 10MHz, and also can select according to the clock of outside input is 1MHz, 2MHz or 5MHz clock.That no matter internal timebase is selected is 1MHz, 2MHz, 5MHz or 10MHz, all can utilize synchro system and the method for synchronous thereof of the compatible multiple clock of the present invention to produce the 10MHz clock signal.
Those skilled in the art can carry out various remodeling and change to the present invention.Therefore, the present invention has covered various remodeling and the change in the scope that falls into appending claims and equivalent thereof.
Claims (6)
1. the synchro system of a compatible multiple clock, it is characterized in that, it comprises external clock coupling amplifying unit, internal timebase signal generation unit, the first multi-harmonic-oscillations 10MHz frequency-selecting unit, the second multi-harmonic-oscillations 10MHz frequency-selecting unit, the one 10MHz band pass filter amplifying unit, the 2nd 10MHz band pass filter amplifying unit, inside and outside reference clock selected cell, clock driver element and control unit, external clock coupling amplifying unit and the first multi-harmonic-oscillations 10MHz frequency-selecting unit, the clock driver element connects, the one 10MHz band pass filter amplifying unit and the first multi-harmonic-oscillations 10MHz frequency-selecting unit, inside and outside reference clock selected cell connects, internal timebase signal generation unit is connected with the second multi-harmonic-oscillations 10MHz frequency-selecting unit, the 2nd 10MHz band pass filter amplifying unit and the second multi-harmonic-oscillations 10MHz frequency-selecting unit, inside and outside reference clock selected cell connects clock driver element and control unit, inside and outside reference clock selected cell connects.
2. the synchro system of compatible multiple clock as claimed in claim 1; it is characterized in that; the function of described external clock coupling amplifying unit mainly be with the frequency that the instrument outside provides be 1,2,5 or the 10MHz clock signal carry out every straight, impedance matching; the input saturation protective circuit is carried out amplitude limit simultaneously, then enters the two-stage amplifying circuit that is comprised of triode and amplifies.
3. the synchro system of compatible multiple clock as claimed in claim 2, it is characterized in that, 1,2,5 or 10MHz clock signal that described the first multi-harmonic-oscillations 10MHz frequency-selecting unit is inputted behind the limited range enlargement are as triggering, through the 10MHz frequency-selective network that is formed by lc circuit, with 1,2,5 or the 10MHz clock signal all converted the 10MHz clock signal to.
4. the synchro system of compatible multiple clock as claimed in claim 1, it is characterized in that, the LC band-pass filter of the 10MHz external timing signal of a described 10MHz band pass filter amplifying unit after with the first multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting through being formed by inductance capacitance, then utilizing triode to carry out two-stage amplifies, the 10MHz clock signal is satisfied by the requirement of sine to the Transistor-Transistor Logic level conversion, offer inside and outside reference clock selected cell.
5. the synchro system of compatible multiple clock as claimed in claim 1, it is characterized in that, base detecting unit, the first NAND gate, the second NAND gate, the 3rd NAND gate when described inside and outside reference clock selected cell comprises, time base detecting unit is connected with the first NAND gate, the second NAND gate, and the 3rd NAND gate is connected with the first NAND gate, the second NAND gate.
6. the method for synchronous of the synchro system of a compatible multiple clock, it is characterized in that, the method for synchronous of the synchro system of described compatible multiple clock adopts the synchro system of compatible multiple clock claimed in claim 1, and the method for synchronous of the synchro system of described compatible multiple clock may further comprise the steps:
S1, external clock coupling amplifying unit with frequency be 1,2,5 or the 10MHz clock signal carry out every straight, impedance matching, amplitude limit, amplification;
S2, the first multi-harmonic-oscillations 10MHz frequency-selecting unit have all converted 1,2,5 or the 10MHz clock signal that external clock mates after amplifying unit is processed to the 10MHz external timing signal;
S3, the 10MHz band pass filter amplifying unit 10MHz external timing signal after with the first multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting carries out filtering and amplification, filtering and amplify after offer inside and outside reference clock selected cell;
S4, internal timebase signal generation unit select 1MHz, 2MHz, 5MHz or 10MHz crystal oscillator accurate as the time disjunction mark of inside as required;
S5, the second multi-harmonic-oscillations 10MHz frequency-selecting unit all convert 1MHz, 2MHz, 5MHz or the 10MHz clock signal of internal timebase signal generation unit to the 10MHz internal clock signal;
S6, the 2nd 10MHz band pass filter amplifying unit 10MHz internal clock signal after with the second multi-harmonic-oscillations 10MHz frequency-selecting unit frequency-selecting carries out filtering and amplification, filtering and amplify after offer inside and outside reference clock selected cell;
S7, inside and outside reference clock selected cell selective basis need to be selected 10MHz external timing signal or 10MHz internal clock signal;
Clock signal after S8, inside and outside reference clock selected cell are selected becomes multipath clock output after the clock drive unit drives;
S9, what select to export by the control of control unit for the clock that offers outside usefulness is 10MHz clock or outside 1,2 or the 5MHz clock that provides.
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| CN105187056A (en) * | 2015-09-06 | 2015-12-23 | 四川九洲电器集团有限责任公司 | Clock signal generation apparatus and clock signal generation method |
| CN106027041A (en) * | 2016-05-12 | 2016-10-12 | 中国电子科技集团公司第四十研究所 | High-performance self-test external reference time-base circuit and implementation method thereof |
| CN109669507A (en) * | 2018-11-09 | 2019-04-23 | 中电科仪器仪表有限公司 | A kind of the generation circuit and control method of digital oscilloscope reference clock |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105187056A (en) * | 2015-09-06 | 2015-12-23 | 四川九洲电器集团有限责任公司 | Clock signal generation apparatus and clock signal generation method |
| CN105187056B (en) * | 2015-09-06 | 2019-02-26 | 四川九洲电器集团有限责任公司 | A kind of clock signal generating device and clock signal creating method |
| CN106027041A (en) * | 2016-05-12 | 2016-10-12 | 中国电子科技集团公司第四十研究所 | High-performance self-test external reference time-base circuit and implementation method thereof |
| CN106027041B (en) * | 2016-05-12 | 2019-03-05 | 中国电子科技集团公司第四十一研究所 | A kind of high-performance self-test External Reference time base circuit and its implementation |
| CN109669507A (en) * | 2018-11-09 | 2019-04-23 | 中电科仪器仪表有限公司 | A kind of the generation circuit and control method of digital oscilloscope reference clock |
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| CN102970093B (en) | 2015-12-16 |
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