CN102315927A - Clock synchronization device and method - Google Patents
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Abstract
The invention discloses a clock synchronization device and method. The device comprises a phase discriminator, a loop filter, a voltage-controlled oscillator, a frequency synthesizer and a clock driver in the sequential connection, wherein clock signals output by the clock driver are fed back to an input end of the phase discriminator after being subjected to frequency division by a frequency divider; phase discrimination is carried out on the clock signals which is subjected to the frequency division and reference clock signals by the phase discriminator, and the obtained phase discrimination value is input to the loop filter; after the input phase discrimination value is subjected to low pass filtering by the loop filter, voltage signals are obtained and then input to the voltage-controlled oscillator, and the voltage-controlled oscillator controls the clock signals generated by oscillation according to the input voltage signals; and after the frequency synthesizer performs the frequency synthesis on the clock signals generated by the oscillation, the obtained clock signals with set frequencies are input into the clock driver, and the clock driver drives the clock signals to generate the required clock signals. According to the invention, the phase position of a clock can be controlled and output accurately, and the system clock performance is improved.
Description
Technical field
The present invention relates to the clock technology in the communications field, relate in particular to a kind of clock synchronization apparatus and method.
Background technology
For communication network, it need provide the business of multiple different application, from general service to intelligent value-added service, from voice to data, integrated service such as image, multiple business and deposit and make the clock problem of system seem more and more important.
The stable clock signal is the basis of various device operate as normal in the communication network, if there is not good clock signal, digital information just phenomenons such as error code, slip can occur inevitably in transmittance process, thereby causes the decline of communication quality.According to the difference of business, its influence degree is also different.For example, for voice call, can hear click; Facsimile service can cause information incomplete; The data service packet loss can increase; Image transmits and phenomenons such as smudgy can occur.Therefore in order to ensure quality of service, clock system is absolutely necessary in communication network.
The clock phase-locked loop technology is the core technology of clock system; Its principle is through the clock signal of output is carried out phase demodulation as the clock signal of feedback signal and timing reference input generation; According to the clock signal of identified result control output, thereby make the signal of clock signal of output consistent with the phase place of the clock signal of timing reference input generation.
Can the communication equipment clock quality is directly connected to digital communication network operate as normal, and therefore good timing reference input is most important.Usually timing reference input is from a high stability and high-precision reference clock source (for example caesium clock or rubidium clock); Or with GPS (Global Positioning System; Global positioning system) as timing reference input; In communication equipment, also usually extract reference clock signal through circuit, as: in the E1 line signal, in SDH (Synchronous Digital Hierarchy, the synchronous digital hierarchy) line signal, extract reference clock signal.Because the reference clock signal of these receptions has all passed through long propagation distance, directly recovers to have shake or drift from circuit, must be at receiving terminal with these interference filterings.
Existing clock synchronization apparatus has adopted PHASE-LOCKED LOOP PLL TECHNIQUE and the reference clock signal that receives has been carried out interference filtering; Be illustrated in figure 1 as the structure of present clock synchronization apparatus; It mainly comprises phase discriminator, loop filter, voltage controlled oscillator, frequency divider, frequency synthesizer and clock driver, and said apparatus realizes that the principle of clock synchronization is following:
Phase discriminator carries out phase demodulation to the f0 and the f1 of input; After adopting sample frequency F to sample the simulation phase demodulation value (being phase difference) that obtains; The digital phase demodulation value that sampling is obtained is input in the loop filter, the reference clock signal imported into for the clock source of f0 wherein, and F is the frequency of the clock signal f of voltage controlled oscillator output; F1 is that the clock signal f of voltage controlled oscillator output feeds back the clock signal of coming in through N frequency division of frequency divider, and N is the positive number more than or equal to 2;
Loop filter carries out LPF to the digital phase demodulation value that receives from phase discriminator; Eliminate because the transmission generation shake of parameter clock signal and shifted signal to the influence of phase demodulation value, convert filtered digital phase discriminator into analog voltage signal through digital to analog converter (DA transducer) and output to voltage controlled oscillator;
Voltage controlled oscillator is according to the phase value of the analog voltage signal control clock signal of input.
It is thus clear that phase discriminator, loop filter, voltage controlled oscillator are formed the phase place degeneration factor, thereby adopt PHASE-LOCKED LOOP PLL TECHNIQUE to realize that f0 is consistent with the phase place of f1, realize lock phase purpose.
Frequency synthesizer carries out frequency synthesis to the clock signal of voltage controlled oscillator output; As carry out frequency multiplication or carry out frequency division etc.; Obtain the clock signal of actual needs; And the clock signal that obtains is input in the clock driver, by the multipath clock signal of clock driver according to the clock signal driving and generating equipment needs of input.Frequency synthesizer generally also adopts phase-locked loop circuit, and the clock signal of voltage controlled oscillator output is advanced horizontal lock once more, obtains the clock frequency that system needs.
Above-mentioned clock synchronization apparatus can not guarantee that because this device has passed through after frequency synthesizer and the clock driver circuit, the clock signal of output all can have the variation of phase place, and changing value is not known to the phase place of output clock.Even if guaranteed f0 and f1 same-phase, also do not had practical significance.And the two-stage phase-locked loop is independently, and the shake of previous stage can continue to pass to next stage, thereby influences the index of system.Therefore the existing shortcoming of above-mentioned clock synchronization apparatus is: the phase place of the clock signal of final output is uncontrollable and the clock system index is bad.
Summary of the invention
The object of the present invention is to provide a kind of clock synchronization apparatus and method that can realize accurate clock signal, so that the clock index of synchronizer to be provided in the communication network equipment.
The present invention provides a kind of clock synchronization apparatus, comprises the phase discriminator, loop filter, voltage controlled oscillator, frequency synthesizer and the clock driver that connect successively, wherein,
The clock signal of said clock driver output feeds back to the input of phase discriminator behind the frequency divider frequency division;
Clock signal and the reference clock signal of said phase discriminator after to frequency division carries out phase demodulation, and the phase demodulation value that obtains is input to loop filter;
Behind the phase demodulation value LPF of said loop filter to input, obtain voltage signal and be input to voltage controlled oscillator, by the clock signal of said voltage controlled oscillator according to the voltage signal control vibration generation of input;
After the clock signal that said frequency synthesizer produces vibration was carried out frequency synthesis, the clock signal that obtains setpoint frequency was input to clock driver, by the clock signal of clock driver driving and generating needs.
The present invention also provides a kind of and carries out the method for clock synchronization based on said apparatus, comprising:
Reference clock signal f0 and clock signal f1 are sent in the phase discriminator, and said f1 is the clock signal that the clock signal of clock driver output obtains behind the frequency divider frequency division;
Carry out phase demodulation through the clock signal and the reference clock signal of phase discriminator after, the phase demodulation value that obtains is input to loop filter frequency division;
Behind the phase demodulation value LPF of loop filter, obtain voltage signal and be input to voltage controlled oscillator, by the clock signal of said voltage controlled oscillator according to the voltage signal control vibration generation of input to input;
After the clock signal that vibration is produced through frequency synthesizer was carried out frequency synthesis, the clock signal that obtains setpoint frequency was input to clock driver, the clock signal that is needed by the clock driver driving and generating.
Utilize clock synchronization apparatus provided by the invention and method to have following beneficial effect:
1) can guarantee that clock synchronization apparatus can reliablely and stablely work, precision is high, can be applied in the various occasions that need high precision synchronous;
2) structure is flexible, can control cost according to concrete needs adjustment design;
3) controlled step is succinct, has guaranteed that like this circuit is efficient and amount of calculation is little, just can realize with processor cheaply;
4) be easy to control the phase place of exporting clock, improve the clock system performance.
Description of drawings
Fig. 1 is a clock synchronization apparatus structure chart of the prior art;
The clock synchronization apparatus structure chart that Fig. 2 provides for the embodiment of the invention;
Fig. 3 is the sequential organization figure of phase discriminator in the embodiment of the invention;
Fig. 4 is a clock synchronizing method flow chart in the embodiment of the invention;
Fig. 5 is the lock phase control flow chart of embodiment of the invention intermediate ring road filter.
Embodiment
Below in conjunction with accompanying drawing and embodiment clock synchronization apparatus provided by the invention and method are illustrated in greater detail.
The object of the present invention is to provide a kind of new clock synchronization apparatus and method; Eliminate the shake and the drift that produce in the present reference source; For the various types of communication system provides a high performance clock system, can certainly be applied in and lock mutually relevant other field.
The clock synchronization apparatus that the embodiment of the invention provides, as shown in Figure 2, comprise the phase discriminator, loop filter, voltage controlled oscillator, frequency synthesizer and the clock driver that connect successively, wherein,
The clock signal f of clock driver output feeds back to the input of phase discriminator behind the frequency divider frequency division, according to Fig. 2, obtain clock signal f1 behind the frequency division;
Clock signal f1 and the reference clock signal f0 of phase discriminator after to frequency division carries out phase demodulation, and the phase demodulation value that obtains is input to loop filter, utilizes phase discriminator can obtain the phase difference of two-way clock signal, and the concrete structure of phase discriminator can adopt the available circuit structure;
Behind the phase demodulation value LPF of loop filter to input; Obtain voltage signal and be input to voltage controlled oscillator; By the clock signal of said voltage controlled oscillator according to the voltage signal control vibration generation of input; Through the LPF of loop filter, can eliminate shake and drift that the reference clock signal of reference source output produces because of transmission, the voltage signal that loop filter produces has reflected the phase place extent; Thereby voltage controlled oscillator is controlled the clock signal that vibration produces, made the phase place of clock signal of clock driver output consistent with the phase place of reference clock signal;
After the clock signal that frequency synthesizer produces vibration is carried out frequency synthesis; The clock signal that obtains setpoint frequency is input to clock driver; Clock signal by clock driver driving and generating needs; Utilize frequency synthesizer can obtain the clock frequency that needs, and the clock signal of frequency synthesizer output can not be input in the equipment usually, therefore need clock driver the electric current of clock signal to be increased or carries out driving the clock signal of output equipment needs after many processing.
The clock synchronization apparatus that the embodiment of the invention provides; Because clock signal and reference clock signal that phase discriminator will finally be exported carry out phase demodulation; Therefore be easy to control the phase place of output clock, improved the system clock performance, avoid the influence of the clock signal of frequency synthesizer and clock driver; Needing in the digital communicating field can be widely used in the equipment of clock synchronization, can improve the stability and the accuracy of professional transmission efficiently.
Usually, phase discriminator need be sampled to the simulation phase demodulation value behind the phase demodulation, and the digital phase demodulation value filtering that sampling is obtained; The voltage signal that obtains simulating according to filtered digital phase demodulation value; Preferably, as shown in Figure 2, the clock synchronization apparatus in the present embodiment also comprises:
Frequency multiplier is connected between clock driver and the phase discriminator, the clock signal f of clock driver output is carried out frequency multiplication after, obtain clock signal nf, and clock signal nf be input to phase discriminator;
Phase discriminator adopts the frequency of doubled clock nf that the phase demodulation value that obtains is sampled;
Behind the digital phase demodulation value LPF that loop filter obtains sampling, convert the voltage signal of simulation into and be input to voltage controlled oscillator through said digital to analog converter.
Frequency multiplier is used to realize the N frequency multiplication; N uses clock signal nf to the sampling of phase demodulation value, because this signal frequency is high more than or equal to 1; So sampling precision is high; Again since this signal by the clock signal of the final output of clock driver as a reference frequency multiplication form, so in sampling, also the frequency change value of system's output is quantized in the phase demodulation value simultaneously.On Mathematical Modeling, analyze, just be equivalent to two phase-locked loop cascades, improved the anti-interference of phase-locked loop systems.
Further, phase discriminator after each clock cycle T finishes, is exported the phase demodulation interrupt signal according to the clock cycle T of reference clock signal, and exports the digital phase demodulation value that sampling obtains in this clock cycle T; After loop filter is received the phase demodulation interrupt signal, read the digital phase demodulation value of phase discriminator output again and carry out LPF.Thereby guarantee that behind the phase demodulation value stabilization, phase discriminator is exported identified result again, guarantee identified result that voltage controlled oscillator reads accurately.
Be used for the clock signal of clock driver output is carried out the frequency divider of frequency division in the present embodiment; Can use FPGA (Field Programmable Gate Array; Field programmable gate array) or CPLD (Complex Programmable Logic Device; CPLD) realizes, also can use special chip to realize.Frequency divider is used to realize 1/N ' frequency division, and N ' is more than or equal to 1.And the frequency of the clock signal f1 that behind the frequency divider frequency division, obtains is identical with the frequency of reference clock signal f0.
Be used for the clock signal of clock driver output is carried out the frequency multiplier of frequency multiplication in the present embodiment, can use FPGA or CPLD to realize, also can use special chip to realize.Frequency multiplier is used to realize the N frequency multiplication, and N is more than or equal to 1, and N ' and N can be the same or different in the present embodiment.
Be used in the present embodiment two-way f0 and f1 signal are carried out phase demodulation and adopt the sample frequency sampling of nf, the phase demodulation value quantizes the phase discriminator of output the most at last, preferably uses programming device to realize, like FPGA or CPLD.
Present embodiment intermediate ring road filter carries out LPF to the phase demodulation value of importing into from phase discriminator and calculates; Eliminate shake and shifted signal; Preferably use processor realization cheaply; Like processors such as single-chip microcomputer, ARM, cooperate a digital to analog converter DA again, convert digital phase demodulation value to analog voltage signal that voltage controlled oscillator needs.
Voltage controlled oscillator converts the voltage signal of input to frequency signal in the present embodiment; Index according to system is used OCXO (Oven Controlled Crystal Oscillator; Constant-temperature crystal oscillator) or TCXO (Temperature Compensate X ' tal (crystal) Oscillator; Realize that temperature compensating crystal oscillator) the crystal oscillator index of voltage controlled oscillator is selected according to the index demand of system, in communication system; If in requiring to satisfy three grades, the index request day ageing rate of crystal oscillator is superior to 1 * 10E-8.
Present embodiment medium frequency synthesizer adopts the analog phase-locked look circuit; And with the clock signal of voltage controlled oscillator output reference clock signal as phase-locked loop circuit; Particular circuit configurations is identical with common phase-locked loop circuit, can use special chip to realize, also can use discrete device to realize.
Clock driver carries out driving many in the present embodiment to the clock signal of input, can use the special clock chip for driving to realize, also can realize with FPGA or CPLD.
Preferably, present embodiment can be integrated into phase discriminator, frequency multiplier, frequency divider, clock driver in the programming device, reduces the cost of system like this, optimizes structure.
Clock synchronization apparatus in the embodiment of the invention is compared with existing clock synchronization apparatus, can make clock system under the situation that does not improve existing design cost, significantly improves the index of clock system.
The embodiment of the invention also provides a kind of clock synchronizing method based on above-mentioned clock synchronization apparatus, and is as shown in Figure 3, may further comprise the steps:
Step S301 is sent to reference clock signal f0 and clock signal f1 in the phase discriminator, and said f1 is the clock signal that the clock signal f of clock driver output obtains behind the frequency divider frequency division;
Wherein, the frequency of f1 is identical with the frequency of f0.
Step S302, clock signal f1 and the reference clock signal f0 after to frequency division carries out phase demodulation through phase discriminator, and the phase demodulation value that obtains is input to loop filter;
Preferably, the clock signal f that clock driver is exported through frequency multiplier carries out frequency multiplication, and doubled clock nf is input to said phase discriminator;
Phase discriminator uses the frequency of clock signal nf that the phase difference of f0 and f1 is sampled; Because this signal frequency is high; So sampling precision is high; Again since this signal by the clock of the final output of system as a reference frequency multiplication form, so in sampling, also the frequency change value of system's output is quantized in the phase demodulation value simultaneously.On Mathematical Modeling, analyze, just be equivalent to two phase-locked loop cascades, improved the anti-interference of phase-locked loop systems.
Preferably; After phase discriminator carries out phase demodulation and samples through the nf signal, according to the clock cycle T of reference clock signal f0, after each clock cycle T finishes; Export effective phase demodulation interrupt signal; And export the digital phase demodulation value that sampling obtains in this clock cycle T, as shown in Figure 4, the phase discriminator interrupt signal is effective when being low level.
Step S303 behind the phase demodulation value LPF of loop filter to input, obtains voltage signal and is input to voltage controlled oscillator;
As shown in Figure 5; After present embodiment intermediate ring road filter is received effective phase demodulation interrupt signal, interrupt clearly earlier, promptly notify phase discriminator that the set of effective phase demodulation interrupt signal is invalid; Be the set high level, loop filter reads the digital phase demodulation value of phase discriminator output more then; If f0 is more leading than the phase place of f1, then phase demodulation value x is being for just, if f0 than the phase lag of f1, then phase demodulation value x is for negative, wherein x is specially the sampled value number of using in this cycle after the nf sampling; Loop filter carries out LPF to the phase demodulation value that reads, and with quick deletion shake and drift, specifically adopts following mode to carry out LPF:
y(n)＝k
1x(n)+k
2x(n-1)+k
3x(n-2)+....+k
mx(n-m+1)
Wherein, y (n) is filtered digital phase demodulation value, k
1～k
mBe the filter factor of loop filter, m is the filter factor number, and x (n) is this digital phase demodulation value that reads, and x (n-j) is the preceding digital phase demodulation value that reads for j time before this clock cycle, and j is a positive integer, 0≤j≤m-1.
The filter factor of loop filter can be made amendment according to the requirement of loop parameter, and the value of general m is less than 12, and this loop filter algorithm implementation complexity is low, uses general processor just can realize.
Loop filter is input to digital to analog converter DA with result calculated, converts the phase demodulation value into voltage signal by digital to analog converter, and voltage controlled oscillator is preserved and be input to this voltage signal as the voltage-controlled value of voltage controlled oscillator.
Step S304, voltage controlled oscillator is according to the clock signal of the voltage signal control vibration generation of input;
Step S305, after the clock signal that vibration is produced through frequency synthesizer was carried out frequency synthesis, the clock signal that obtains setpoint frequency was input to clock driver;
Step S306 is by the clock signal f of clock driver driving and generating needs, simultaneously; The two-way clock signal f of the output of clock driver delivers to frequency divider and frequency multiplier respectively, and frequency multiplier carries out frequency multiplication with the clock signal f of input, and doubled clock nf is sent in the phase discriminator; Meanwhile, frequency divider carries out frequency division to the clock signal f of input, and the clock signal f1 behind the frequency division is sent in the phase discriminator; Return execution in step S301, two-way f0 and f1 are carried out phase demodulation, so circulation by phase discriminator.
Clock synchronization apparatus that the embodiment of the invention provides and method have following advantage:
1) can guarantee that clock system can reliablely and stablely work, precision is high, can be applied in the various occasions that need high precision synchronous;
2) structure is flexible, can be according to concrete needs adjustment design, control system cost;
3) controlled step is succinct, has guaranteed that like this circuit is efficient and amount of calculation is little, just can realize with processor cheaply;
4) adopt the programmable logic device design, can realize multiple combination.Design is flexible and changeable, and adaptability is strong;
5) be easy to control the phase place of exporting clock, improve systematic function.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (10)
1. a clock synchronization apparatus is characterized in that, comprises the phase discriminator, loop filter, voltage controlled oscillator, frequency synthesizer and the clock driver that connect successively, wherein,
The clock signal of said clock driver output feeds back to the input of phase discriminator behind the frequency divider frequency division;
Clock signal and the reference clock signal of said phase discriminator after to frequency division carries out phase demodulation, and the phase demodulation value that obtains is input to loop filter;
Behind the phase demodulation value LPF of said loop filter to input, obtain voltage signal and be input to voltage controlled oscillator, by the clock signal of said voltage controlled oscillator according to the voltage signal control vibration generation of input;
After the clock signal that said frequency synthesizer produces vibration was carried out frequency synthesis, the clock signal that obtains setpoint frequency was input to clock driver, by the clock signal of clock driver driving and generating needs.
2. device as claimed in claim 1 is characterized in that, also comprises:
Frequency multiplier is connected between said clock driver and the phase discriminator, and the clock signal of said clock driver output is carried out being input to said phase discriminator after the frequency multiplication;
Said phase discriminator adopts the frequency of doubled clock that the phase demodulation value that obtains is sampled;
Behind the digital phase demodulation value LPF that said loop filter obtains sampling, convert the voltage signal of simulation into and be input to voltage controlled oscillator through said digital to analog converter.
3. device as claimed in claim 2 is characterized in that,
Said phase discriminator after each clock cycle T finishes, is exported effective phase demodulation interrupt signal according to the clock cycle T of reference clock signal, and exports the digital phase demodulation value that sampling obtains in this clock cycle T;
After said loop filter is received effective phase demodulation interrupt signal, read the digital phase demodulation value of phase discriminator output again and carry out LPF.
4. like claim 2 or 3 described devices, it is characterized in that,
Said phase discriminator, frequency multiplier, frequency divider, clock driver are integrated in the programming device.
5. like the arbitrary described device of claim 1～3, it is characterized in that,
Said frequency synthesizer adopts phase-locked loop circuit, and with the clock signal of the voltage controlled oscillator output reference clock signal as phase-locked loop circuit.
6. like the arbitrary described device of claim 1～3, it is characterized in that,
Said voltage controlled oscillator uses constant-temperature crystal oscillator OCXO or temperature compensating crystal oscillator TCXO to realize;
Said phase discriminator, clock driver, frequency multiplier, frequency divider use on-site programmable gate array FPGA or complex programmable logic device (CPLD) to realize.
7. one kind is carried out the method for clock synchronization based on the said device of claim 1, it is characterized in that, comprising:
Reference clock signal f0 and clock signal f1 are sent in the phase discriminator, and said f1 is the clock signal that the clock signal of clock driver output obtains behind the frequency divider frequency division;
Carry out phase demodulation through the clock signal and the reference clock signal of phase discriminator after, the phase demodulation value that obtains is input to loop filter frequency division;
Behind the phase demodulation value LPF of loop filter, obtain voltage signal and be input to voltage controlled oscillator, by the clock signal of said voltage controlled oscillator according to the voltage signal control vibration generation of input to input;
After the clock signal that vibration is produced through frequency synthesizer was carried out frequency synthesis, the clock signal that obtains setpoint frequency was input to clock driver, the clock signal that is needed by the clock driver driving and generating.
8. method as claimed in claim 7 is characterized in that, further comprises:
Through frequency multiplier the clock signal of said clock driver output is carried out frequency multiplication, doubled clock is input to said phase discriminator;
After said phase discriminator carries out phase demodulation, adopt the frequency of doubled clock that the phase demodulation value that obtains is sampled;
Behind the digital phase demodulation value LPF that said loop filter obtains sampling, convert the voltage signal of simulation into and be input to voltage controlled oscillator through said digital to analog converter.
9. method as claimed in claim 7 is characterized in that,
After said phase discriminator carries out phase demodulation,, after each clock cycle T finishes, export effective phase demodulation interrupt signal, and export the digital phase demodulation value that sampling obtains in this clock cycle T according to the clock cycle T of reference clock signal;
After said loop filter is received effective phase demodulation interrupt signal, read the digital phase demodulation value of phase discriminator output again and carry out LPF.
10. method as claimed in claim 9 is characterized in that, loop filter reads the digital phase demodulation value of phase discriminator output and carries out LPF, specifically adopts following mode:
y(n)＝k
1x(n)+k
2x(n-1)+k
3x(n-2)+....+k
mx(n-m+1)
Wherein, k
1～k
mBe the filter factor of loop filter, m is the filter factor number, and x (n) is this digital phase demodulation value that reads, and x (n-j) is the preceding digital phase demodulation value that reads for j time, and j is a positive integer, 0≤j≤m-1.
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