CN101321051A - Clock synchronization apparatus and method for radio frequency remote unit - Google Patents

Abstract

The invention provides a clock synchronization device of a radio frequency zoom out unit, comprising an optical module, an SerDes, an FPGA, a PFD, wherein the clock synchronization device of the radio frequency zoom out unit also comprises a digital loop filter, a direct digital frequency synthesizer (DDS), a DAC, an analog filter, a clock dispenser. The optical module is connected with one end of the SerDes, the PFD, the digital loop filter, the DDS, the DAC, the analog filter and the clock dispenser. The output end of the analog filter is accessed with the input end of the PFD, and the other end of the clock dispenser is respectively connected with the SerDes, the FPGA and the radio frequency circuit of the receiver and transmitter, the ADC and the DAC integrated in the adio frequency zoom out unit. The device adopts the whole digital phase locked loop, with low cost, overcomes the drawback of the aggravating performance after aging, wherein the system has high reliability, which provides the high accuracy clock system, and effectively eliminates the jitter of the recovery clock.

Description

The clock synchronization apparatus of Remote Radio Unit and method thereof

Technical field

The present invention relates to the Clock Synchronization Technology in Optical Fiber Transmission field, be specifically related to the clock synchronization apparatus and the method thereof of Remote Radio Unit.

Background technology

Remote Radio Unit extensively adopts in mobile communication system.Adopt Remote Radio Unit can solve problems such as machine room addressing difficulty and minimizing feeder loss, improve the efficient of system.And Clock Synchronization Technology is the key technology of Remote Radio Unit.

The transceiver that analog to digital converter (ADC), digital to analog converter (DAC) and radio frequency (RF) circuit constitute is integrated in the Remote Radio Unit, and the work clock of transceiver influence the receiving sensitivity of system and launches index such as modulation accuracy.Remote Radio Unit by optical fiber from the base station or the upper level Remote Radio Unit carry out exchanges data, bunchiness device/the deserializer (SerDes) of fiber data interface needs the tranmitting data register of very little shake, reliable to guarantee data transmit-receive, so the degree of stability of clock influences the stability of a system greatly, must obtain high accuracy clock.

Present clock synchronization mainly is by adopting the gps satellite synchronised clock or realizing from the method for optical fiber recovered clock.

Adopt the gps satellite synchronised clock that following shortcoming is arranged:

(1) cost height needs the GPS receiver of installation expensive.

(2) gps antenna reconnaissance difficulty, when RRU is positioned at indoorly when carrying out indoor covering, the signal of satellite is not fine, causes gps antenna reconnaissance difficulty, the flexible use of Remote Radio Unit is limited.

The method that the tradition far-drawing system is mainly taked from the optical fiber recovered clock realizes by analog phase-locked look (PLL) and voltage controlled oscillator (VCXO).In the time of the Remote Radio Unit multi-stage cascade, the clock recovered near-end rapid deterioration of making an uproar mutually.As shown in Figure 1, realize that by PLL and VCXO optical module is connected with PLL, analog loop filter, VCXO successively in traditional far-drawing system of clock recovery, the output of VCXO be connected with PLL, SerDes, field programmable gate array logic device FPGA respectively simultaneously form.Because the analog phase-locked look loop bandwidth is than broad, so the clock recovered shake is bigger, is difficult to satisfy the requirement of Remote Radio Unit.

Technical scheme such as Chinese patent publication number CN1867119 are also arranged, open day on November 22nd, 2006, name is called in " clock recovery method and device in a kind of RF far-end module " said, adopts digital phase-locked loop and constant temperature VCXO (OCXO) to carry out the phase-locked method that obtains reasonable clock.Digital phase-locked loop can obtain very narrow loop bandwidth, can hang down below the 1Hz, so clock is improved, and can satisfy system's needs.But this method need be used constant temperature VCXO (OCXO), cost height.The frequency stability of OCXO is high more simultaneously, and price is high more.

Therefore present clock synchronization scheme is difficult to obtain good cost performance, and clock accuracy is not high enough, has reduced competitiveness of product.

Summary of the invention

The objective of the invention is to overcome the shortcoming of prior art, the clock synchronization apparatus of a kind of cost performance height, loop bandwidth is narrow, clock jitter is low, clock accuracy is high Remote Radio Unit is provided.

Another object of the present invention is to provide a kind of method that realizes clock synchronization by the clock synchronization apparatus of above-mentioned Remote Radio Unit.

Purpose of the present invention is achieved through the following technical solutions: the clock synchronization apparatus of Remote Radio Unit comprises optical module, SerDes, FPGA, PFD, the clock synchronization apparatus of described Remote Radio Unit also comprises digital loop filters, Direct Digital Frequency Synthesizers (DDS), DAC, analog filter, the clock distributor, optical module successively with SerDes, PFD, digital loop filters, DDS, DAC, analog filter, the clock distributor is connected, the output of analog filter is connected with the input of PFD simultaneously, the clock distributor simultaneously respectively with SerDes, the radio frequency of integrated transceiver (RF) circuit in FPGA and the Remote Radio Unit, ADC, DAC is connected.

Analog filter in the clock synchronization apparatus of described Remote Radio Unit is low pass filter or band pass filter.

Utilize the method for the clock synchronization apparatus realization clock synchronization of above-mentioned Remote Radio Unit, comprise the steps:

(1) upper level RRU or signal of base station are transferred to SerDes by optical module;

(2) SerDes recovers the clock signal that has very big shake according to the signal of optical module;

(3) the SerDes clock signal recovering out inserts PFD as the reference clock signal of PFD;

(4) output signal of PFD inserts digital loop filters, carries out the frequency control word that loop filtering produces control DDS then;

(5) output signal of DDS access DAC carries out digital-to-analogue conversion;

(6) output signal of DAC inserts low pass filter to suppress harmonic wave and mirror image, and filtered clock signal inserts PFD, clock distributor respectively;

(7) output signal of clock distributor inserts radio frequency (RF) circuit, ADC, the DAC of transceiver integrated in SerDes, FPGA and the Remote Radio Unit respectively as work clock.

The present invention has following advantage and effect with respect to prior art:

(1) whole system does not adopt expensive OCXO and VCXO, has reduced cost significantly;

(2) adopt all-digital phase-locked loop to realize, overcome the shortcoming that the analog phase-locked look aged properties worsens;

(3) adopt DDS to substitute VCXO and OCXO, make that the reliability of system is higher;

(4) DDS make things convenient for rate very high, the high accuracy clock system can be provided;

(5) DPLL digital phase-locked loop is compared with simulaed phase locked loop, and the DPLL digital phase-locked loop bandwidth is narrower, can effectively eliminate the shake of recovered clock;

(6) frequency resolution of DDS can reach 10^-4Hz, can satisfy the requirement of the 0.05ppm of Remote Radio Unit fully.

Description of drawings

Fig. 1 is the clock recovery circuitry block diagram of traditional far-drawing system.

Fig. 2 is the circuit block diagram of the clock synchronization apparatus of Remote Radio Unit of the present invention.

Embodiment

The present invention is described in further detail below in conjunction with embodiment and accompanying drawing, but embodiments of the present invention are not limited thereto.

Embodiment

Fig. 2 shows concrete structure of the present invention, as seen from Figure 2, the clock synchronization apparatus of this Remote Radio Unit is connected with SerDes, PFD, digital loop filters, DDS, DAC, analog filter, clock distributor one end successively by optical module, the output of analog filter inserts the input of PFD, the clock distributor other end be connected with SerDes, FPGA respectively form.

The course of work of the clock synchronization apparatus of this Remote Radio Unit is such:

Upper level RRU or signal of base station are transferred to RRU by FPGA, SerDes and optical module, and wherein the reference clock of the work clock CLK1 of FPGA and SerDes and system is synchronous.

The SerDes of RRU (202) extracts recovered clock signal CLK2 according to the serial signal of optical module (201) from serial data stream.Recovered clock CLK2 and CLK1 also are synchronous, but shake can not must go to tremble processing by subsequent conditioning circuit directly as the reference clock of RRU greatly.

Send into PFD (203) from the clock signal that SerDes recovers out, the output signal of PFD is sent into digital loop filters (204), digital loop filters (204) produces frequency control word control DDS (205), the output signal of DDS (205) is sent into DAC (206) and is produced the simulated clock simulation clock signal, the mirror image and the harmonic wave of analog filter (207) filtering clock signal, filtered clock CLK7 sends into PFD (203) and clock distributor (208) respectively.The filtered clock CLK3 of clock distributor (208) distribution inserts SerDes, CLK4 and inserts FPGA, and CLK5 and CLK6 insert radio frequency (RF) circuit, ADC, the DAC of transceiver integrated in the Remote Radio Unit respectively.In the time of loop-locking, CLK7 and all synchronous with clock CLK1 by clock CLK3, CLK4, CLK5, the CLK6 etc. of CLK7 distribution generation.

Because the loop bandwidth of digital phase-locked loop can be lower than 1Hz, therefore can obtain low jitter, high accuracy clock.

As mentioned above; just can realize the present invention preferably; the foregoing description is a preferred implementation of the present invention; but embodiments of the present invention are not restricted to the described embodiments; other any do not deviate from change, the modification done under spirit of the present invention and the principle, substitutes, combination, simplify; all should be the substitute mode of equivalence, be included within protection scope of the present invention.

Claims (4)

1, the clock synchronization apparatus of Remote Radio Unit, comprise optical module, SerDes, FPGA, PFD, it is characterized in that: the clock synchronization apparatus of described Remote Radio Unit also comprises digital loop filters, DDS, DAC, analog filter, the clock distributor, optical module successively with SerDes, PFD, digital loop filters, DDS, DAC, analog filter, clock distributor one end is connected, the output of analog filter inserts the input of PFD, the clock distributor other end respectively with SerDes, the RF circuit of integrated transceiver in FPGA and the Remote Radio Unit, ADC, DAC is connected.

2, the clock synchronization apparatus of Remote Radio Unit according to claim 1 is characterized in that: the analog filter in the clock synchronization apparatus of described Remote Radio Unit is a low pass filter.

3, the clock synchronization apparatus of Remote Radio Unit according to claim 1 is characterized in that: the analog filter in the clock synchronization apparatus of described Remote Radio Unit is a band pass filter.

4, utilize the method for the clock synchronization apparatus realization clock synchronization of each described Remote Radio Unit of claim 1～3, comprise the steps:

(1) upper level RRU or signal of base station are transferred to SerDes by optical module;

(2) SerDes recovers the clock signal that has very big shake according to the signal of optical module;

(3) the SerDes clock signal recovering out inserts PFD as the reference clock signal of PFD;

(4) output signal of PFD inserts digital loop filters, carries out the frequency control word that loop filtering produces control DDS then;

(5) output signal of DDS access DAC carries out digital-to-analogue conversion;

(6) output signal of DAC inserts low pass filter to suppress harmonic wave and mirror image, and filtered clock signal inserts PFD, clock distributor respectively;

(7) output signal of clock distributor inserts RF circuit, ADC, the DAC of transceiver integrated in SerDes, FPGA and the Remote Radio Unit respectively as work clock.

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