CN106413077A - Clock synchronization circuit of point-to-multipoint microwave communication system, and operation method and applications thereof - Google Patents
Clock synchronization circuit of point-to-multipoint microwave communication system, and operation method and applications thereof Download PDFInfo
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- CN106413077A CN106413077A CN201610748110.5A CN201610748110A CN106413077A CN 106413077 A CN106413077 A CN 106413077A CN 201610748110 A CN201610748110 A CN 201610748110A CN 106413077 A CN106413077 A CN 106413077A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
- H04W56/001—Synchronization between nodes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0652—Synchronisation among time division multiple access [TDMA] nodes, e.g. time triggered protocol [TTP]
- H04J3/0655—Synchronisation among time division multiple access [TDMA] nodes, e.g. time triggered protocol [TTP] using timestamps
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- Computer Networks & Wireless Communication (AREA)
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- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention relates to a clock synchronization circuit of a point-to-multipoint microwave communication system, and an operation method and applications thereof. The circuit comprises an outdoor unit, an indoor unit and a Serdes interface circuit, wherein the outdoor unit is connected with the indoor unit via the Serdes interface circuit, and data interaction and clock synchronization between the outdoor unit and the indoor unit are achieved via the Serdes interface circuit. The outdoor unit comprises a radio frequency transceiving module, a clock crystal oscillator and a modulation-demodulation FPGA. The indoor unit comprises a link layer FPGA, a DAC circuit, a RC filter circuit and a voltage-controlled crystal oscillator. According to the circuit provided by the invention, correct transceiving control of the indoor unit on communication data packets of the outdoor unit is achieved by sending time slot control packets in a time count value manner, reference transceiving time of all communication frames is at the outdoor unit, and the problems about time delay and time delay variation caused by a connection medium between the indoor and outdoor units and a transmission length are solved. The clock synchronization circuit is high in transmission efficiency, low in implementation cost, universal and reliable.
Description
Technical field
The present invention relates to a kind of point-to-multipoint microwave communication system clock synchronizing circuit and its operation method and application, belong to
Wireless microwave communication technical field.
Background technology
Point-to-multipoint microwave communication system is in horizon range or repeated switching, is entered with microwave band electromagnetic wave for medium
A kind of advanced communication system of the information transfers such as row voice, data, image, mainly by groups such as central station, Yong Huzhan, relay stations
Become.Point-to-multipoint microwave communication system has that capacity is big, quality is good, networking flexibility the features such as, be a kind of weight of national communication net
Want means of communication, be also applied for the various private wire network such as electric power, oil field, mine, harbour.
The multi-access mode that point-to-multipoint microwave communication system adopts has FDMA, CDMA, TDMA etc., based on frequency resource, leads to
Believe the factors such as capacity, system, adopt TDMA multi-access mode more.Duplex mode has FDD and TDD.
In FDD system, because downlink information is to continuously transmit, when clock synchronous characteristic information can obtain to maintain in real time
Clock is synchronous.And in TDD system, downlink data is burst mode, clock synchronous characteristic information is simultaneously discontinuous, if system is using high-precision
Degree clock source, it is possible to achieve system communicates, but high cost.How to design one kind and be applied to TDD mode point-to-multipoint microwave
Inexpensive, general, the reliable clock synchronization circuit of communication system becomes technical problem urgently to be resolved hurrily.
If point-to-multipoint microwave communication system will ensure that communicate is normally carried out, need each user station that central station is kept
Clock synchronization, frame synchronization and net synchronous condition, and clock is synchronously the primary essential condition of system work.Conventional clock is synchronous
Using method be mostly demodulation module tracking lock central station clock information by outdoor unit, then after synchronization when
Clock is sent to indoor unit link layer, and link layer carries out the transmitting-receiving work of communication frame according to this synchronised clock.The shortcoming of the method
It is, because indoor and outdoor connection medium and conveying length have very big variability, to lead to the data transmit-receive time delay of indoor and outdoor consistent
Property bad, and this time delay value can be counted aerial time delay, reduces efficiency of transmission, increased indoor unit frame transmitting-receiving control difficult
Degree.
Content of the invention
For the point-to-multipoint microwave communication system clock synchronizing circuit present situation based on TDD mode, the invention provides one
Plant inexpensive, general, reliable clock synchronization circuit.This circuit core thought is using low cost in station data link layer
VCXO, burst frame originating point information is captured by FPGA platform, and detects the time deviation of frame originating point information, through data processing
Produce VCXO adjusted value, by real-time adjustment VCXO frequency it is ensured that system clock is synchronous.This design circuit cost
Low, circuit is simple, highly versatile and portability are good.
Present invention also offers the operation method of foregoing circuit and application.
Term is explained
1st, FPGA (Field-Programmable Gate Array), i.e. field programmable gate array, it be PAL,
The product developing further on the basis of the programming devices such as GAL, CPLD.It is as in special IC (ASIC) field
A kind of semi-custom circuit and occur, both solved the deficiency of custom circuit, overcome original programming device gate circuit again
The limited shortcoming of number.
2nd, iir digital filter, i.e. " recursion filter ".Recursion filter, as the term suggests, there is feedback.
The technical scheme is that：
A kind of point-to-multipoint microwave communication system clock synchronizing circuit, including outdoor unit, indoor unit, Serdes interface
Circuit, described outdoor unit connects described indoor unit by Serdes interface circuit, realizes institute by Serdes interface circuit
State outdoor unit synchronous with described indoor unit data interaction and clock.
Using realizing outdoor unit, indoor unit data transfer the features such as the high speed of Serdes interface circuit, clock recovery
Synchronous with clock.
Described outdoor unit and described indoor unit data interaction and clock synchronization, institute are realized by indoor and outdoor interface protocol
State frame head part, the data division of standard ethernet frame and the standard ethernet that indoor and outdoor interface protocol includes standard ethernet frame
The Frame Check Sequence part of frame, the frame header of described standard ethernet frame is divided including lead code, is defined symbol, destination address, source ground
Location, length, the data division of described standard ethernet frame includes indoor and outdoor control data and time slot data, described standard ethernet
The Frame Check Sequence part of frame includes frame check.
According to currently preferred, described outdoor unit includes radio-frequency (RF) receiving and transmission module, clock crystal oscillator, modulation /demodulation FPGA,
Described indoor unit includes link layer FPGA, DAC-circuit, RC filter circuit and VCXO；Described Serdes interface circuit bag
Include the Serdes interface positioned at described outdoor unit and the 2nd Serdes interface being located at described indoor unit；
Described modulation /demodulation FPGA connects a described Serdes interface；Described 2nd Serdes interface connects described link
Layer FPGA；Described radio-frequency (RF) receiving and transmission module, described clock crystal oscillator connect described modulation /demodulation FPGA respectively, described link layer FPGA,
Annular connects successively for described DAC-circuit, described RC filter circuit and described VCXO；
Described radio-frequency (RF) receiving and transmission module is used for the wireless receiving and dispatching of communication data；
Described clock crystal oscillator is used for providing reference clock for a described Serdes interface；
The sequence control packet that described modulation /demodulation FPGA sends according to described link layer FPGA, during search is derived from real time
The frame head data of center station, to be captured record time counting value when current frame head reaches to after frame head data, and be packaged into
Standard ethernet frame structure format is sent to described link layer FPGA；
Time count value when described link layer FPGA reaches according to the current frame head receiving, is reached constantly with previous frame head
Between count value carry out deviation information process, obtain deviation data, deliver to described DAC-circuit, pressure is converted to by described DAC-circuit
Control analogue signal；
Described voltage-controlled analogue signal, after described RC filter circuit, sends to described VCXO, controls its output frequency
Rate is progressively synchronized to central station clock.
Outdoor unit, indoor unit are mainly with FPGA for core processing platform.Using fpga chip there is abundant I/O
Resource, logical resource, SRAM resource, PLL, DSP and multiple I/O level standard.
First Serdes interface and the 2nd Serdes interface all using standard ethernet frame structure, by using time counting
Value mode sending time slots control data bag is realized indoor unit and the accurate transmitting-receiving of outdoor unit communication data packet is controlled, Suo Youtong
The transmitting-receiving reference instant of letter frame is all in outdoor unit.
According to currently preferred, described RC filter circuit includes resistance R1, electric capacity C1, and one end of described resistance R1 connects
Described DAC-circuit, described VCXO connects the other end of described resistance R1 and one end of described electric capacity C1 respectively.RC filtered electrical
Road is used for filtering the interference component on voltage control signal.
According to currently preferred, the resistance value of resistance R1 is 1K Ω, and the capacitance of described electric capacity C1 is 0.1 μ F.
According to currently preferred, the voltage-controlled span of control of described VCXO is not less than ± 50ppm.Meet communication system
Clock interface frequency range requires.
According to currently preferred, described link layer FPGA includes PLL module and iir digital filter, described PLL module
For producing clock frequency needed for link layer FPGA inside, described iir digital filter is used for filtering air transmission shake sum
Word sampling dithering.
According to currently preferred, the formula such as formula of described iir digital filter calculating present clock deviation data x (n)
(I) shown in：
Y (n)=(1- α) * y (n-1)+α * x (n) (I)
In formula I, time count value when y (n) refers to that current frame head reaches, time when y (n-1) refers to that previous frame head reaches
Count value, α is coefficient, and the span of α is 0.1-0.4.
The operation method of above-mentioned clock synchronization circuit, concrete steps include：
(1) described link layer FPGA passes through a Serdes interface and the 2nd Serdes interface sending time slots control data bag
To described modulation /demodulation FPGA；
(2) the sequence control packet being sent according to described link layer FPGA, described modulation /demodulation FPGA searches in real time
From after the frame head data of central station, the starting position to system frame information to be captured, record time counting when current frame head reaches
It is worth, and is packaged into standard ethernet frame structure format and be sent to described link layer FPGA；
(3) time count value when described link layer FPGA reaches according to the current frame head receiving, is reached with previous frame head
When time count value carry out deviation information process, obtain deviation data, be sent to described DAC-circuit, turned by described DAC-circuit
It is changed to voltage-controlled analogue signal；
(4) described voltage-controlled analogue signal, after described RC filter circuit, sends to described VCXO, controls its output
Frequency is progressively synchronized to central station clock.
The application of above-mentioned clock synchronization circuit is it is adaptable to the clock being not less than the different system frame frequency of 125Hz is synchronous.
Beneficial effects of the present invention are：
It is core processing platform that this clock synchronization circuit adopts FPGA, realizes indoor and outdoor data by Serdes interface circuit
Interaction and clock are synchronous；In combination with efficient indoor and outdoor interface protocol, by using time counting value mode sending time slots control
Packet processed is realized indoor unit and the accurate transmitting-receiving of outdoor unit communication data packet is controlled, during the transmitting-receiving benchmark of all communication frames
Carve all in outdoor unit, solve the problems, such as the time delay because indoor and outdoor connects medium and conveying length causes and Delay Variation.Should
Clock synchronization circuit efficiency of transmission is high, cost of implementation is low, general reliability.
Brief description
Fig. 1 is the connection block diagram of clock synchronization circuit of the present invention；
Specific embodiment
With reference to Figure of description and embodiment, the present invention is further qualified, but not limited to this.
Embodiment 1
A kind of point-to-multipoint microwave communication system clock synchronizing circuit, including outdoor unit, indoor unit, Serdes interface
Circuit, described outdoor unit connects described indoor unit by Serdes interface circuit, realizes institute by Serdes interface circuit
State outdoor unit synchronous with described indoor unit data interaction and clock.
Using realizing outdoor unit, indoor unit data transfer the features such as the high speed of Serdes interface circuit, clock recovery
Synchronous with clock.
Described outdoor unit and described indoor unit data interaction and clock synchronization, institute are realized by indoor and outdoor interface protocol
State frame head part, the data division of standard ethernet frame and the standard ethernet that indoor and outdoor interface protocol includes standard ethernet frame
The Frame Check Sequence part of frame, the frame header of described standard ethernet frame is divided including lead code, is defined symbol, destination address, source ground
Location, length, the data division of described standard ethernet frame includes indoor and outdoor control data and time slot data, described standard ethernet
The Frame Check Sequence part of frame includes frame check.As shown in table 1：
Table 1
Described outdoor unit includes radio-frequency (RF) receiving and transmission module, clock crystal oscillator, modulation /demodulation FPGA, and described indoor unit includes chain
Road floor FPGA, DAC-circuit, RC filter circuit and VCXO；Described Serdes interface circuit is included positioned at described outdoor unit
A Serdes interface and be located at described indoor unit the 2nd Serdes interface；
Described modulation /demodulation FPGA connects a described Serdes interface；Described 2nd Serdes interface connects described link
Layer FPGA；Described radio-frequency (RF) receiving and transmission module, described clock crystal oscillator connect described modulation /demodulation FPGA respectively, described link layer FPGA,
Annular connects successively for described DAC-circuit, described RC filter circuit and described VCXO；As shown in Figure 1.
Described radio-frequency (RF) receiving and transmission module is used for the wireless receiving and dispatching of communication data；
Described clock crystal oscillator is used for providing reference clock for a described Serdes interface；
The sequence control packet that described modulation /demodulation FPGA sends according to described link layer FPGA, during search is derived from real time
The frame head data of center station, to be captured record time counting value when current frame head reaches to after frame head data, and be packaged into
Standard ethernet frame structure format is sent to described link layer FPGA；
Time count value when described link layer FPGA reaches according to the current frame head receiving, is reached constantly with previous frame head
Between count value carry out deviation information process, obtain deviation data, deliver to described DAC-circuit, pressure is converted to by described DAC-circuit
Control analogue signal；
Described voltage-controlled analogue signal, after described RC filter circuit, sends to described VCXO, controls its output frequency
Rate is progressively synchronized to central station clock.
Outdoor unit, indoor unit are mainly with FPGA for core processing platform.Using fpga chip there is abundant I/O
Resource, logical resource, SRAM resource, PLL, DSP and multiple I/O level standard.
First Serdes interface and the 2nd Serdes interface all using standard ethernet frame structure, by using time counting
Value mode sending time slots control data bag is realized indoor unit and the accurate transmitting-receiving of outdoor unit communication data packet is controlled, Suo Youtong
The transmitting-receiving reference instant of letter frame is all in outdoor unit.
Described RC filter circuit includes resistance R1, electric capacity C1, and one end of described resistance R1 connects described DAC-circuit, described
VCXO connects the other end of described resistance R1 and one end of described electric capacity C1 respectively.RC filter circuit is used for filtering voltage-controlled letter
Interference component on number.
The resistance value of resistance R1 is 1K Ω, and the capacitance of described electric capacity C1 is 0.1 μ F.
The voltage-controlled span of control of described VCXO is not less than ± 50ppm.Meet communication system clock interface frequency range
Require.
Described link layer FPGA includes PLL module and iir digital filter, and described PLL module is used for producing link layer
Clock frequency needed for FPGA inside, described iir digital filter is used for filtering air transmission shake and digital sampling dithering.
Described iir digital filter calculates the formula of present clock deviation data x (n) as shown in formula I：
Y (n)=(1- α) * y (n-1)+α * x (n) (I)
In formula I, time count value when y (n) refers to that current frame head reaches, time when y (n-1) refers to that previous frame head reaches
Count value, α is coefficient, and the span of α is 0.1-0.4.
Embodiment 2
The operation method of the clock synchronization circuit described in embodiment 1, concrete steps include：
(1) described link layer FPGA passes through a Serdes interface and the 2nd Serdes interface sending time slots receive and control number
According to bag to described modulation /demodulation FPGA；
(2) the time slot receive control data bag being sent according to described link layer FPGA, described modulation /demodulation FPGA searches in real time
Rope is derived from the frame head data of central station, to be captured record time counting value when current frame head reaches to after frame head data, and
It is packaged into and described link layer FPGA is sent to standard ethernet frame structure format；
(3) time count value when described link layer FPGA reaches according to the current frame head receiving, is reached with previous frame head
When time count value carry out deviation information process, obtain deviation data, be sent to described DAC-circuit, turned by described DAC-circuit
It is changed to voltage-controlled analogue signal；
(4) described voltage-controlled analogue signal, after described RC filter circuit, sends to described VCXO, controls its output
Frequency is progressively synchronized to central station clock.
Embodiment 3
The application of the clock synchronization circuit described in embodiment 1 is it is adaptable to be not less than the clock of the different system frame frequency of 125Hz
Synchronous.
Claims (9)
1. a kind of point-to-multipoint microwave communication system clock synchronizing circuit it is characterised in that include outdoor unit, indoor unit,
Serdes interface circuit, described outdoor unit connects described indoor unit by Serdes interface circuit, by Serdes interface
Outdoor unit described in circuit realiration is synchronous with described indoor unit data interaction and clock.
2. a kind of point-to-multipoint microwave communication system clock synchronizing circuit according to claim 1 is it is characterised in that described
Outdoor unit includes radio-frequency (RF) receiving and transmission module, clock crystal oscillator, modulation /demodulation FPGA, and described indoor unit includes link layer FPGA, DAC
Circuit, RC filter circuit and VCXO；Described Serdes interface circuit includes the Serdes positioned at described outdoor unit
Interface and the 2nd Serdes interface being located at described indoor unit；
Described modulation /demodulation FPGA connects a described Serdes interface；Described 2nd Serdes interface connects described link layer
FPGA；Described radio-frequency (RF) receiving and transmission module, described clock crystal oscillator connect described modulation /demodulation FPGA, described link layer FPGA, institute respectively
Annular connects successively to state DAC-circuit, described RC filter circuit and described VCXO；
Described radio-frequency (RF) receiving and transmission module is used for the wireless receiving and dispatching of communication data；
Described clock crystal oscillator is used for providing reference clock for a described Serdes interface；
The sequence control packet that described modulation /demodulation FPGA sends according to described link layer FPGA, search in real time is derived from central station
Frame head data, to be captured to after frame head data, record time counting value when current frame head reaches, and be packaged into standard
Ethernet frame architecture is sent to described link layer FPGA；
Time count value when described link layer FPGA reaches according to the current frame head receiving, time meter when reaching with previous frame head
Numerical value carries out deviation information process, obtains deviation data, delivers to described DAC-circuit, is converted to voltage-controlled mould by described DAC-circuit
Intend signal；
Described voltage-controlled analogue signal, after described RC filter circuit, sends to described VCXO, control its output frequency by
Step is synchronized to central station clock.
3. a kind of point-to-multipoint microwave communication system clock synchronizing circuit according to claim 2 is it is characterised in that described
RC filter circuit includes resistance R1, electric capacity C1, and one end of described resistance R1 connects described DAC-circuit, and described VCXO is respectively
Connect the other end of described resistance R1 and one end of described electric capacity C1.
4. a kind of point-to-multipoint microwave communication system clock synchronizing circuit according to claim 3 is it is characterised in that resistance
The resistance value of R1 is 1K Ω, and the capacitance of described electric capacity C1 is 0.1 μ F.
5. a kind of point-to-multipoint microwave communication system clock synchronizing circuit according to claim 2 is it is characterised in that described
The voltage-controlled span of control of VCXO is not less than ± 50ppm.
6. a kind of point-to-multipoint microwave communication system clock synchronizing circuit according to claim 2 is it is characterised in that described
Link layer FPGA includes PLL module and iir digital filter, and described PLL module is used for producing the internal institute of described link layer FPGA
Need clock frequency, described iir digital filter is used for filtering air transmission shake and digital sampling dithering.
7. a kind of point-to-multipoint microwave communication system clock synchronizing circuit according to claim 6 is it is characterised in that described
Iir digital filter calculates the formula of present clock deviation data x (n) as shown in formula I：
Y (n)=(1- α) * y (n-1)+α * x (n) (I)
In formula I, time count value when y (n) refers to that current frame head reaches, time counting when y (n-1) refers to that previous frame head reaches
Value, α is coefficient, and the span of α is 0.1-0.4.
8. the operation method of the arbitrary described clock synchronization circuit of claim 2-7 is it is characterised in that concrete steps include：
(1) described link layer FPGA passes through a Serdes interface and the 2nd Serdes interface sending time slots receive control data bag
To described modulation /demodulation FPGA；
(2) the time slot receive control data bag being sent according to described link layer FPGA, described modulation /demodulation FPGA searches in real time
From the frame head data of central station, to be captured to after frame head data, record time counting value when current frame head reaches, and pack
Become to be sent to described link layer FPGA with standard ethernet frame structure format；
(3) time count value when described link layer FPGA reaches according to the current frame head receiving, is reached constantly with previous frame head
Between count value carry out deviation information process, obtain deviation data, be sent to described DAC-circuit, be converted to by described DAC-circuit
Voltage-controlled analogue signal；
(4) described voltage-controlled analogue signal, after described RC filter circuit, sends to described VCXO, controls its output frequency
Progressively it is synchronized to central station clock.
9. the arbitrary described clock synchronization circuit of claim 1-7 application it is characterised in that being applied to not less than 125Hz's
The clock of different system frame frequency is synchronous.
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| CN201610748110.5A CN106413077B (en) | 2016-08-29 | 2016-08-29 | Clock synchronization circuit of point-to-multipoint microwave communication system, and operation method and application thereof |
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| CN106413077B (en) | 2023-09-29 |
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