CN106413077B - Clock synchronization circuit of point-to-multipoint microwave communication system, and operation method and application thereof - Google Patents
Clock synchronization circuit of point-to-multipoint microwave communication system, and operation method and application thereof Download PDFInfo
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- CN106413077B CN106413077B CN201610748110.5A CN201610748110A CN106413077B CN 106413077 B CN106413077 B CN 106413077B CN 201610748110 A CN201610748110 A CN 201610748110A CN 106413077 B CN106413077 B CN 106413077B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
- H04W56/001—Synchronization between nodes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0652—Synchronisation among time division multiple access [TDMA] nodes, e.g. time triggered protocol [TTP]
- H04J3/0655—Synchronisation among time division multiple access [TDMA] nodes, e.g. time triggered protocol [TTP] using timestamps
Abstract
The invention relates to a clock synchronization circuit of a point-to-multipoint microwave communication system, an operation method and an application thereof. The outdoor unit comprises a radio frequency transceiver module, a clock crystal oscillator and a modulation demodulation FPGA, and the indoor unit comprises a link layer FPGA, a DAC circuit, an RC filter circuit and a voltage-controlled crystal oscillator; the invention realizes the accurate receiving and transmitting control of the indoor unit to the outdoor unit communication data packet by transmitting the time slot control data packet in a time counting value mode, and the receiving and transmitting reference time of all communication frames is in the outdoor unit, thereby solving the problems of time delay and time delay change caused by indoor and outdoor connection media and transmission length. The clock synchronization circuit has high transmission efficiency, low realization cost and general reliability.
Description
Technical Field
The invention relates to a clock synchronization circuit of a point-to-multipoint microwave communication system, and an operation method and application thereof, and belongs to the technical field of wireless microwave communication.
Background
The point-to-multipoint microwave communication system is an advanced communication system for transmitting information such as voice, data, image and the like by taking electromagnetic waves in a microwave band as a medium in the range of visual distance or through relay switching, and mainly comprises a central station, a subscriber station, a relay station and the like. The point-to-multipoint microwave communication system has the characteristics of large capacity, good quality, flexible networking and the like, is an important communication means of a national communication network, and is also suitable for various special communication networks such as electric power, oil fields, mines, ports and the like.
The point-to-multipoint microwave communication system adopts a multiple access mode FDMA, CDMA, TDMA, and the system adopts a TDMA multiple access mode based on factors such as frequency resources, communication capacity and the like. Duplex modes include FDD and TDD.
In the FDD system, since the downlink information is continuously transmitted, the clock synchronization feature information can be acquired in real time to maintain clock synchronization. In the TDD system, the downlink data is in burst mode, the clock synchronization characteristic information is not continuous, and if the system adopts a high-precision clock source, system communication can be achieved, but the cost is too high. How to design a low-cost, universal and reliable clock synchronization circuit suitable for a TDD mode point-to-multipoint microwave communication system is a technical problem to be solved.
If the point-to-multipoint microwave communication system is to ensure the normal operation of communication, each subscriber station needs to maintain clock synchronization, frame synchronization and network synchronization conditions for the central station, and the clock synchronization is the first necessary condition for the system to work. The conventional clock synchronization method mostly tracks and locks clock information of a central station through a demodulation module of an outdoor unit, and then transmits the synchronized clock to a link layer of an indoor unit, wherein the link layer carries out receiving and transmitting work of communication frames according to the synchronized clock. The method has the defects that the consistency of the indoor and outdoor data receiving and transmitting time delay is poor due to the large variability of the indoor and outdoor connecting media and the transmission length, and the time delay value can be calculated into the air time delay, so that the transmission efficiency is reduced, and the receiving and transmitting control difficulty of indoor unit frames is increased.
Disclosure of Invention
Aiming at the current situation of a clock synchronization circuit of a point-to-multipoint microwave communication system based on a TDD mode, the invention provides a low-cost, universal and reliable clock synchronization circuit. The circuit core concept is that a low-cost voltage-controlled crystal oscillator is adopted in a data link layer of a subscriber station, burst frame header information is captured through an FPGA platform, time deviation of the frame header information is detected, a voltage-controlled crystal oscillator adjustment value is generated through data processing, and the frequency of the voltage-controlled crystal oscillator is adjusted in real time, so that the synchronization of a system clock is ensured. The design circuit has the advantages of low cost, simple circuit, strong universality and good portability.
The invention also provides an operation method and application of the circuit.
Interpretation of the terms
1. FPGA (Field-Programmable Gate Array), a Field programmable gate array, is a product of further development on the basis of programmable devices such as PAL, GAL, CPLD. The programmable device is used as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASICs), which not only solves the defect of custom circuits, but also overcomes the defect of limited gate circuits of the original programmable device.
2. IIR digital filters, i.e. "recursive filters". Recursive filters, as the name implies, have feedback.
The technical scheme of the invention is as follows:
the clock synchronization circuit of the point-to-multipoint microwave communication system comprises an outdoor unit, an indoor unit and a Serdes interface circuit, wherein the outdoor unit is connected with the indoor unit through the Serdes interface circuit, and the data interaction and clock synchronization of the outdoor unit and the indoor unit are realized through the Serdes interface circuit.
The characteristics of high speed, clock recovery and the like of the Serdes interface circuit are utilized to realize data transmission and clock synchronization of the outdoor unit and the indoor unit.
The indoor and outdoor interface protocol comprises a frame head part of a standard Ethernet frame, a data part of the standard Ethernet frame and a frame check sequence part of the standard Ethernet frame, wherein the frame head part of the standard Ethernet frame comprises a preamble, a delimiter, a destination address, a source address and a length, the data part of the standard Ethernet frame comprises indoor and outdoor control data and time slot data, and the frame check sequence part of the standard Ethernet frame comprises frame check.
According to the invention, the outdoor unit comprises a radio frequency transceiver module, a clock crystal oscillator and a modulation-demodulation FPGA, and the indoor unit comprises a link layer FPGA, a DAC circuit, an RC filter circuit and a voltage-controlled crystal oscillator; the Serdes interface circuit comprises a first Serdes interface positioned at the outdoor unit and a second Serdes interface positioned at the indoor unit;
the modem FPGA is connected with the first Serdes interface; the second Serdes interface is connected with the link layer FPGA; the radio frequency transceiver module and the clock crystal oscillator are respectively connected with the modulation-demodulation FPGA, and the link layer FPGA, the DAC circuit, the RC filter circuit and the voltage-controlled crystal oscillator are sequentially and annularly connected;
the radio frequency transceiver module is used for wireless transceiving of communication data;
the clock crystal oscillator is used for providing a reference clock for the first Serdes interface;
the modem FPGA searches frame header data from a central station in real time according to a time slot control data packet sent by the link layer FPGA, records a time count value when the current frame header arrives after the frame header data is captured, and packages the time count value into a standard Ethernet frame structure format and sends the standard Ethernet frame structure format to the link layer FPGA;
the link layer FPGA performs deviation information processing according to the received current frame head arrival time count value and the last frame head arrival time count value to obtain deviation data, and the deviation data is sent to the DAC circuit and converted into a voltage-controlled analog signal through the DAC circuit;
and the voltage-controlled analog signal is transmitted to the voltage-controlled crystal oscillator after passing through the RC filter circuit, and the output frequency of the voltage-controlled analog signal is controlled to be gradually synchronized to a central station clock.
The outdoor unit and the indoor unit mainly take an FPGA as a core processing platform. The adopted FPGA chip has rich I/O resources, logic resources, static random access memory resources, PLL, DSP and various I/O level standards.
The first Serdes interface and the second Serdes interface adopt standard Ethernet frame structures, and the indoor unit can accurately transmit and receive the communication data packet of the outdoor unit by transmitting the time slot control data packet in a time counting value mode, and the transmitting and receiving reference time of all communication frames is in the outdoor unit.
According to the invention, the RC filter circuit comprises a resistor R1 and a capacitor C1, wherein one end of the resistor R1 is connected with the DAC circuit, and the voltage-controlled crystal oscillator is respectively connected with the other end of the resistor R1 and one end of the capacitor C1. The RC filter circuit is used for filtering interference components on the voltage-controlled signal.
According to the present invention, the resistance value of the resistor R1 is preferably 1kΩ, and the capacitance value of the capacitor C1 is preferably 0.1 μf.
According to the invention, the voltage control range of the voltage controlled crystal oscillator is not less than +/-50 ppm. Meeting the frequency range requirement of the clock interface of the communication system.
Preferably, the link layer FPGA comprises a PLL module for generating a clock frequency required inside the link layer FPGA and an IIR digital filter for filtering out over-the-air jitter and digital sampling jitter.
According to the invention, the formula for calculating the current clock deviation data x (n) by the IIR digital filter is shown as formula (i):
y(n)＝(1-α)*y(n-1)+α*x(n) (Ⅰ)
in the formula (I), y (n) refers to the current frame head arrival time count value, y (n-1) refers to the last frame head arrival time count value, alpha is a coefficient, and the value range of alpha is 0.1-0.4.
The operation method of the clock synchronization circuit comprises the following specific steps:
(1) The link layer FPGA sends a time slot control data packet to the modem FPGA through a first Serdes interface and a second Serdes interface;
(2) According to the time slot control data packet sent by the link layer FPGA, the modem FPGA searches frame header data from a central station in real time, records a time count value when the current frame header arrives after capturing the starting position of system frame information, packages the time count value into a standard Ethernet frame structure format and sends the standard Ethernet frame structure format to the link layer FPGA;
(3) The link layer FPGA performs deviation information processing according to the received current frame head arrival time count value and the last frame head arrival time count value to obtain deviation data, and the deviation data is sent to the DAC circuit and converted into a voltage-controlled analog signal through the DAC circuit;
(4) And the voltage-controlled analog signal is transmitted to the voltage-controlled crystal oscillator after passing through the RC filter circuit, and the output frequency of the voltage-controlled analog signal is controlled to be gradually synchronized to a central station clock.
The application of the clock synchronization circuit is suitable for clock synchronization of different system frame frequencies which are not less than 125 Hz.
The beneficial effects of the invention are as follows:
the clock synchronization circuit adopts an FPGA as a core processing platform, and realizes indoor and outdoor data interaction and clock synchronization through a Serdes interface circuit; meanwhile, by combining with an efficient indoor and outdoor interface protocol, the time slot control data packet is sent by using a time counting value mode to realize accurate receiving and sending control of the indoor unit to the outdoor unit communication data packet, and the receiving and sending reference time of all communication frames is in the outdoor unit, so that the problems of time delay and time delay change caused by indoor and outdoor connection media and transmission length are solved. The clock synchronization circuit has high transmission efficiency, low realization cost and general reliability.
Drawings
FIG. 1 is a block diagram of a connection of a clock synchronization circuit according to the present invention;
Detailed Description
The invention is further defined by, but is not limited to, the following drawings and examples in conjunction with the specification.
Example 1
The clock synchronization circuit of the point-to-multipoint microwave communication system comprises an outdoor unit, an indoor unit and a Serdes interface circuit, wherein the outdoor unit is connected with the indoor unit through the Serdes interface circuit, and the data interaction and clock synchronization of the outdoor unit and the indoor unit are realized through the Serdes interface circuit.
The characteristics of high speed, clock recovery and the like of the Serdes interface circuit are utilized to realize data transmission and clock synchronization of the outdoor unit and the indoor unit.
The indoor and outdoor interface protocol comprises a frame head part of a standard Ethernet frame, a data part of the standard Ethernet frame and a frame check sequence part of the standard Ethernet frame, wherein the frame head part of the standard Ethernet frame comprises a preamble, a delimiter, a destination address, a source address and a length, the data part of the standard Ethernet frame comprises indoor and outdoor control data and time slot data, and the frame check sequence part of the standard Ethernet frame comprises frame check. As shown in table 1:
TABLE 1
The outdoor unit comprises a radio frequency transceiver module, a clock crystal oscillator and a modulation demodulation FPGA, and the indoor unit comprises a link layer FPGA, a DAC circuit, an RC filter circuit and a voltage-controlled crystal oscillator; the Serdes interface circuit comprises a first Serdes interface positioned at the outdoor unit and a second Serdes interface positioned at the indoor unit;
the modem FPGA is connected with the first Serdes interface; the second Serdes interface is connected with the link layer FPGA; the radio frequency transceiver module and the clock crystal oscillator are respectively connected with the modulation-demodulation FPGA, and the link layer FPGA, the DAC circuit, the RC filter circuit and the voltage-controlled crystal oscillator are sequentially and annularly connected; as shown in fig. 1.
The radio frequency transceiver module is used for wireless transceiving of communication data;
the clock crystal oscillator is used for providing a reference clock for the first Serdes interface;
the modem FPGA searches frame header data from a central station in real time according to a time slot control data packet sent by the link layer FPGA, records a time count value when the current frame header arrives after the frame header data is captured, and packages the time count value into a standard Ethernet frame structure format and sends the standard Ethernet frame structure format to the link layer FPGA;
the link layer FPGA performs deviation information processing according to the received current frame head arrival time count value and the last frame head arrival time count value to obtain deviation data, and the deviation data is sent to the DAC circuit and converted into a voltage-controlled analog signal through the DAC circuit;
and the voltage-controlled analog signal is transmitted to the voltage-controlled crystal oscillator after passing through the RC filter circuit, and the output frequency of the voltage-controlled analog signal is controlled to be gradually synchronized to a central station clock.
The outdoor unit and the indoor unit mainly take an FPGA as a core processing platform. The adopted FPGA chip has rich I/O resources, logic resources, static random access memory resources, PLL, DSP and various I/O level standards.
The first Serdes interface and the second Serdes interface adopt standard Ethernet frame structures, and the indoor unit can accurately transmit and receive the communication data packet of the outdoor unit by transmitting the time slot control data packet in a time counting value mode, and the transmitting and receiving reference time of all communication frames is in the outdoor unit.
The RC filter circuit comprises a resistor R1 and a capacitor C1, one end of the resistor R1 is connected with the DAC circuit, and the voltage-controlled crystal oscillator is respectively connected with the other end of the resistor R1 and one end of the capacitor C1. The RC filter circuit is used for filtering interference components on the voltage-controlled signal.
The resistance value of the resistor R1 is 1KΩ, and the capacitance value of the capacitor C1 is 0.1 μF.
The voltage control range of the voltage controlled crystal oscillator is not less than +/-50 ppm. Meeting the frequency range requirement of the clock interface of the communication system.
The link layer FPGA comprises a PLL module and an IIR digital filter, wherein the PLL module is used for generating clock frequency required by the inside of the link layer FPGA, and the IIR digital filter is used for filtering air transmission jitter and digital sampling jitter.
The formula for calculating the current clock deviation data x (n) by the IIR digital filter is shown as formula (I):
y(n)＝(1-α)*y(n-1)+α*x(n) (Ⅰ)
in the formula (I), y (n) refers to the current frame head arrival time count value, y (n-1) refers to the last frame head arrival time count value, alpha is a coefficient, and the value range of alpha is 0.1-0.4.
Example 2
The method for operating a clock synchronization circuit of embodiment 1 comprises the following specific steps:
(1) The link layer FPGA sends a time slot receiving control data packet to the modem FPGA through a first Serdes interface and a second Serdes interface;
(2) Receiving a control data packet according to a time slot sent by the link layer FPGA, searching frame header data from a central station in real time by the modem FPGA, recording a time count value when the current frame header arrives after the frame header data is captured, and packaging the time count value into a standard Ethernet frame structure format and sending the standard Ethernet frame structure format to the link layer FPGA;
(3) The link layer FPGA performs deviation information processing according to the received current frame head arrival time count value and the last frame head arrival time count value to obtain deviation data, and the deviation data is sent to the DAC circuit and converted into a voltage-controlled analog signal through the DAC circuit;
(4) And the voltage-controlled analog signal is transmitted to the voltage-controlled crystal oscillator after passing through the RC filter circuit, and the output frequency of the voltage-controlled analog signal is controlled to be gradually synchronized to a central station clock.
Example 3
The application of the clock synchronization circuit described in embodiment 1 is applicable to clock synchronization of different system frame rates of not less than 125 Hz.
Claims (8)
1. The clock synchronization circuit of the point-to-multipoint microwave communication system is characterized by comprising an outdoor unit, an indoor unit and a Serdes interface circuit, wherein the outdoor unit is connected with the indoor unit through the Serdes interface circuit, and the data interaction and clock synchronization between the outdoor unit and the indoor unit are realized through the Serdes interface circuit;
the outdoor unit comprises a radio frequency transceiver module, a clock crystal oscillator and a modulation demodulation FPGA, and the indoor unit comprises a link layer FPGA, a DAC circuit, an RC filter circuit and a voltage-controlled crystal oscillator; the Serdes interface circuit comprises a first Serdes interface positioned at the outdoor unit and a second Serdes interface positioned at the indoor unit;
the modem FPGA is connected with the first Serdes interface; the second Serdes interface is connected with the link layer FPGA; the radio frequency transceiver module and the clock crystal oscillator are respectively connected with the modulation-demodulation FPGA, and the link layer FPGA, the DAC circuit, the RC filter circuit and the voltage-controlled crystal oscillator are sequentially and annularly connected;
the radio frequency transceiver module is used for wireless transceiving of communication data;
the clock crystal oscillator is used for providing a reference clock for the first Serdes interface;
the modem FPGA searches frame header data from a central station in real time according to a time slot control data packet sent by the link layer FPGA, records a time count value when the current frame header arrives after the frame header data is captured, and packages the time count value into a standard Ethernet frame structure format and sends the standard Ethernet frame structure format to the link layer FPGA;
the link layer FPGA performs deviation information processing according to the received current frame head arrival time count value and the last frame head arrival time count value to obtain deviation data, and the deviation data is sent to the DAC circuit and converted into a voltage-controlled analog signal through the DAC circuit;
and the voltage-controlled analog signal is transmitted to the voltage-controlled crystal oscillator after passing through the RC filter circuit, and the output frequency of the voltage-controlled analog signal is controlled to be gradually synchronized to a central station clock.
2. The clock synchronization circuit of the point-to-multipoint microwave communication system according to claim 1, wherein the RC filter circuit comprises a resistor R1 and a capacitor C1, one end of the resistor R1 is connected to the DAC circuit, and the voltage-controlled crystal oscillator is connected to the other end of the resistor R1 and one end of the capacitor C1 respectively.
3. A clock synchronization circuit for a point-to-multipoint microwave communication system according to claim 2, wherein the resistance value of the resistor R1 is 1kΩ, and the capacitance value of the capacitor C1 is 0.1 μf.
4. The clock synchronization circuit of a point-to-multipoint microwave communication system according to claim 1, wherein a voltage control range of the voltage controlled crystal oscillator is not less than ±50ppm.
5. The clock synchronization circuit of the point-to-multipoint microwave communication system according to claim 1, wherein the link layer FPGA comprises a PLL module and an IIR digital filter, the PLL module being configured to generate a clock frequency required inside the link layer FPGA, the IIR digital filter being configured to filter out over-the-air jitter and digital sampling jitter.
6. The clock synchronization circuit of the point-to-multipoint microwave communication system according to claim 5, wherein a formula for calculating the current clock deviation data x (n) by the IIR digital filter is shown in formula (i):
y(n)＝ (1-α)*y(n-1)+ α*x(n) (Ⅰ)
in the formula (I), y (n) refers to the current frame head arrival time count value, y (n-1) refers to the last frame head arrival time count value, alpha is a coefficient, and the value range of alpha is 0.1-0.4.
7. A clock synchronization circuit for a point-to-multipoint microwave communication system according to any of claims 1-6, wherein the clock synchronization circuit is adapted for clock synchronization of different system frame rates of not less than 125 Hz.
8. A method of operation for use in a clock synchronization circuit as claimed in any one of claims 1 to 7, comprising the steps of:
(1) The link layer FPGA sends a time slot receiving control data packet to the modem FPGA through a first Serdes interface and a second Serdes interface;
(2) Receiving a control data packet according to a time slot sent by the link layer FPGA, searching frame header data from a central station in real time by the modem FPGA, recording a time count value when the current frame header arrives after the frame header data is captured, and packaging the time count value into a standard Ethernet frame structure format and sending the standard Ethernet frame structure format to the link layer FPGA;
(3) The link layer FPGA performs deviation information processing according to the received current frame head arrival time count value and the last frame head arrival time count value to obtain deviation data, and the deviation data is sent to the DAC circuit and converted into a voltage-controlled analog signal through the DAC circuit;
(4) And the voltage-controlled analog signal is transmitted to the voltage-controlled crystal oscillator after passing through the RC filter circuit, and the output frequency of the voltage-controlled analog signal is controlled to be gradually synchronized to a central station clock.
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| US8731007B2 (en) * | 2005-12-30 | 2014-05-20 | Remec Broadband Wireless, Llc | Digital microwave radio link with a variety of ports |
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| CN103051575A (en) * | 2011-10-14 | 2013-04-17 | 美国博通公司 | Multi gigabit modem for mmwave point to point links |
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