CN107046449A

CN107046449A - Method and clock for time synchronized

Info

Publication number: CN107046449A
Application number: CN201610083923.7A
Authority: CN
Inventors: 吕京飞
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2016-02-06
Filing date: 2016-02-06
Publication date: 2017-08-15
Also published as: WO2017133478A1

Abstract

This application provides the method and clock for time synchronized.This method includes the first clock and receives the first information and the second information that second clock is sent, and the first information is used for the time grade for indicating the second clock, and second information is used for the frequency level for indicating the second clock；First clock compares the frequency level of the frequency level of first clock and the second clock after it is determined that the time grade of first clock and the time grade of the second clock are equal, obtains the first comparative result；First clock according to first comparative result determine whether using the second clock as first clock master clock.In such scheme, it is determined that considering frequency level this factor before master clock.Therefore, above-mentioned technical proposal helps to select the preferable master clock of quality.Or, above-mentioned technical proposal helps avoid selecting second-rate master clock.

Description

Method and clock for time synchronized

Technical field

The present invention relates to the communications field, the more particularly to method and clock for time synchronized.

Background technology

In communication network, each equipment has the clock of oneself.In order to meet business transmission demand, the clock of equipment need to be to be synchronized.The deviation of time of the clock of two equipment of communication is needed no more than certain limit.

Clock synchronously includes Frequency Synchronization and time synchronized.Realize that the clock between two equipment can synchronously there are two schemes.Described two equipment can be two base stations.One kind is that each equipment installs satellite antenna, and the clock of equipment is synchronous with the clock realization of aerial synchronous satellite.Another is that the clock of each equipment is synchronized with a common clock source by a transmission network, so as to realize that clock is synchronous between two equipment.

Most of existing communication networks use second scheme, i.e., the clock of each equipment is synchronized with a common clock source.

For second scheme, Frequency Synchronization routing algorithm can be International Telecommunication Union (International Telecom Union, ITU Synchronication status message (Synchronization status message, the SSM) algorithm) G.781 and G.8264 defined.Time synchronized routing algorithm can be Electrical and Electronic Engineering society (Institute of Electrical and Electronics Engineers, IEEE best master clock algorithm (the Best Master Clock Algorithm that) 1588-2008 is defined, BMCA) or the ITU replacements that G.8275.1 the BMCA algorithms based on IEEE 1588-2008 are defined best master clock algorithm (Alternate Best Master Clock Algorithm, A-BMCA) algorithm.

Existing SSM frequency synchronization algorithms can be the algorithm G.781 and G.8264 defined by ITU.Opposite equip. (or clock in equipment) sends the message containing frequency level information to local device (or clock in equipment).After local device receives message, the frequency level of opposite equip. and the frequency level of local device are compared according to the message received, so as to regard the higher equipment of frequency level as master clock.If frequency level is identical, need to compare configuration information, so that it is determined that master clock, 5.12 chapters of the detailed content referring to ITU G.781.

Time synchronized path between two clocks can be determined according to prior art.For example, the A-BMCA algorithms that G.8275.1 the time synchronized path between device A and equipment B can define according to IEEE 1588-2008 BMCA algorithms or ITU are determined.Specifically, in the prior art, when device A is identical with equipment B time grade, the time synchronized path between device A and equipment B can be determined by comparing the configuration information of device A and equipment B.Device A is using equipment B as after the master clock of device A, and device A is synchronized to equipment B time.Or, equipment B is using device A as after equipment B master clock, and equipment B is synchronized to the time of device A.Determine that the method for the configuration information for comparing two clocks after the time grade of two clocks is identical is likely to result in not selecting the preferable master clock of quality.Or, it is possible to lead to not avoid selecting second-rate master clock.

Therefore, the preferable master clock of quality how is selected.Or, how to avoid selecting second-rate master clock, as urgent problem to be solved.

The content of the invention

The embodiments of the invention provide a kind of method and clock for time synchronized, this method can select the preferable master clock of quality.Or, it is to avoid the second-rate master clock of selection.

First aspect there is provided a kind of method for time synchronized, including：

First clock receives the first information and the second information that second clock is sent, and the first information is used for the time grade for indicating the second clock, and second information is used for the frequency level for indicating the second clock；

First clock compares the frequency level of the frequency level of first clock and the second clock after it is determined that the time grade of first clock and the time grade of the second clock are equal, obtains the first comparative result；

First clock according to first comparative result determine whether using the second clock as first clock master clock.

Therefore, the embodiment of the present invention is by the case of the time grade identical of two clocks, the frequency level of comparison clock, and according to comparative result determine whether using a clock as another clock master clock.That is, determining to consider frequency level this factor before master clock.Therefore, above-mentioned technical proposal contributes to the master clock for selecting quality higher.Or, above-mentioned technical proposal helps avoid the master clock for selecting quality relatively low.Determine after master clock, also determined that from the time synchronized path of clock from the master clock of clock.Therefore, above-mentioned technical proposal helps to set up the higher time synchronized path of quality.Or, above-mentioned technical proposal helps avoid setting up the relatively low time synchronized path of quality.

Specifically, being sent mutually in the embodiment of the present invention, between the first clock and second clock includes time class information and the message for time synchronized of frequency level information.Then time tracking is carried out, for example it is described by taking the angle of the first clock as an example as follows, after the first clock receives message, can be by the temporal quality grade and the temporal quality grade of local device (the first clock) of the second clock received, when the temporal quality grade of second clock is higher than the temporal quality grade of the first clock, the time of first clock tracing second clock, opposite, when the temporal quality grade of the first clock is higher than the temporal quality grade of second clock, second clock tracks the time of the first clock, when the temporal quality grade of two clocks is equal, first clock can compare the Frequency Synchronization credit rating of the Frequency Synchronization credit rating of the first clock and second clock, obtain the first comparative result；And according to comparative result determine whether the second clock as the master clock of first clock whether track the time of the second clock really according to comparative result.

It should be understood that the first information in the embodiment of the present invention can also be described as time class information, the second information can also be described as frequency level information.The embodiment of the present invention is not limited to this.

It should be noted that in embodiments of the present invention, the A-BMCA algorithms that G.8275.1 mode for carrying out time synchronized according to time grade can be defined using ITU, or the BMCA algorithms that IEEE 1588-2008 are defined, no longer it is described in detail herein.

Wherein, the first comparative result can indicate that the frequency level of the first clock is more than, less than or equal to three kinds of situations of frequency level of second clock.For these three situations, accordingly time tracking method is also differed accordingly, will be described respectively below.

With reference in a first aspect, in a kind of implementation of first aspect, when first comparative result indicates that the frequency level of first clock is less than the frequency level of the second clock,

First clock according to first comparative result determine whether using the second clock as first clock master clock, including：

First clock according to first comparative result using the second clock as first clock master clock.

With reference to first aspect and its above-mentioned implementation, in another implementation of first aspect, when first comparative result indicates that the frequency level of first clock is higher than the frequency level of the second clock,

First clock according to first comparative result determine avoid using the second clock as first clock master clock.

In other words, in this case, because when temporal quality grade is identical, the frequency level of the first clock is high, namely time precision is high.So second clock need using first clock as the second clock master clock.

With reference to first aspect and its above-mentioned implementation, in another implementation of first aspect, this method also includes：

First clock receives the second configuration information of second clock transmission, second configuration information includes at least one in the identity of the big master clock of the priority one, the priority two of the big master clock of the second clock and the second clock of the big master clock of the second clock

Wherein, when first comparative result indicate first clock frequency level be equal to the second clock frequency level when, first clock according to first comparative result determine whether using the Section Point as the first node master clock, including：

First clock is after first comparative result is obtained, and the first configuration information of first clock is compared by first clock with second configuration information, obtains the second comparative result；

First clock determined whether the second clock as the master clock of first clock according to second comparative result, at least one in the identity of the big master clock of the priority one of the big master clock of first configuration information including first clock, the priority two of the big master clock of first clock and first clock.

In other words, in this case, i.e., when the time grade and frequency level all same of the first clock and second clock, the first clock also needs to compare configuration information, and carries out time synchronized according to comparative result.

It should be understood that being to compare same type of value correspondence, different types of value is not compared when the first clock compares the first configuration information and the second configuration information.For example, the priority one of the big master clock of the first clock is made comparisons with the priority one of the big master clock of second clock, the identity of the big master clock of the first clock and the identity of the big master clock of second clock are compared.

It should be understood that, in the embodiment of the present invention, the A-BMCA algorithms G.8275.1 defined similar to ITU, or, the BMCA algorithms defined similar to IEEE 1588-2008, the configuration information can include at least one in priority one, the priority two of big master clock, the identity of big master clock and the port local first level of big master clock.Specifically how time synchronized is carried out according to configuration information and be referred to two standards, here is omitted.

It should be understood that the time class information and frequency level information in the embodiment of the present invention can also can be limited by a message bearing by different message bearings, the embodiment of the present invention not to this.

With reference to first aspect and its above-mentioned implementation, in another implementation of first aspect, first clock receives the first information and the second information that second clock is sent, including：

First clock receives the message for time synchronized that second clock is sent, and the message includes the first information and second information.

With reference to first aspect and its above-mentioned implementation, in another implementation of first aspect, the message is notice Announce message,

Second information of the second clock is carried in the reserve bytes of the message header of the Announce message,

Or, the second information of the second clock is carried in the reserve bytes of the message field of the Announce message,

Or, the second information of the second clock is carried in the Type Length value TLV fields in the Announce message.

Second information of the second clock is stored in clock quality clockQuality data sets by first clock,

After the time of the first clock tracing second clock, when first clock and the 3rd clock carry out time synchronized, the second information of the second clock is sent to the 3rd clock.

For example, the clock quality data set (clockQuality data set) that the clock quality data set, which can be Precision Time Protocol PTP, to be defined.It can be IEEE 1588v1 or IEEE 1588-2008 that the PTP, which can be,.

Specifically, after first clock receives the Announce message of second clock, the frequency level information of the second clock is stored in the local clockQuality data sets of the first clock, then the judgement synchronized, after the first clock determines the time of tracking second clock, the frequency level information of the second clock can be retained in the local clockQuality data sets of the first clock, and when first clock and the 3rd clock carry out time synchronized, the frequency level information of the second clock is sent to the 3rd clock, time synchronizing is carried out according to the frequency level information of the second clock to trigger the 3rd clock.When first determines the time without tracking second clock, the frequency level information of the second clock can be deleted from the local clockQuality data sets of the first clock, and when first clock and the 3rd clock carry out time synchronized, the frequency level information of first clock is still sent to the 3rd clock, time synchronizing is carried out according to the frequency level information of first clock to trigger the 3rd clock.

With reference to first aspect and its above-mentioned implementation, in another implementation of first aspect, the first information includes：At least one in the variance yields of the time deviation of the big master clock of the grade of the big master clock of the second clock, the precision of the big master clock of the second clock and the second clock.

Second aspect, there is provided a kind of the first clock for time synchronized, first clock can realize any implementation in first aspect and its implementation, the operation and/or function of modules in first clock, it is respectively used to the correlation method feature in the first aspect of realization and its implementation, for sake of simplicity, will not be repeated here.

The third aspect includes the memory and processor of store instruction there is provided a kind of equipment for time synchronized, the equipment, wherein, the computing device instruction carries out any method for time synchronized provided such as first aspect and its various implementations.

Fourth aspect is applied in communication system there is provided a kind of processing unit, the processing unit.The processing unit can be one or more processors or chip.In the case of other are possible, the processing unit can also be entity apparatus or virtual bench in communication system.The processing unit is arranged to perform any method for time synchronized that above-mentioned first aspect and its various implementations are provided.

5th aspect is there is provided a kind of computer program product, and the computer program product includes：Computer program code, when the computer program code is run by the computing unit, processing unit or processor of communication equipment so that the communication equipment performs any method for time synchronized that above-mentioned first aspect and its various implementations are provided.

6th aspect is there is provided a kind of computer-readable recording medium, and the computer-readable recording medium storage has program, and the program causes communication equipment to perform any method for time synchronized that above-mentioned first aspect and its various implementations are provided.

7th aspect is there is provided a kind of first device, including the first clock that such as second aspect is provided.The first device can be base station, terminal or transmission node.

Eighth aspect is there is provided a kind of network system, including first device and second device, and first device includes the first clock that second aspect is provided, and second device includes the second clock that second aspect is related to.

For example, in such scheme, clock is the node for referring to send or receiving the message for time synchronized.

For example, the message for time synchronized can be the precision clock protocol message that IEEE 1588-2008 are defined.

For example, master clock (master clock) is a kind of clock.Specifically, master clock is the source (source of time) of a time.The source of the time can be synchronized to from clock.

The time precision of clock represents error of the time relative to standard time source of clock, and the time precision higher time for representing clock of clock is smaller relative to the error in standard time source.Similarly, the frequency accuracy of clock represents error size of the frequency relative to standard frequency source of the clock, and the higher frequency for representing clock of frequency accuracy of clock is smaller relative to the error of standard frequency source.

Brief description of the drawings

In order to illustrate the technical solution of the embodiments of the present invention more clearly, will be briefly described below to the required accompanying drawing used in the embodiment of the present invention.It should be evident that drawings described below is only some embodiments of the present invention, for those of ordinary skill in the art, on the premise of not paying creative work, other accompanying drawings can also be obtained according to these accompanying drawings.

Fig. 1 is the clock system schematic diagram of one embodiment of the invention.

Fig. 2 is BMCA algorithm flow charts provided in an embodiment of the present invention.

Fig. 3 is A-BMCA algorithm flow charts provided in an embodiment of the present invention.

Fig. 4 is time synchronized exemplary plot provided in an embodiment of the present invention.

Fig. 5 is the method schematic flow diagram according to an embodiment of the invention for time synchronized.

Fig. 6 is the method schematic flow diagram according to another embodiment of the present invention for time synchronized.

Fig. 7 is the method schematic flow diagram according to another embodiment of the present invention for time synchronized.

Fig. 8 is the schematic block diagram of the clock according to an embodiment of the invention for time synchronized.

Fig. 9 is the schematic block diagram of the clock according to an embodiment of the invention for time synchronized.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is explicitly described.Obviously, described embodiment is a part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, the other embodiment that those of ordinary skill in the art can obtain on the premise of creative work is not made.

The embodiment of the present invention can be applied to various communication systems.Therefore, the application scenarios of technical scheme provided in an embodiment of the present invention are not restricted to particular communications system.The communication system that the application scenarios of technical scheme are used can be global system for mobile telecommunications (Global System of Mobile communication, referred to as " GSM ") system, CDMA (Code Division Multiple Access, referred to as " CDMA ") system, WCDMA (Wideband Code Division Multiple Access, referred to as " WCDMA ") system, GPRS (General Packet Radio Service, referred to as " GPRS "), Long Term Evolution (Long Term Evolution, referred to as " LTE ") system, LTE FDDs (Frequency Division Duplex, referred to as " FDD ") system, LTE time division duplexs (Time Division Duplex, referred to as " TDD ") or UMTS (Universal Mobile Telecommunication System, referred to as " UMTS ").

Fig. 1 is the clock system schematic diagram of one embodiment of the invention.System shown in Fig. 1 includes base station, base station controller, transmission node and common clock source.Wherein, base station controller passes through the business between transmission node scheduling base station.Transmission node can be ethernet switch, Internet protocol (internet protocol, IP) router, Packet Transport Network PTN (Packet Transport Network), microwave M icrowave equipment or optical transfer network OTN (Optical Transport Network).Base station can be the equipment for being communicated with terminal device.For example, base station can be base station (the Base Transceiver Station in gsm system or CDMA, BTS), can also be the base station (NodeB in WCDMA system, NB), it can also be the evolved base station (Evolutional Node B, eNB or eNodeB) in LTE system.Or base station can be the network side equipment in relay station, access point, mobile unit or future 5G networks.

The clock of each base station can be synchronized to a common clock source (a kind of standard time clock) in system shown in Fig. 1, so that the synchronization between realizing base station.As seen from Figure 1, by the transmission of transmission node, base station of the transmission node by the clock signal transmission in common clock source to end.Middle transmission node can bring the loss of clock signal when transmitting clock signal.Therefore, during transmission node transmission clock signal, the preferable time synchronized path of a performance can be selected.Such as, the time synchronized path of better performances can be apart from most short time synchronized path.

In the embodiment of the present invention, device A and equipment B are two clocks for needing to carry out time synchronized respectively.Clock described herein is the node for referring to send or receiving the message for time synchronized.Message for time synchronized can be the precision clock protocol message (precision time protocol message) that IEEE 1588-2008 are defined.Further, clock described herein can provide the measurement (measurement of passage of time) of the passage to the time.For example, clock described herein can be the clock that the chapters of IEEE 1588-2008 the 3rd are defined.When implementing, clock includes crystal oscillator and phaselocked loop.

In the embodiment of the present invention, master clock (master clock) is a kind of clock.Specifically, master clock is the source (source of time) of a time.The source of the time can be synchronized to from clock.For example, master clock can be the master clock that the chapters of IEEE 1588-2008 the 3rd are defined.

It should also be understood that the time grade in the embodiment of the present invention is used for the precision for describing the time of clock.The precision of the time of the precision of the time of the high clock of the time grade clock low higher than time grade.Frequency level is used for the precision for describing the frequency of clock.The precision of the frequency of the precision of the frequency of the high clock of the frequency level clock low higher than frequency level.

The time precision of clock in the embodiment of the present invention represents error of the time relative to standard time source of clock, and the time precision higher time for representing clock of clock is smaller relative to the error in standard time source.Similarly, the frequency accuracy of clock represents error size of the frequency relative to standard frequency source of the clock, and the higher frequency for representing clock of frequency accuracy of clock is smaller relative to the error of standard frequency source.

Think to be less than master clock from least one in the time precision and frequency accuracy of clock in the embodiment of the present invention.That is the time from clock is not accurate enough with respect to master clock.Time deviation (Offset) can be determined, and then calibrate the time from clock according to the Offset according to the message for time synchronized sent with master clock from clock.

It should also be understood that in embodiments of the present invention, device A tracking equipment B time (i.e. synchronous path is A to B).The time for being synchronized to equipment B with device A represents same implication.

Specifically, in device A using equipment B as after the master clock (i.e. device A is that from clock, equipment B is master clock) of device A, interact between device A and equipment B is used for the message of time synchronized.The message for being used for time synchronized can be accurate clock synchronization protocol (Precision Time Protocol, PTP) message, for example, can be at least one in synchronous (Sync) message, tracking (Follow_Up) message, delay request (Delay-Req) message and delay response (Delay_Resp) message.Time deviation (Offset) can be calculated based on the message for being used for time synchronized.Device A is obtained after Offset, can be according to Offset calibrator (-ter) units A time.

Similarly, equipment B tracking equipments A time represents same implication with the equipment B times for being synchronized to device A.Specifically, equipment B is using device A as after equipment B master clock (i.e. equipment B be from clock, device A is master clock), and interact between equipment B and device A is used for the message of time synchronized.The message for being used for time synchronized can be accurate clock synchronization protocol (Precision Time Protocol, PTP) message.For example, the PTP message can include synchronous (Sync) message, tracking (Follow_Up) message, delay request (Delay-Req) message and delay response (Delay_Resp) message.The time deviation (Offset) of equipment B and device A can be calculated based on the message for being used for time synchronized.Equipment B is obtained after Offset, can be according to Offset calibrator (-ter) units B time.

Time synchronized path decision algorithm can be the A-BMCA algorithms that G.8275.1 the BMCA algorithms and ITU that IEEE 1588-2008 mentioned above are defined define.It is described in detail respectively with reference to Fig. 2 and Fig. 3.

Specifically, Fig. 2 is BMCA algorithm flow charts provided in an embodiment of the present invention.On BMCA algorithms, IEEE 1588-2008 are may be referred to.As shown in Fig. 2 device A and equipment B are respectively received includes the message for time synchronized of time class information and configuration information from other side.Device A and equipment B according to the message received by comparing device A and equipment B time grade respectively.And compare the grade of configuration information after grade is identical in the time again, to determine time synchronized path.Device A and equipment B it is determined that carry out time synchronized (tracking) again after synchronous path.Wherein, time class information includes：The variance yields (GM offsetScaledLogVariance) of the deviation of the big grade (GM class) of master clock, the precision (GM accuracy) of big master clock and big master clock.Configuration information includes：The ID (GM identity) of the big priority one (GM priroty1) of master clock, the priority two (GM priority2) of big master clock and big master clock.Specifically, as shown in Fig. 2 device A and equipment B can perform following steps：

201, judge whether the ID of device A and equipment B big master clock is equal.If equal, it can determine to carry out time synchronized according to existing mode, here is omitted.If unequal, step 202 is performed.

202, compare the priority one of device A and equipment B big master clock.If A>B, then perform step 208.Step 203 is performed if A=B, if A<B, then perform step 209.

It should be understood that for device A and an equipment B class information, such as priority one of big master clock.Use A>B represents that the value of the priority one of the big master clock of device A is more than the value of the priority one of equipment B big master clock；And for illustrating that the time grade of device A is less than equipment B time grade.I.e. equipment B time precision is higher than the time precision of device A.Use A<B represents that the value of the priority one of the big master clock of device A is less than the value of the priority one of equipment B big master clock；And for illustrating that the time grade of device A is more than equipment B time grade.I.e. the time precision of device A is higher than equipment B time precision.Represent that the value of the priority one of the big master clock of device A is equal to the value of the priority one of equipment B big master clock with A=B.The time precision of device A and equipment B is cannot be distinguished by using the priority one of big master clock.

That is, working as A>During B, illustrate that equipment B precision is higher than the precision of device A, so performing 208.Similarly, A is worked as<During B, illustrate that the precision of device A is higher than equipment B precision, so performing 209.Similarly, when a=b, the precision that the accurate facility B of device A is cannot be distinguished by according to the priority one of the big master clock is illustrated, so performing 203, relatively more other class informations.

It is succinct for description for other class informations it should be noted that herein, with similar description, i.e., A is used respectively>B、A<B and A=B represent the relation of device A and the value of equipment B corresponding class information.The A hereinafter occurred>B、A<B and A=B represent the magnitude relationship of the value of device A class information corresponding with equipment B, no longer will hereinafter be illustrated one by one.

It shall yet further be noted that hereinafter, for any class information, working as A>During B, the precision of explanation device A is less than equipment B precision.Similarly, A is worked as<During B, illustrate that the precision of device A is higher than equipment B precision.When a=b, illustrate according to any class information cannot be distinguished by device A accurate facility B precision, it is necessary to the other class informations of comparison.For sake of simplicity, no longer will hereinafter be illustrated one by one.

203, compare the grade of device A and equipment B big master clock.If A>B, then perform step 208.Step 204 is performed if A=B, if A<B, then perform step 209.

204, compare the precision of device A and equipment B big master clock.If A>B, then perform step 208.Step 205 is performed if A=B, if A<B, then perform step 209.

205, compare the variance yields of device A and the deviation of equipment B big master clock.If A>B, then perform step 208.Step 206 is performed if A=B, if A<B, then perform step 209.

206, compare the priority two of device A and equipment B big master clock.If A>B, then perform step 208.Step 207 is performed if A=B, if A<B, then perform step 209.

207, compare the ID of device A and equipment B big master clock value.If A>B, then perform step 208.If A<B, then perform step 209.

208, device A tracking equipment B time.

209, equipment B tracking equipments A time.

Fig. 3 is A-BMCA algorithm flow charts provided in an embodiment of the present invention.On A-BMCA algorithms, ITU may be referred to G.8275.1.As shown in figure 3, device A and equipment B receive mutually the message for time synchronized including time class information and configuration information of other side.Device A and equipment B according to the message received by comparing device A and equipment B time grade respectively, and the grade after grade is identical in the time in relatively configuration information, to determine time synchronized path.Device A and equipment B it is determined that carry out time synchronized (tracking) again after synchronous path.Wherein, time class information includes：The variance yields (GM offsetScaledLogVariance) of the deviation of the big clock grade (GM clockClass) of master clock, the clock accuracy (GM clockAccuracy) of big master clock and big master clock；Configuration information includes：The priority two (GM priority2) of big master clock, the local first level (localPriority) of port, the local first level of local clock and the clock ID (GM clockIdentity) of master clock greatly.The local first level of port is to confer to the local first level of (assign) port.The local first level of local clock is to confer to the local first level of (assign) local clock.Specifically, as shown in figure 3, the step of device A and equipment B need to carry out following time synchronized：

301, compare the clock grade of device A and equipment B big master clock.If A>B, then perform step 308.Step 302 is performed if A=B, if A<B, then perform step 309.

302, compare the clock accuracy of device A and equipment B big master clock.If A>B, then perform step 308.Step 303 is performed if A=B, if A<B, then perform step 309.

303, compare the variance yields of device A and the deviation of equipment B big master clock.If A>B, then perform step 308.Step 304 is performed if A=B, if A<B, then perform step 309.

304, compare the priority two of device A and equipment B big master clock.If A>B, then perform step 308.Step 305 is performed if A=B, if A<B, then perform step 309.

305, compare the local first level of the local first level and device A of the port of device A.Wherein, device A port is for the port with equipment B interaction messages.Or compare the local first level and equipment B local first level of equipment B port.Wherein, equipment B ports are for the port with device A interaction message.If the local first level of A port performs step 308 higher than the local first level of device A.Step 306 is performed if the local first level that the local first level of A port is equal to device A, if the local first level of A port performs step 309 less than the local first level of device A.

306, judge whether device A and equipment B clock grade are less than or equal to 127.If it is it can determine to carry out time synchronized according to existing mode, here is omitted.If it is not, then performing 307.

307, compare the clock ID of device A and equipment B big master clock value.If A>B, then perform step 308.If A<B, then perform step 309, can determine to carry out time synchronized according to existing mode if A=B, here is omitted.

308, device A tracking equipment B time.

309, equipment B tracking equipments A time.

It is previously mentioned, is determined from clock after master clock, the message synchronous for clock can be interacted between clock and master clock.Offset can be determined according to interactive message from clock.So as to which the time from clock can be calibrated from clock.That is, the time from determination master clock to calibration from clock is, it is necessary to undergo a process.The process needs to take regular hour length.It is appreciated that the precision of the calibrated time from clock is influenceed by the time grade of master clock.Further, since needing to take regular hour length to calibration from this process of the time of clock from determination master clock, the precision of the calibrated time from clock is also influenceed by the frequency level of master clock.Therefore, under the premise of time grade identical, the quality of the clock signal of the high clock output of frequency level is higher than the quality of the clock signal of the low clock output of frequency level., as the scheme of master clock, the scheme of frequency level high clock as master clock is helped so that from clock relative to using the low clock of frequency level and obtain the precision higher calibrated time.Current Time synchronization algorithm (such as BMCA algorithms or A-BMCA algorithms) does not account for frequency level in selection time synchronous path.Thus, it is possible to cause the time tracking of the high clock of frequency level in the low clock of frequency level.Assuming that equipment B frequency level is higher than the frequency level of device A, when equipment B is identical with the time grade of device A, current Time synchronization algorithm may cause：Time synchronized path is that A tracks B.Above so that device A can not obtain the precision higher calibrated time.

It is different with the frequency level of two equipment, and time grade it is identical exemplified by illustrate.As shown in figure 4, device A frequency level is that (frequency accuracy is generally 10 to synchronous ether clock (synchronous Ethernet Equipment Clock, EEC)^-6, i.e., error per second is 10^-6S), equipment B frequency levels are that (frequency accuracy is generally 10 to primary reference clock (Primary Reference Clock, PRC)^-11, i.e., error per second is 10^-11S), wherein PRC grades are higher than EEC grades.The time grade of device A and equipment B time grade are all 187, and oversampling clock mark (clockID) is not different, and clockID sizes are pre-seted, and the quality of synchronization accuracy is not represented.

The Frequency Synchronization SSM algorithms G.781 and G.8264 defined according to ITU, Frequency Synchronization path is that A tracks B.And according to the A-BMCA algorithms that G.8275.1 ITU defines in the BMCA algorithms defined of IEEE 1588-2008 in above-mentioned Fig. 2 and Fig. 3, because time grade clockClass is 187, then BMCA algorithms and A-BMCA algorithms can all compare which minimum of clockID.Due to the clockID of device A：0x0001, less than equipment B clockID：0x0002, so that time synchronized path, which is B, tracks A.At this moment equipment B time can be synchronized with the time of device A, and the time precision of output is also 10^-6, rather than itself 10 of equipment B^-11Precision.It is final to realize the timing tracking accuracy that end base station equipment receives difference.

The defect of Frequency Synchronization credit rating is not accounted for for existing Time synchronization algorithm BMCA and A-BMCA, the embodiment of the present invention is proposed in Time synchronization algorithm BMCA, need to consider the influence of frequency level in A-BMCA and other Time synchronization algorithms.

The synchronous method of the embodiment of the present invention can make it that time synchronized path also tracks A for B in figure 4 above so that equipment B and the time precision of device A output are all 10^-11Magnitude.

Fig. 5 is the method schematic diagram of time synchronized according to an embodiment of the invention.Method as shown in Figure 5 is performed by the first clock.First clock can be located in first node, and second clock can be located in Section Point.Wherein, first node and Section Point can be adjacent two transmission node in Fig. 1 scenes.Specifically, method as shown in Figure 5 can include：

510, the first clock receives the first information and the second information that second clock is sent, and the first information is used for the time grade for indicating the second clock, and second information is used for the frequency level for indicating the second clock.

520, first clock compares the frequency level of the frequency level of first clock and the second clock after it is determined that the time grade of first clock and the time grade of the second clock are equal, obtains the first comparative result.

530, first clock according to first comparative result determine whether using the second clock as first clock master clock.

For example, 520 when implementing, and frequency level and the frequency level of the second clock of the first clock ratio first clock are that first clock determines to perform after the time grade of first clock is equal with the time grade of the second clock.In addition, first clock obtains first comparative result by the frequency level of the frequency level and the second clock of relatively more described first clock.

Therefore, the embodiment of the present invention is by the case of the time grade identical of two clocks, the frequency level of comparison clock, and according to comparative result determine whether using a clock as another clock master clock.That is, determining to consider frequency level this factor before master clock.Therefore, above-mentioned technical proposal contributes to the master clock for selecting quality higher.Or, above-mentioned technical proposal helps avoid the master clock for selecting quality relatively low.Determine after master clock, also determined that from the time synchronized path of clock from clock.Therefore, above-mentioned technical proposal helps to set up the higher time synchronized path of quality.Or, above-mentioned technical proposal helps avoid setting up the relatively low time synchronized path of quality.

It should be understood that in embodiments of the present invention, the time grade being related to can include：The variance yields (GM offsetScaledLogVariance) of the deviation of the big clock grade (GM clockClass) of master clock, the clock accuracy (GM clockAccuracy) of big master clock and big master clock.On above-mentioned time grade, the A-BMCA algorithms that G.8275.1 the BMCA algorithms and ITU that IEEE 1588-2008 define define are refer to.

The first information in the embodiment of the present invention is referred to as time class information, and the second information is referred to as frequency level information.

Specifically, being sent mutually in the embodiment of the present invention, between the first clock and second clock includes the message for time synchronized of time class information and frequency level information.Then time tracking is carried out, for example it is described by taking the angle of the first clock as an example as follows, after the first clock receives the message of second clock, the time grade of the temporal quality grade and local device (the first clock) of the second clock received can be compared.When the time grade of second clock is higher than the time grade of the first clock, the time of the first clock tracing second clock.Opposite, when the time grade of the first clock is higher than the time grade of second clock, second clock tracks the time of the first clock.When the time grade of two clocks is equal, first clock can compare the frequency level of the frequency level of the first clock and second clock, obtain the first comparative result.First clock according to the first comparative result determine whether using the second clock as first clock master clock.Whether track the time of the second clock really according to the first comparative result.

For example, determining the second clock that as after the master clock of first clock the first clock can track the time of second clock according to first comparative result in the first clock.Specifically, in the first clock using second clock as after the master clock (i.e. the first clock be from clock, second clock is master clock) of the first clock, the message for time synchronized can be interacted between the first clock and second clock.The message for being used for time synchronized can be accurate clock synchronization protocol (Precision Time Protocol, PTP) message.Such as PTP message can include synchronous (Sync) message, tracking (Follow_Up) message, delay request (Delay-Req) message and delay response (Delay_Resp) message.The deviation (Offset) of time can be calculated based on the message for being used for time synchronized.First clock is obtained after Offset, and the time of the first clock can be calibrated according to Offset.

It should also be understood that in embodiments of the present invention, time class information and frequency level information that second clock is sent can be specifically the time class information and frequency level information of second clock itself.When second clock has tracked the time of other clocks, the time class information and frequency level information that second clock is sent can be the time class information and frequency level information of the clock of second clock tracking.Can also be the time class information and frequency level information of other clocks itself.The time class information and frequency level information that second clock is sent in above-mentioned two situations in present example are properly termed as the time class information and frequency level information of second clock.

A kind of situation, first comparative result indicates that the frequency level of first clock is less than the frequency level of the second clock.

Correspondingly, in 530, first clock according to first comparative result using the second clock as first clock master clock.

Alternately, another situation, first comparative result indicates that the frequency level of first clock is higher than the frequency level of the second clock.

Correspondingly, in 530, first clock according to first comparative result avoid using the second clock as first clock master clock.

In other words, in the case of time grade identical, the frequency level of the first clock is higher than the frequency level of second clock.Then the time precision of the first clock is higher than the time precision of second clock.So second clock need using first clock as the second clock master clock.

Alternately, the third situation, first comparative result indicates that the frequency level of first clock is equal to the frequency level of the second clock.Present invention method also includes：First clock receives the second configuration information of second clock transmission, and second configuration information includes at least one in the identity of the priority one of big master clock, the priority two of big master clock and big master clock of the second clock.

Correspondingly, in 530, first clock obtains the second comparative result it is determined that after first comparative result, the first configuration information of first clock is compared by first clock with second configuration information.And according to second comparative result determine whether using the second clock as first clock master clock.Wherein, first configuration information includes at least one in the identity of the priority one of big master clock, the priority two of big master clock and big master clock of first clock.

It should be understood that, in the embodiment of the present invention, the A-BMCA algorithms G.8275.1 defined similar to ITU, or, the BMCA algorithms defined similar to IEEE 1588-2008, the configuration information can include at least one in the local first level of the priority one of big master clock, the priority two of big master clock, the identity of big master clock and local clock and the local first level of port.Specifically how time synchronized is carried out according to configuration information and be referred to two standards, here is omitted.

Accordingly, as another embodiment, when time class information and frequency level information can be by a message bearings.The first node receives time class information and the frequency level information that Section Point is sent, including：The first node receives the message for time synchronized that Section Point is sent, and the message includes the time class information and frequency level information.

Alternatively, as another embodiment, the message for time synchronized in the embodiment of the present invention can be notice Announce message,

Or,

Second information of the second clock is carried in the reserve bytes of the message field of the Announce message,

Or, the second information of the second clock is carried in Type Length value (Type, Length, Value, TLV) field in the Announce message.

Specifically, the time class information and other information that G.8275.1 IEEE 1588-2008 and ITU are used to compare are by Announce message transmissions to opposite equip..Wherein the form of Announce message as shown in Table 1 and Table 2, wherein, table 1 for Announce message message header in content, (referring to IEEE 1588-2008 tables 18).Table 2 is the message header of Announce message and the content of message field, (referring to IEEE 1588-2008 tables 25).

Table 1, Announce message headers

Table 2, Announce message headers and message field

Second information, i.e. frequency level information can be represented only with 4 bits.The embodiments of the invention provide following three kinds of implementations：

The first, the second information is put into the message header of Announce message.

As shown in Table 1, the 5th byte of Announce message headers and the 16th~19 byte are reserve bytes, and one of byte can be selected to be used for the second information for transmitting clock.

Second, the second information is put into the message field (message field) of Announce message.

As shown in Table 2, the 46th byte of Announce message is reserve bytes, can be used for the second information for transmitting clock.

The third, can predefine TLV fields (the privately owned TLV defined) in Announce message in the embodiment of the present invention, the field is used to transmit the second information.

Specifically, IEEE 1588-2008 are defined, and other standards based on IEEE 1588-2008 can define privately owned TLV.The TLV call formats of wherein normal structure extension are (see IEEE 1588-2008 forms 35) as shown in table 3：

Table 3, the TLV forms of IEEE 1588-2008 requirements

Each field contents of the corresponding TLV of the second information in the embodiment of the present invention can be as follows：

Type Length value type (tlvType)：According to IEEE 1588-2008 forms 34, this field value is 3.

TLV length fields section (lengthField)：According to IEEE 1588-2008 14.3.2.2 chapters and sections requirement, this field is 6+N.Because the second information only needs to take 1 byte, i.e. N=1, therefore this field value 7.Interchangeable, N can also be greater than 1 integer.

Organization number (organizationID)：Produced according to the OUI codes of normal structure or equipment.

Organize subtype (organizationSubType)：Formulated by normal structure or equipment vendor.

Data field (dataField)：This field is the second information (can be 1 byte), and specific value reference ITU is G.781.Interchangeable, the second information can also be multiple bytes.

It should be understood that above-mentioned TLV form is schematically, the TLV in the embodiment of the present invention can also follow other forms.The experimental TLV that such as IEEE 1588-2008 14.2 chapters and sections are defined, the embodiment of the present invention is not limited to this.

Alternatively, as another embodiment, present invention method can also include：

The frequency level information of the second clock is stored in clock quality clockQuality data sets by first clock.

After the time of the first clock tracing second clock, when first clock and the 3rd clock carry out time synchronized, the frequency level information of the second clock is sent to the 3rd clock.Time synchronizing is carried out according to the frequency level information of the second clock to trigger the 3rd clock.

For example, the clock quality data set can be the clock quality data set that Precision Time Protocol (Precision Time Protocol, PTP) is defined.It can be IEEE 1588v1 or IEEE 1588-2008 that the PTP, which can be,.

Specifically, after first clock receives the Announce message of second clock, the frequency level information of the second clock is stored in the local clockQuality data sets of the first clock.Then the grade to the first clock and second clock is compared.After the first clock determines the time of tracking second clock, the frequency level information of the second clock can be retained in the local clockQuality data sets (data sets) of the first clock.And when first clock and the 3rd clock carry out time synchronized, the frequency level information of the second clock is sent to the 3rd clock.Time synchronizing is carried out according to the frequency level information of the second clock to trigger the 3rd clock.When the first clock determines the time without tracking second clock, the frequency level information of the second clock can be deleted from the local clockQuality data sets of the first clock.And when first clock and the 3rd clock carry out time synchronized, the frequency level information of first clock is still sent to the 3rd clock.Time synchronizing is carried out according to the frequency level information of first clock to trigger the 3rd clock.

For example, equipment (such as the first clock) is received after the second information of miscellaneous equipment (such as second clock), it is necessary to add local data sets.Because the clockQuality of the existing IEEE 1588-2008 acquiescence local data sets (defaultDS) defined and the big master clock quality (grandmasterclockQuality) of host node data set (parentDS) have included the variance yields (offsetScaledLogVariance) of clock grade (clockClass), clock accuracy (clockAccuracy) and deviation.Therefore, the embodiment of the present invention can add the second information in clockQuality data sets.Specifically, the clockQuality in present example is as follows：

It should be understood that the processing (for example, storage, deletion etc.) in the embodiment of the present invention to time class information and configuration information, is referred to the mechanism that IEEE 1588-2008 are defined, here is omitted.

The method for time synchronized of the embodiment of the present invention is described above in conjunction with Fig. 5, with reference to Fig. 6 and Fig. 7 specific examples, the possible implementation of the method for time synchronized shown in Fig. 5 is described in detail.

Fig. 6 is the method schematic diagram of time synchronized according to another embodiment of the present invention.As shown in fig. 6, device A and equipment B receive mutually other side include the first information (time class information), the second information (frequency level information) and the message for time synchronized of configuration information after, progress time tracking.Wherein, the first information includes：The variance yields (GM offsetScaledLogVariance) of the time deviation of the big grade (GM class) of master clock, the precision (GM accuracy) of big master clock and big master clock.Second information includes：The Frequency Synchronization credit rating (GM SSM) of big master clock；Configuration information includes：The identity (GM identity, GM ID) of the big priority one (GM priroty1) of master clock, the priority two (GM priority2) of big master clock and big master clock.Specifically, as shown in fig. 6, the step of device A and equipment B need to carry out following time synchronized：

601, judge whether the ID of device A and equipment B big master clock is equal.If it is it can determine to carry out time synchronized according to existing mode, here is omitted.If unequal, 602 are performed.

602, compare the priority one of device A and equipment B big master clock.If A>B, then perform step 609.Step 603 is performed if A=B, if A<B, then perform step 610.

603, compare the grade of device A and equipment B big master clock.If A>B, then perform step 609.Step 604 is performed if A=B, if A<B, then perform step 610.

604, compare the precision of device A and equipment B big master clock,.If A>B, then perform step 608.Step 605 is performed if A=B, if A<B, then perform step 609.

605, compare the variance yields of device A and the deviation of equipment B big master clock.If A>B, then perform step 609.Step 606 is performed if A=B, if A<B, then perform step 610.

606, compare the Frequency Synchronization credit rating of device A and equipment B master clock source.If A>B, then perform step 609.Step 607 is performed if A=B, if A<B, then perform step 610.

607, compare the priority two of device A and equipment B master clock source.If A>B, then perform step 609.Step 608 is performed if A=B, if A<B, then perform step 610.

608, compare the ID of device A and equipment B master clock source value.If A>B, then perform step 609.If A<B, then perform step 610.

609, device A tracking equipment B time.

610, equipment B tracking equipments A time.

It should be noted that the method shown in Fig. 6 can regard the improvement of the BMCA algorithms defined to IEEE 1588-2008 as, it is the comparison that the second information (frequency level information) is added on the basis of existing BMCA algorithms.Specifically, step 601-605 is corresponding with the step 201-205 in Fig. 2, and 607-610 is corresponding with 206-209, and here is omitted.Due to when carrying out time synchronized, it is contemplated that the precision of frequency, and then the more excellent path of precision can be selected, so as to lift the timing tracking accuracy of output.

Fig. 7 is the method schematic diagram according to another embodiment of the present invention for time synchronized.As shown in fig. 7, device A and equipment B receive mutually other side include the first information (time class information), the second information (frequency level information) and the message for time synchronized of configuration information after, progress time tracking.Wherein, the first information includes：The variance yields (GM offsetScaledLogVariance) of the deviation of the big clock grade (GM clockClass) of master clock, the clock accuracy (GM clockAccuracy) of big master clock and big master clock.Second information includes：The Frequency Synchronization credit rating (GM SSM) of big master clock.Configuration information includes：The clock ID (GM identity) of the priority two (GM priority2) of big master clock, the local first level (localPriority) of port and big master clock.Specifically, as shown in figure 3, the step of device A and equipment B need to carry out following time synchronized：

701, compare the clock grade of device A and equipment B big master clock.If A>B, then perform step 709.Step 702 is performed if A=B, if A<B, then perform step 710.

702, compare the clock accuracy of device A and equipment B big master clock.If A>B, then perform step 709.Step 707 is performed if A=B, if A<B, then perform step 710.

703, compare the variance yields of device A and the deviation of equipment B big master clock.If A>B, then perform step 709.Step 704 is performed if A=B, if A<B, then perform step 710.

704, compare the Frequency Synchronization credit rating of device A and equipment B big master clock.If A>B, then perform step 709.Step 705 is performed if A=B.If A<B, then perform step 710.

705, compare the priority two of device A and equipment B big master clock.If A>B, then perform step 709.Step 706 is performed if A=B.If A<B, then perform step 710.

706, compare device A and equipment B port local first level.If A>B, then perform step 709.If A=B, step 707 is performed.If A<B, then perform step 710.

707, judge whether device A and equipment B clock grade are less than or equal to 127.If it is it can determine to carry out time synchronized according to existing mode, here is omitted.If it is not, then performing 708.

708, compare the clock ID of device A and equipment B master clock source value.If A>B, then perform step 709.If A<B, then perform step 710.If A=B, it can determine to carry out time synchronized according to existing mode, here is omitted.

709, device A tracking equipment B time.

710, equipment B tracking equipments A time.

It should be noted that the method shown in Fig. 7 can regard the improvement of the A-BMCA algorithms G.8275.1 defined to ITU as, it is the comparison that the second information (frequency level information) is added on the basis of the A-BMCA algorithms that G.8275.1 ITU defines.Specifically, step 701-703 is corresponding with the step 301-303 in Fig. 3, and 705-708 is corresponding with 304-307, and here is omitted.Due to when carrying out time synchronized, it is contemplated that the precision of frequency, and then the more excellent path of precision can be selected, so as to lift the timing tracking accuracy of output.

It should be noted that figure 6 above and Fig. 7 example are just for the sake of helping skilled in the art to understand the embodiment of the present invention, and the embodiment of the present invention have to be limited to illustrated concrete numerical value or concrete scene.Those skilled in the art are according to actual conditions, it is clear that can carry out various modifications or change of equal value, and such modification or change are also fallen into the range of the embodiment of the present invention.

The method of the time synchronized of the embodiment of the present invention is described in detail above in conjunction with Fig. 1 to Fig. 7, the equipment that the time synchronized of the embodiment of the present invention is described with reference to Fig. 8 to Fig. 9.

Fig. 8 is the schematic block diagram of the clock according to an embodiment of the invention for time synchronized.Clock shown in Fig. 8 is the first clock, and the first clock can be the clock in any one first transmission node in Fig. 1 scenes.Second clock can be the clock in the Section Point in Fig. 1 scenes, and first node and Section Point can be two intermediate transmission nodes of the arbitrary neighborhood in Fig. 1 scenes.

It should be understood that the first clock 800 shown in Fig. 8 can realize each process being used in method for synchronizing time being related in Fig. 5 embodiments.The operation and/or function of modules in first clock 800, respectively in order to realize the corresponding flow in the embodiment of the method in Fig. 5.The description in above method embodiment is for details, reference can be made to, to avoid repeating, description is described in detail in appropriate omit herein.

Specifically, the first clock 800 shown in Fig. 8 includes：First receiving unit 810 and comparing unit 820 and determining unit 830.

First receiving unit 810 is used for the first information and the second information for receiving second clock transmission, and the first information is used for the time grade for indicating the second clock, and second information is used for the frequency level for indicating the second clock.

Comparing unit 820 is used for after it is determined that the time grade of first clock and the time grade of the second clock are equal, and the frequency level of the frequency level of first clock and the second clock is compared, and obtains the first comparative result.

Determining unit 830 be used for according to first comparative result determine whether using the second clock as first clock master clock.

Further, it is used as another embodiment, when first comparative result indicate first clock frequency level be less than the second clock frequency level when, the determining unit 830 specifically for according to first comparative result using the second clock as first clock master clock.

Alternately, it is used as another embodiment, when first comparative result indicate first clock frequency level be higher than the second clock frequency level when, the determining unit 830 specifically for according to first comparative result determine avoid using the second clock as first clock master clock.

Alternately, as another embodiment, first clock also includes：Second receiving unit, the second configuration information for receiving second clock transmission, second configuration information includes at least one in the identity of the big master clock of the priority one, the priority two of the big master clock of the second clock and the second clock of the big master clock of the second clock

Wherein, when first comparative result indicates that the frequency level of first clock is equal to the frequency level of the second clock, the determining unit 830 is specifically for after the comparing unit obtains first comparative result, first configuration information of first clock is compared with second configuration information, obtain the second comparative result, and according to second comparative result determine whether using the second clock as first clock master clock, first configuration information includes the priority one of the big master clock of first clock, at least one in the identity of the priority two of the big master clock of first clock and the big master clock of first clock.

Alternatively, as another embodiment, the first receiving unit 810 includes the first information and second information specifically for receiving the message for time synchronized that the second clock is sent, the message.

Alternatively, as another embodiment, the message is notifies Announce message, and the second information of the second clock is carried in the reserve bytes of the message header of the Announce message；Or, the second information of the second clock is carried in the reserve bytes of the message field of the Announce message；Or, the second information of the second clock is carried in the Type Length value TLV fields in the Announce message.

Alternatively, as another embodiment, first clock also includes：

Memory cell, for the second information of the second clock to be stored in Precision Time Protocol PTP clock quality clockQuality data sets；

Transmitting element, after for time when first clock tracing second clock, the second information of the second clock is sent to the 3rd clock.

Alternatively, as another embodiment, the first information includes：At least one in the variance yields of the time deviation of the big master clock of the grade of the big master clock of the second clock, the precision of the big master clock of the second clock and the second clock.

Fig. 9 is the schematic block diagram of the equipment according to an embodiment of the invention for time synchronized.Clock shown in Fig. 9 is the first clock, first clock can be the clock in any one first transmission node in Fig. 1 scenes, second clock can be the clock in the Section Point in Fig. 1 scenes, and first node and Section Point can be two intermediate transmission nodes of the arbitrary neighborhood in Fig. 1 scenes.

It should be understood that, the first clock 900 shown in Fig. 9 can realize each process in the method for synchronizing time being related in Fig. 5 embodiments, the operation and/or function of modules in first clock 900, respectively in order to realize the corresponding flow in the embodiment of the method in Fig. 5, it for details, reference can be made to the description in above method embodiment, to avoid repeating, description is described in detail in appropriate omit herein.

The first clock 900 shown in Fig. 9 includes processor 910 and memory 920, alternatively, can also include bus system 930 and transceiver 940.Wherein, transceiver 940 is used to receive the first information and the second information that second clock is sent, and the first information is used for the time grade for indicating the second clock, and second information is used for the frequency level for indicating the second clock.Processor 910 is connected with memory 920 by bus system 930, the memory 920 is used for store instruction, the processor 910 is used for the instruction for performing the memory 920 storage after it is determined that the time grade of first clock and the time grade of the second clock are equal, the frequency level of the frequency level of first clock and the second clock is compared, the first comparative result is obtained；And according to first comparative result determine whether using the second clock as first clock master clock.

The method that the embodiments of the present invention are disclosed can apply in processor 910, or be realized by processor 910.Processor 910 is probably a kind of IC chip, the disposal ability with signal.In implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 910 or the instruction of software form.Above-mentioned processor 910 can be general processor, digital signal processor (Digital Signal Processor, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), field programmable gate array (Field Programmable Gate Array, FPGA) or other PLDs, discrete gate or transistor logic, discrete hardware components.It can realize or perform disclosed each method, step and the logic diagram in the embodiment of the present invention.General processor can be microprocessor or the processor can also be any conventional processor etc..The step of method with reference to disclosed in the embodiment of the present invention, can be embodied directly in hardware decoding processor and perform completion, or perform completion with the hardware in decoding processor and software module combination.Software module can be located at random access memory (Random Access Memory, RAM), in the ripe storage medium in this area such as flash memory, read-only storage (Read-Only Memory, ROM), programmable read only memory or electrically erasable programmable memory, register.The storage medium is located at memory 920, processor 910 reads the information in memory 920, the step of completing the above method with reference to its hardware, the bus system 930 can also include power bus, controlling bus and status signal bus in addition etc. in addition to including data/address bus.But for the sake of clear explanation, various buses are all designated as bus system 930 in figure.

Further, it is used as another embodiment, when first comparative result indicate first clock frequency level be less than the second clock frequency level when, the processor 910 specifically for according to first comparative result using the second clock as first clock master clock.

Alternately, as another embodiment when first comparative result indicate first clock frequency level be higher than the second clock frequency level when, processor 910 specifically for according to first comparative result determine avoid using the second clock as first clock master clock.

Alternately, it is used as another embodiment, the transceiver 940 is additionally operable to receive the second configuration information that the second clock is sent, and second configuration information includes at least one in the identity of the big master clock of the priority one, the priority two of the big master clock of the second clock and the second clock of the big master clock of the second clock.

Wherein, when first comparative result indicates that the frequency level of first clock is equal to the frequency level of the second clock, the processor 910 is specifically for after the comparing unit obtains first comparative result, first configuration information of first clock is compared with second configuration information, obtain the second comparative result, and according to second comparative result determine whether using the second clock as first clock master clock, first configuration information includes the priority one of the big master clock of first clock, at least one in the identity of the priority two of the big master clock of first clock and the big master clock of first clock.

Alternatively, as another embodiment, transceiver 940 includes the first information and second information specifically for receiving the message for time synchronized that the second clock is sent, the message.

Alternatively, as another embodiment, processor 910 is used to the second information of the second clock being stored in Precision Time Protocol PTP clock quality clockQuality data sets.

Transceiver 940 is additionally operable to that after the time of first clock tracing second clock, the second information of the second clock is sent to the 3rd clock.

The embodiment of the present invention additionally provides a kind of first device, including such as the first clock in Fig. 8 or Fig. 9.The first device can be with the base station in Fig. 1 scenes, terminal, transmission node etc..

Eighth aspect is there is provided a kind of network system, including first device and second device, and first device is included such as the first clock in Fig. 8 or Fig. 9, second device include to this first when send the second clock of message for time synchronized.

It should be understood that during " one embodiment " or " embodiment " for being mentioned in specification means that the special characteristic relevant with embodiment, structure or characteristic are included at least one embodiment of the present invention.Therefore, " in one embodiment " or " in one embodiment " occurred everywhere in entire disclosure not necessarily refers to identical embodiment.In addition, these specific feature, structure or characteristics can be combined in one or more embodiments in any suitable manner.It should be understood that, in various embodiments of the present invention, the size of the sequence number of above-mentioned each process is not meant to the priority of execution sequence, and the execution sequence of each process should be determined with its function and internal logic, and any limit is constituted without tackling the implementation process of the embodiment of the present invention.

In addition, the terms " system " and " network " are often used interchangeably herein.The terms "and/or", only a kind of incidence relation for describing affiliated partner, represents there may be three kinds of relations, for example, A and/or B, can be represented：Individualism A, while there is A and B, these three situations of individualism B.In addition, character "/" herein, it is a kind of relation of "or" to typically represent forward-backward correlation object.

It should be understood that in embodiments of the present invention, " B " corresponding with A represents that B is associated with A, and B can be determined according to A.It is also to be understood that determining that B is not meant to determine B only according to A according to A, B can also be determined according to A and/or other information.

Those of ordinary skill in the art can be appreciated that, the unit and algorithm steps of each example described with reference to the embodiments described herein, it can be realized with electronic hardware, computer software or the combination of the two, in order to clearly demonstrate the interchangeability of hardware and software, the composition and step of each example are generally described according to function in the above description.These functions are performed with hardware or software mode actually, depending on the application-specific and design constraint of technical scheme.Professional and technical personnel can realize described function to each specific application using distinct methods, but this realization is it is not considered that beyond the scope of this invention.

It is apparent to those skilled in the art that, for convenience of description and succinctly, the specific work process of the system of foregoing description, device and unit may be referred to the corresponding process in preceding method embodiment, will not be repeated here.

In several embodiments provided herein, it should be understood that disclosed systems, devices and methods, it can realize by another way.For example, device embodiment described above is only schematical, for example, the division of unit, it is only a kind of division of logic function, there can be other dividing mode when actually realizing, such as multiple units or component can combine or be desirably integrated into another system, or some features can be ignored, or do not perform.In addition, shown or discussed coupling or direct-coupling or communication connection each other can be by the INDIRECT COUPLING of some interfaces, device or unit or communication connection or electricity, mechanical or other forms are connected.

The unit illustrated as separating component can be or may not be physically separate, and the part shown as unit can be or may not be physical location, you can with positioned at a place, or can also be distributed on multiple NEs.Some or all of unit therein can be selected to realize the purpose of scheme of the embodiment of the present invention according to the actual needs.

In addition, each functional unit in each embodiment of the invention can be integrated in a processing unit or unit is individually physically present or two or more units are integrated in a unit.Above-mentioned integrated unit can both be realized in the form of hardware, it would however also be possible to employ the form of SFU software functional unit is realized.

Through the above description of the embodiments, it is apparent to those skilled in the art that the present invention can be realized with hardware, or firmware is realized, or combinations thereof mode is realized.When implemented in software, above-mentioned functions can be stored in computer-readable medium or be transmitted as one or more instructions on computer-readable medium or code.Computer-readable medium includes computer-readable storage medium and communication media, and wherein communication media includes being easy to any medium that computer program is transmitted from a place to another place.Storage medium can be any usable medium that computer can be accessed.As example but it is not limited to：Computer-readable medium can include RAM, ROM, EEPROM, CD-ROM or other optical disc storages, magnetic disk storage medium or other magnetic storage apparatus or can be used in carrying or store with instruct or data structure form desired program code and can by computer access any other medium.In addition.Any connection can be suitably turn into computer-readable medium.For example, if software is to be transmitted using coaxial cable, optical fiber cable, twisted-pair feeder, Digital Subscriber Line (DSL) or such as wireless technology of infrared ray, radio and microwave etc from website, server or other remote sources, then the wireless technology of coaxial cable, optical fiber cable, twisted-pair feeder, DSL or such as infrared ray, wireless and microwave etc be included in belonging to medium it is fixing in.As used in the present invention, disk (Disk) and dish (disc) include compression laser disc (CD), laser disc, laser disc, Digital Versatile Disc (DVD), floppy disk and Blu-ray Disc, the replicate data of the usual magnetic of which disk, and dish is then with laser come optical replicate data.Above combination above should also be as being included within the protection domain of computer-readable medium.

In a word, the preferred embodiment of technical solution of the present invention is the foregoing is only, is not intended to limit the scope of the present invention.Within the spirit and principles of the invention, any modification, equivalent substitution and improvements made etc., should be included in the scope of the protection.

Claims

1. a kind of method for time synchronized, it is characterised in that including：

First clock receives the first information and the second information that second clock is sent, and the first information is used for The time grade of the second clock is indicated, second information is used for the frequency for indicating the second clock Grade；

First clock is it is determined that time grade and the time of the second clock of first clock After grade is equal, the frequency level of the frequency level of first clock and the second clock is done into ratio Compared with the first comparative result of acquisition；

First clock determines whether to regard the second clock as institute according to first comparative result State the master clock of the first clock.

2. according to the method described in claim 1, it is characterised in that

When first comparative result indicates that the frequency level of first clock is less than the second clock Frequency level when,

First clock determines whether to regard the second clock as institute according to first comparative result The master clock of the first clock is stated, including：

First clock according to first comparative result using the second clock as described first when The master clock of clock.

3. according to the method described in claim 1, it is characterised in that

When first comparative result indicates that the frequency level of first clock is higher than the second clock Frequency level when,

First clock determines to avoid regarding the second clock as institute according to first comparative result State the master clock of the first clock.

4. according to the method described in claim 1, it is characterised in that methods described also includes：

First clock receives the second configuration information that the second clock is sent, and described second matches somebody with somebody confidence Breath include the priority one of big master clock of the second clock, the big master clock of the second clock it is excellent At least one in the identity of the big master clock of first level two and the second clock,

Wherein, when first comparative result indicates that the frequency level of first clock is equal to described second During the frequency level of clock, first clock is determined whether described according to first comparative result Two nodes as the first node master clock, including：

First clock is after first comparative result is obtained, when first clock is by described first First configuration information of clock is compared with second configuration information, obtains the second comparative result；

First clock determines whether to regard the second clock as institute according to second comparative result The master clock of the first clock is stated, first configuration information includes the excellent of the big master clock of first clock The big master clock of first level one, the priority two of the big master clock of first clock and first clock At least one in identity.

5. method according to any one of claim 1 to 4, it is characterised in that described first Clock receives the first information and the second information that second clock is sent, including：

First clock receives the message for time synchronized that the second clock is sent, the message Including the first information and second information.

6. method according to claim 5, it is characterised in that the message is notice Announce Message,

Second information of the second clock is carried on the reserved word of the message header of the Announce message In section,

Or,

Second information of the second clock is carried on the reserved word of the message field of the Announce message In section,

Or, the type that the second information of the second clock is carried in the Announce message is long Spend in value TLV fields.

7. method according to any one of claim 1 to 6, it is characterised in that methods described Also include：

Second information of the second clock is stored in clock quality clockQuality by first clock In data set；

After the time of second clock described in first clock tracing, the clock of clockwise the 3rd when described first Send the second information of the second clock.

8. method according to any one of claim 1 to 7, it is characterised in that

The first information includes：The clock grade clockClass of the big master clock of the second clock, The clock accuracy clockAccuracy of the big master clock of the second clock and the big master of the second clock At least one in the variance yields offsetScaledLogVariance of the time deviation of clock.

9. a kind of the first clock for time synchronized, it is characterised in that including：

First receiving unit, the first information and the second information for receiving second clock transmission, described the One information is used for the time grade for indicating the second clock, and second information is used to indicate described second The frequency level of clock；

Comparing unit, for it is determined that time grade and the time of the second clock of first clock After grade is equal, the frequency level of the frequency level of first clock and the second clock is done into ratio Compared with the first comparative result of acquisition；

Determining unit, for being determined whether to regard the second clock as institute according to first comparative result State the master clock of the first clock.

10. the first clock according to claim 9, it is characterised in that

The determining unit according to first comparative result specifically for regarding the second clock as institute State the master clock of the first clock.

11. the first clock according to claim 9, it is characterised in that

When the determining unit according to first comparative result specifically for determining to avoid described second Clock as first clock master clock.

12. the first clock according to claim 9, it is characterised in that first clock is also wrapped Include：

Second receiving unit, for receiving the second configuration information that the second clock is sent, described second The priority one of the big master clock of configuration information including the second clock, the second clock it is big main when At least one in the identity of the priority two of clock and the big master clock of the second clock,

Wherein, when first comparative result indicates that the frequency level of first clock is equal to described second During the frequency level of clock, the determining unit in the comparing unit specifically for obtaining first ratio After result, the first configuration information of first clock is compared with second configuration information, Obtain the second comparative result, and according to second comparative result determine whether using the second clock as The master clock of first clock, first configuration information includes the big master clock of first clock The big master clock of priority one, the priority two of the big master clock of first clock and first clock Identity at least one.

13. the first clock according to any one of claim 9 to 12, it is characterised in that the One receiving unit is described to disappear specifically for receiving the message for time synchronized that the second clock is sent Breath includes the first information and second information.

14. the first clock according to claim 13, it is characterised in that the message is notice Announce message,

Or,

15. the first clock according to any one of claim 9 to 14, it is characterised in that institute Stating the first clock also includes：

Memory cell, for the second information of the second clock to be stored in into clock quality clockQuality In data set；

Transmitting element, for when the time of second clock described in first clock tracing after, during to the 3rd Clock sends the second information of the second clock.

16. the first clock according to any one of claim 9 to 15, it is characterised in that