CN108319762B - Clock area support-based sectional programmable clock network structure - Google Patents

Clock area support-based sectional programmable clock network structure Download PDF

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CN108319762B
CN108319762B CN201810014415.2A CN201810014415A CN108319762B CN 108319762 B CN108319762 B CN 108319762B CN 201810014415 A CN201810014415 A CN 201810014415A CN 108319762 B CN108319762 B CN 108319762B
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clock
distribution
wiring
node
programmable
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CN108319762A (en
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徐彦峰
范继聪
胡凯
张艳飞
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Wuxi Zhongwei Yixin Co Ltd
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Wuxi Zhongwei Yixin Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

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Abstract

The invention discloses a clock region support-based sectional programmable clock network structure, which comprises a wiring clock and a distribution clock, wherein the wiring clock ensures the same path delay from a clock source to root clock nodes in different clock regions through the programmable characteristic, thereby providing a high-performance clock signal with the skew of almost zero. N wiring clocks and n distribution clocks respectively traverse each clock region in the vertical direction and the horizontal direction, and the value of n is adjustable. The wiring clock is connected with the clock input port, the clock signal is sent to a clock root node in the clock area, and then the clock signal is sent to all parts of the clock area through the distribution clock. The inside of the clock region adopts a fishbone type clock network structure, and each leaf node clock is driven by distribution clock enabling. The invention is suitable for large-scale high-performance FPGA, can provide low-offset high-performance clock signals, and meets the requirement of large-scale FPGA chips on high-performance clocks.

Description

Clock area support-based sectional programmable clock network structure
Technical Field
The invention relates to a clock network structure suitable for a large-scale FPGA (field programmable gate array) structure, in particular to a clock region support-based sectional programmable clock network structure, and belongs to the technical field of programmable logic devices.
Background
An FPGA (Field-Programmable Gate Array) device has the advantages of short development period, low cost, low risk, high integration level, high flexibility, and convenience for electronic system maintenance and upgrade, so that it is popular with users of terminal products, becomes the mainstream of an integrated circuit chip, is widely applied in various fields, such as communication, control, video, information processing, electronics, internet, automobile, aerospace, etc., and is also widely applied in prototype verification of an integrated circuit to shorten the product development time.
With the continuous improvement of the process level, the FPGA has larger and larger scale, higher and higher working frequency and higher requirements on the structure of a clock network. Currently, a double-layer fishbone clock network structure is generally adopted by an FPGA, the clock network structure fans out a clock from a geometric center of the FPGA structure, global clock resource fan-out from a device center to an FPGA edge is supported, and offset (skew) is accumulated all the time. However, as the scale and performance of the FPGA are continuously improved, the clock skew may be accumulated to cause a large negative impact on the overall timing budget of the design, so a clock network structure capable of effectively reducing the clock skew needs to be designed.
The double-layer fishbone clock network structure has the advantages of simple structure, obvious layers, good conformity with programmable resources, layout wiring area saving, easy expansion and the like, and has great advantages in a small-capacity FPGA. However, due to the clock skew accumulation characteristic of the architecture, the working frequency of the clock is often limited when the architecture is applied to a high-capacity and high-performance FPGA. Therefore, a low skew clock network structure suitable for large-scale high-performance FPGAs needs to be designed.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the structure is suitable for large-scale high-performance FPGA, can provide a low-offset high-performance clock signal, and meets the requirement of large-scale FPGA chips on high-performance clocks.
The invention adopts the following technical scheme for solving the technical problems:
a clock area support segmented programmable clock network structure is characterized in that an FPGA chip is divided into a plurality of clock areas with the same size according to the size of the FPGA chip, the clock areas are arranged in an array mode, and adjacent clock areas are spliced together; the programmable clock network structure comprises a wiring clock at the top layer of a clock area, a distribution clock and a fishbone clock structure in the clock area, wherein the wiring clock comprises a horizontal wiring clock and a vertical wiring clock, the distribution clock comprises a horizontal distribution clock and a vertical distribution clock, the wiring clock comprises a fixed delay clock wiring section and a programmable bidirectional clock driver, the distribution clock comprises a fixed delay clock distribution section and a programmable bidirectional clock driver, there are n horizontal routing clocks and n horizontal distribution clocks across each clock region in the horizontal direction, n vertical wiring clocks and n vertical distribution clocks penetrate through each clock area in the vertical direction, n is a positive integer, the clock wiring sections and the clock distribution sections penetrate through the clock areas, and the programmable bidirectional clock driver is positioned at the splicing position of the two adjacent clock areas;
the fishbone clock structure comprises a root clock node and a plurality of leaf clock nodes, wherein the root clock node is arranged in each clock area, the root clock node is positioned on a clock distribution section of a vertical distribution clock, the leaf clock nodes are connected with the clock distribution section of a horizontal distribution clock, a wiring clock is used for sending a clock signal to the root clock node in the clock area from a clock input port, the wiring clock is programmable, the vertical distribution clock is used for sending the clock signal to the horizontal distribution clock from the root clock node, and the horizontal distribution clock is used for sending the clock signal to each leaf clock node of the fishbone clock structure.
In a preferred embodiment of the present invention, the clock signal of the root clock node is derived from a horizontal routing clock and a vertical routing clock, the root clock node sends the clock signal to a horizontal distribution clock through a one-way programmable driver, and the horizontal distribution clock drives each leaf clock node through an enable.
As a preferred embodiment of the present invention, the horizontal distribution clock in the clock region drives each leaf clock node by enabling, and when the logic circuit of the corresponding leaf clock node does not work, the clock drive is turned off, and the corresponding leaf clock node is cut off.
As a preferred embodiment of the present invention, the clock distribution segment and the clock wiring segment in the clock region are connected to the clock distribution segment and the clock wiring segment in the adjacent clock region through the programmable bidirectional clock driver.
As a preferable aspect of the present invention, the value of n is adjusted according to the scale of the FPGA chip and the routing rate of the wiring clock.
Compared with the prior art, the invention adopting the technical scheme has the following technical effects:
1. the sectional programmable clock network structure adopts a hierarchical design, the top layer adopts a sectional programmable wiring clock based on a clock area, and the clock skew close to zero is achieved through a predictable and flexible wiring clock. The fishbone clock routing is adopted in the clock area at the bottom layer, the size of clock deviation is controlled by controlling the area of the clock area, and the problem of overlarge clock skew accumulation caused by the increase of the FPGA scale can be effectively solved.
2. The nodes of the fishbone clock network in the clock area are all controlled by programmable drive, and the purpose of reducing power consumption can be realized according to the requirement.
Drawings
FIG. 1 is an overall architecture diagram of a clock domain based architecture for supporting a segmented programmable clock network architecture in accordance with the present invention.
Fig. 2 is a diagram of the internal structure of the clock zone of the present invention.
FIG. 3 is a programming diagram of a network architecture supporting a segmented programmable clock based on clock domains in accordance with the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
As shown in fig. 1, a clock region-based support segmented programmable clock network structure is suitable for a large-scale FPGA, and can provide a low-offset high-performance clock signal to meet the requirement of a large-scale FPGA chip on a high-performance clock. The clock network structure provides a concept of a clock area, the FPGA structure adopting the clock network is composed of the clock areas, the two-dimensional splicing of the clock areas in a plane forms rows and columns, and the whole FPGA structure is formed by matching IO (input/output) columns and configuration columns. Each clock region contains logic resources commonly seen in FPGAs such as DSP, BRAM and CLB, and these logic resources exist in the clock region in the form of columns, and the type and number of the columns of the logic resources in each clock region may be different, but the height should be kept consistent, and the resource type in the vertical direction should be the same. The IO column is an IO module and comprises a common IO and a global clock IO, the global clock IO receives an external clock signal and transmits the clock signal to the interior of each clock region through the bidirectional programmable driver.
The clock network structure uses a segmented programmable clock network on top, called a wiring clock. The wiring clock is composed of a fixed-delay clock wiring section and a programmable bidirectional clock buf, the wiring clock is mainly used for sending a clock signal to a root clock node in a clock area from a clock input port, and the delay of a target path can be guaranteed to be the same through programmable bidirectional clock driving, so that a high-performance clock signal with the skew of zero is provided. A fishbone clock structure is adopted in the clock area, a main clock in the clock area is called as a distribution clock, and power consumption can be effectively reduced by enabling to drive a leaf node clock. Each clock region has a root clock node therein, which is located on the vertical distribution clock, and the root clock node clock signal is derived from the horizontal wiring clock and the vertical wiring clock. The distribution clock is composed of a fixed-delay clock distribution section and a programmable bidirectional clock drive, and can be connected with the distribution clocks of adjacent clock areas. The clock region support sectional programmable clock network structure can ensure that the skew of a root clock node of a clock region is zero through programmability, so that a high-performance clock signal with low skew is provided for a large-scale FPGA.
The wiring clock and the distribution clock respectively pass through the clock area in the vertical direction and the horizontal direction, and the wiring clock is programmable and can transmit a clock signal from the clock input port into the clock area. The horizontal wiring clock and the distribution clock pass through the middle of the clock area, and balance of a fishbone clock network in the clock area is guaranteed.
As shown in fig. 2, for an internal structure diagram of a clock region supporting a segmented programmable clock network structure based on the clock region, n wiring clocks and n distribution clocks respectively pass through each clock region in the horizontal direction and the vertical direction, and the value of n can be adjusted according to the FPGA scale and the flexibility of the wiring clocks, thereby making a compromise between area and flexibility. There is a root clock node on the vertical distribution clock inside the clock region, the root clock node can be driven by the horizontal wiring clock and the vertical wiring clock, and the root clock node can drive the horizontal distribution clock. The wiring clock is programmable, and the vertical wiring clock and the horizontal wiring clock are driven bidirectionally, so that a clock signal can be sent to the root clock node in each clock zone from the clock input port through programming, and the delay reaching the root clock node in each clock zone is ensured to be the same, and the skew close to zero is achieved. A fishbone clock network structure is adopted in the clock area, and the horizontal distribution clock is used as a main clock network of the fishbone clock network. The horizontal distribution clock drives each leaf node clock by enabling, the leaf node clock provides clock signals for the logic resources in the clock area, and each leaf node clock provides clock signals for a column of the logic resources. When the leaf node clock is not used corresponding to a row of logic, the enable drive can be closed, and the corresponding logic is prevented from being overturned due to the clock signal, so that the purpose of reducing power consumption is achieved, and the low-power-consumption design is realized.
The clock network structure supports segmented programming, and the skew of clock signals reaching root clock nodes of each clock area can be guaranteed to be zero by programming bidirectional programmable drives on the wiring clock. The clock offset is not increased along with the increase of the FPGA scale, and is only influenced by the size of a clock area, and the accumulated skew inside the clock area is smaller, so that a clock signal with low offset and high performance can be provided. The wiring clock and the distribution clock in the clock area in the clock network structure can be connected with the wiring clock and the distribution clock in the adjacent clock area, a higher-level clock area concept is abstracted, the clock network structure is suitable for the condition of lower clock frequency, and the programming flexibility is further increased.
Fig. 3 shows an example of a programming implementation that supports a segmented programmable clock network architecture based on clock domains. In the graph, a and B are root clock nodes of two clock areas, and it can be seen from the graph that the distances from the root clock nodes a and B to a clock input port are different, and in the traditional FPGA clock network structure, a larger delay difference exists between a clock input from the clock input port and the root clock nodes a and B, thereby affecting some high-speed applications. The invention provides a network structure supporting a sectional programmable clock based on a clock area, which can well solve the problem based on programmability, ensure the clock skew of two root clock nodes A and B to be zero and improve the whole application performance.
The above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modifications made on the basis of the technical scheme according to the technical idea of the present invention fall within the protection scope of the present invention.

Claims (5)

1. A method for supporting a sectional programmable clock network structure based on a clock area is characterized in that an FPGA chip is divided into a plurality of clock areas with the same size according to the size of the FPGA chip, the clock areas are arranged in an array mode, and adjacent clock areas are spliced together; the programmable clock network structure comprises a wiring clock at the top layer of a clock area, a distribution clock and a fishbone clock structure in the clock area, wherein the wiring clock comprises a horizontal wiring clock and a vertical wiring clock, the distribution clock comprises a horizontal distribution clock and a vertical distribution clock, the wiring clock comprises a fixed delay clock wiring section and a programmable bidirectional clock driver, the distribution clock comprises a fixed delay clock distribution section and a programmable bidirectional clock driver, there are n horizontal routing clocks and n horizontal distribution clocks across each clock region in the horizontal direction, n vertical wiring clocks and n vertical distribution clocks penetrate through each clock area in the vertical direction, n is a positive integer, the clock wiring sections and the clock distribution sections penetrate through the clock areas, and the programmable bidirectional clock driver is positioned at the splicing position of the two adjacent clock areas;
the fishbone clock structure comprises a root clock node and a plurality of leaf clock nodes, wherein the root clock node is arranged in each clock area, the root clock node is positioned on a clock distribution section of a vertical distribution clock, the leaf clock nodes are connected with the clock distribution section of a horizontal distribution clock, a wiring clock is used for sending a clock signal to the root clock node in the clock area from a clock input port, the wiring clock is programmable, the vertical distribution clock is used for sending the clock signal to the horizontal distribution clock from the root clock node, and the horizontal distribution clock is used for sending the clock signal to each leaf clock node of the fishbone clock structure.
2. The method of claim 1, wherein the clock signal of the root clock node is derived from a horizontal routing clock and a vertical routing clock, the root clock node sends the clock signal to the horizontal distribution clock through a one-way programmable driver, and the horizontal distribution clock drives each leaf clock node through an enable.
3. The method of claim 1, wherein the horizontal distributed clock within the clock domain drives each leaf clock node by enabling, and when the logic circuit of the corresponding leaf clock node is not operating, the clock drive is turned off, cutting off the corresponding leaf clock node.
4. The method of claim 1 wherein the clock distribution segments and clock routing segments in a clock domain are connected to clock distribution segments and clock routing segments in an adjacent clock domain by programmable bi-directional clock drivers.
5. The method of claim 1, wherein the value of n is adjusted according to the size of the FPGA chip and the routing rate of the routing clock.
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CN109684718A (en) * 2018-12-24 2019-04-26 成都华微电子科技有限公司 Low-power consumption may be programmed SoC device and design method
CN111310409B (en) * 2020-02-28 2022-04-08 福州大学 Multi-stage FPGA wiring method for optimizing time division multiplexing technology

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