CN114039600A - Multichannel high-speed AD synchronous acquisition device and method - Google Patents
Multichannel high-speed AD synchronous acquisition device and method Download PDFInfo
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- CN114039600A CN114039600A CN202111138049.XA CN202111138049A CN114039600A CN 114039600 A CN114039600 A CN 114039600A CN 202111138049 A CN202111138049 A CN 202111138049A CN 114039600 A CN114039600 A CN 114039600A
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- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
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Abstract
The invention provides a multichannel high-speed AD synchronous acquisition device and a method, comprising a data processing board and N data acquisition boards; the data processing board comprises a local oscillator, a phase-locked loop, a power divider, a clock chip I, I, N analog optical modules, a digital optical module I (N is more than or equal to 1), and a data processing board FPGA chip; the data acquisition board comprises an analog optical module II, SMA, a clock chip II, a digital optical module II, M AD conversion chips (M is more than or equal to 1) and a data acquisition board FPGA chip. The device and the method of the invention combine the automatic synchronization function of the high-speed AD conversion chip, the inter-board synchronization technology, the analog optical module, the digital optical module and the GTX transmission technology, solve the limitation of multi-channel high-speed AD synchronous acquisition, ensure the synchronism and the phase consistency of multi-channel AD data acquisition, have high measurement precision, the precision of the correlation coefficient is better than 99 percent, and the precision of the correlation phase is less than or equal to +/-0.5 degrees.
Description
Technical Field
The invention belongs to the technical field of high-speed acquisition of microwave remote sensing broadband signals, and particularly relates to a multi-channel high-speed AD synchronous acquisition device and method.
Background
Along with the increasing number of AD acquisition channels, the increasing AD sampling precision, the increasing acquisition data transmission rate and the system miniaturization requirement, higher requirements are also provided for multi-channel high-speed AD synchronous acquisition, and a method which is easy to expand, easy to engineer and suitable for multi-channel high-speed AD synchronous acquisition is urgently needed. Through sufficient research, documents mostly mention the synchronization function and the synchronization pins of an AD device when describing the synchronization technology of a multi-chip AD acquisition system, and the system only realizes the in-board synchronization of limited channels and has poor reliable synchronization performance. Therefore, it is necessary to provide a multi-channel high-speed AD synchronous acquisition apparatus and method, which solve the problem of inter-board synchronization in AD acquisition and improve the reliability of synchronous acquisition.
Disclosure of Invention
In order to overcome the defects in the prior art, the inventor of the invention carries out intensive research, provides a multi-channel high-speed AD synchronous acquisition device and method, solves the problem of reliable synchronization of a high-speed AD multi-channel synchronous system under high-speed sampling, improves the reliability of synchronous acquisition, can realize the synchronism of acquisition among plates in a plate, is easy to realize in engineering and expand, and can realize higher-speed acquisition. The method has wide application range, high reliability and easy engineering realization, can be widely applied to a broadband signal high-speed acquisition system in the field of microwave remote sensing, and has wide market application prospect, thereby completing the invention.
The technical scheme provided by the invention is as follows:
in a first aspect, a multi-channel high-speed AD synchronous acquisition device comprises a data processing board and N data acquisition boards; the data processing board comprises a local oscillator, a phase-locked loop, a power divider, a clock chip I, I, N digital optical modules I (N is more than or equal to 1) and an FPGA chip of the data processing board, wherein the local oscillator, the phase-locked loop and the power divider are sequentially connected, the local oscillator generates a base frequency clock and sends the base frequency clock to the phase-locked loop, and the phase-locked loop performs phase-locking frequency multiplication on the base frequency clock and sends the base frequency clock to the power divider; the power divider is respectively connected with an analog optical module I and a clock chip I, the clock chip I is connected with a digital optical module I and a data processing board FPGA chip, the power divider divides the clock power into two paths, one path of the power divider transmits a synchronous sampling clock CLK to N data acquisition boards through the analog optical module I, the other path of the power divider divides N +1 paths of clocks through the clock chip I, wherein the N paths of synchronous clocks RCLK are respectively transmitted to the N data acquisition boards through the N paths of digital optical modules I, and the 1 path of FPGA _ CLK clock enters the data processing board FPGA chip to serve as a working clock of the data processing board FPGA chip; the data processing board FPGA chip receives the data sent by the N acquisition boards through the digital optical module I, and sends the data to the ground after related processing;
the data acquisition board comprises an analog optical module II, an SMA (shape memory alloy), a clock chip II, a digital optical module II, M AD (analog to digital) conversion chips (M is more than or equal to 1) and a data acquisition board FPGA (field programmable gate array) chip, wherein the analog optical module II sends a synchronous sampling clock CLK transmitted by the analog optical module I to the clock chip II through the SMA, the clock chip II divides the synchronous sampling clock CLK into M sampling clocks and 1 working clock which are in the same phase, and sends each sampling clock to each corresponding high-speed AD conversion chip to be used as a sampling clock of the high-speed AD conversion chips, so that the plurality of AD conversion chips are synchronously sampled, and the AD sampling boards are synchronous; sending the 1-path working clock to a data acquisition board FPGA chip as a working clock of the data acquisition board FPGA chip;
the M AD conversion chips are divided into 1 main AD conversion chip and M-1 slave AD conversion chips which are respectively provided with an AD conversion chip with an automatic synchronization function so as to enable the AD sampling board to be synchronous, the main AD conversion chip receives RCLK signals sent by the data processing board and controls DCLK clocks of the slave AD conversion chips so as to ensure that the initial phases of the DCLK clocks of the M AD conversion chips are completely consistent; the data acquisition board FPGA chip receives the data transmitted by the AD conversion chip, and the data is quantized by 1bit and then sent to the data processing board through the digital optical module II.
In a second aspect, a multichannel high-speed AD synchronous acquisition method includes the following steps:
(1) the data processing board generates a fundamental frequency clock by a local oscillator and sends the fundamental frequency clock to a phase-locked loop, and the phase-locked loop performs phase-locking frequency multiplication on the fundamental frequency clock and then sends the fundamental frequency clock to a power divider; the power divider divides the clock power into two paths, one path is sent to N data acquisition boards through an analog optical module I, the other path is divided into N +1 paths of clocks through a clock chip I, wherein the N paths of synchronous clocks RCLK are respectively sent to the N data acquisition boards through the N paths of digital optical modules I, and the 1 path of FPGA _ CLK clock enters a data processing board FPGA chip to serve as a working clock of the data processing board FPGA chip;
(2) the analog optical module II of each data acquisition board transmits a synchronous sampling clock CLK transmitted by the analog optical module I to a clock chip II through SMA, the clock chip II divides the synchronous sampling clock into an M-path sampling clock and a 1-path working clock which are in the same phase, and transmits each path of sampling clock to each corresponding high-speed AD conversion chip to be used as a sampling clock of the high-speed AD conversion chip, so that a plurality of AD conversion chips are synchronously sampled, and the synchronization among the AD sampling boards is completed; sending the 1-path working clock to a data acquisition board FPGA chip as a working clock of the data acquisition board FPGA chip;
(3) the AD conversion chip of the data acquisition board has an automatic synchronization function so as to synchronize the AD sampling in the board; the main AD conversion chip of the data acquisition board receives the RCLK signal sent by the data processing board and controls the DCLK clock of the slave AD conversion chip so as to enable the initial phases of the DCLK clock of the M AD conversion chips to be completely consistent;
(4) the FPGA chip of the data acquisition board is added with a delay fine adjustment module of an AD clock, and the phases of the data of multiple paths of AD are consistent by changing the phase of a reference clock of a sampling AD conversion chip;
(5) each AD conversion chip of the data acquisition board samples and converts an input broadband intermediate frequency analog signal into an analog-to-digital signal according to a high-speed AD sampling clock sent by a clock chip II, then sends the analog-to-digital signal to an FPGA chip of the data acquisition board, and performs 1bit quantization after speed reduction, digital filtering and IQ processing;
(6) the FPGA chip of the data acquisition board sends 1bit quantized data to the data processing board through a GTX signal transceiver and a digital optical fiber; preferably, the data acquisition board adds a frame header when the GTX signal transceiver transmits each frame of data, and the data processing board judges the simultaneity of the data through the frame header to ensure that the calculated data are the data acquired at the same time;
(7) the FPGA chip of the data processing board is also used for sending a synchronous working signal and an accompanying clock thereof to the N digital optical modules I through the LVDS interface chip, the digital optical modules I send the synchronous working signal and the accompanying clock thereof to the data acquisition boards, each data acquisition board analyzes the synchronous working signal by using the accompanying clock, and then the synchronous working signal is used as the start of data processing of the data acquisition boards, so that the synchronism of data processing implemented by the N data acquisition boards and the 1 data processing board is ensured.
The multichannel high-speed AD synchronous acquisition device and the method provided by the invention have the following beneficial effects:
(1) the invention provides a multichannel high-speed AD synchronous acquisition device and a method, wherein a data processing board generates N paths of synchronous sampling clocks through a local oscillator, a phase-locked loop and a power divider and transmits the N paths of synchronous sampling clocks to an analog optical module I, each data acquisition board generates in-phase multi-path sampling clocks through the analog optical module II, an SMA and a clock chip II and transmits the in-phase multi-path sampling clocks to a plurality of AD conversion chips to serve as synchronous sampling clocks, and the data acquisition boards realize in-board synchronization by using an automatic synchronization function of the AD self-carrying and finally realize in-board and inter-board synchronization of the sampling clocks.
(2) The invention provides a multichannel high-speed AD synchronous acquisition device and a method, wherein, the transmission line from each data acquisition board to a GTX signal transceiver of a data processing board on hardware and the synchronous working signal line from the data processing board to each data acquisition board are equal in length; the data acquisition board increases the frame header when each frame of data is transmitted by the GTX, and the data processing board judges the simultaneity of the data through the frame header, so that the calculated data are the data acquired at the same time.
(3) The invention provides a multichannel high-speed AD synchronous acquisition device and a method, wherein a data processing board simultaneously sends synchronous working signals and accompanying clocks thereof to N data acquisition boards, each data acquisition board analyzes the synchronous working signals by using the accompanying clocks, and then the synchronous signals are used as the start of data processing, so that the synchronism of the data processing of the N data acquisition boards and 1 data processing board is ensured.
(4) The FPGA software of the data acquisition board is added with a delay fine adjustment module of an AD clock, and the consistency of the data phases of multiple paths of AD is ensured by changing the reference clock phase of a sampling AD chip; the main AD conversion chip of the data acquisition board receives the RCLK signal sent by the data processing board, controls the DCLK clock of the slave AD conversion chip, and can ensure that the initial phases of the DCLK clock of the M AD conversion chips are completely consistent.
Drawings
FIG. 1 is a block diagram of a single data acquisition board assembly of the present invention;
FIG. 2 is a block diagram of the data processing board of the present invention;
FIG. 3 is a block diagram of a clock tree of the present invention;
fig. 4 is a block diagram of the synchronous implementation of the cascade of the AD conversion chips in the data acquisition board.
Detailed Description
The features and advantages of the present invention will become more apparent and appreciated from the following detailed description of the invention.
The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
According to a first aspect of the present invention, a multi-channel high-speed AD synchronous acquisition apparatus is provided, including a data processing board and N data acquisition boards, as shown in fig. 1, where the data processing board includes a local oscillator, a phase-locked loop, a power divider, a clock chip I, I, N analog optical modules, a digital optical module I (N is greater than or equal to 1, and N is 4 in fig. 1), and a data processing board FPGA chip, where the local oscillator, the phase-locked loop, and the power divider are connected in sequence, the local oscillator generates a base frequency clock and sends the base frequency clock to the phase-locked loop, and the phase-locked loop performs phase-locking and frequency-multiplying on the base frequency clock and sends the base frequency clock to the power divider; the power divider is respectively connected with an analog optical module I and a clock chip I, the clock chip I is connected with a digital optical module I and a data processing board FPGA chip, the power divider divides the clock power into two paths, one path of the power divider transmits a synchronous sampling Clock (CLK) to N data acquisition boards through the analog optical module I, the other path of the power divider divides N +1 paths of clocks through the clock chip I, wherein the N paths of synchronous clocks (RCLK) are respectively transmitted to the N data acquisition boards through the N paths of digital optical modules I, and the 1 path of clocks (FPGA _ CLK) enter the data processing board FPGA chip to serve as a working clock of the data processing board FPGA chip; the FPGA chip of the data processing board receives the data sent by the N acquisition boards through the digital optical module I, and the data are subjected to relevant processing and then sent to the ground through the LVDS interface chip;
as shown in fig. 2, the data acquisition board includes an analog optical module II, an SMA, a clock chip II, a digital optical module II, M AD conversion chips (M is greater than or equal to 1, and M is 4 in fig. 2) and a data acquisition board FPGA chip, the analog optical module II sends a synchronous sampling Clock (CLK) transmitted by the analog optical module I to the clock chip II through the SMA, the clock chip II divides the synchronous sampling clock into M sampling clocks (e.g., CLK 1-CLK 4) and 1 working clock (e.g., CLK5) of the same phase, and sends each sampling clock to each corresponding high-speed AD conversion chip as a sampling clock of the high-speed AD conversion chip, so as to ensure synchronous sampling of a plurality of AD conversion chips and achieve synchronization between the AD sampling chips; meanwhile, the 1-path working clock is sent to the FPGA chip of the data acquisition board to be used as the working clock of the FPGA chip of the data acquisition board (figure 3); the M AD conversion chips are divided into 1 main AD conversion chip and M-1 slave AD conversion chips which are respectively provided with an AD conversion chip with an automatic synchronization function so as to realize the in-board synchronization of AD sampling, the main AD conversion chip receives RCLK signals sent by the data processing board and controls the DCLK clocks of the slave AD conversion chips so as to ensure that the initial phases of the DCLK clocks of the M AD conversion chips are completely consistent (figure 4). The data acquisition board FPGA chip receives the data transmitted by the AD conversion chip, and the data is quantized by 1bit and then sent to the data processing board through the digital optical module II.
As shown in fig. 1, a local oscillator of a data processing board generates a 50MHz base frequency clock frequency, which is sent to a phase-locked loop, the phase-locked loop multiplies the frequency of the base frequency clock to 1.2GHz and then sends the frequency to a power divider, the power divider divides the 1.2GHz clock power into two paths, and one of the two paths sends N1.2 GHz synchronous sampling Clocks (CLK) to N data acquisition boards through an analog optical module I.
In the invention, the AD synchronous acquisition device has a data processing and synchronizing function. As shown in fig. 1, the FPGA chip of the data processing board is further configured to send a synchronous working signal and an accompanying clock thereof to the N digital optical modules I through the LVDS interface chip, the digital optical modules I send the synchronous working signal and the accompanying clock thereof to the data acquisition boards, each data acquisition board analyzes the synchronous working signal through the FIFO using the accompanying clock, and then uses the synchronous working signal as a start of data processing of the data acquisition boards, thereby ensuring synchronization of data processing performed by the N data acquisition boards and the 1 data processing board.
In the invention, the AD synchronous acquisition device has a data phase synchronization function. As shown in fig. 4, the data acquisition board controls DCLK of the remaining 3 slave AD conversion chips using the RCLK signal of one master AD conversion chip to ensure that the start phases of DCLK of 4 AD conversion chips are consistent. In addition to using the RCLK signal of the master AD conversion chip to control the DCLK clocks of the remaining slave AD conversion chips, the following method may be used: the FPGA chip of the data acquisition board is provided with a delay fine-tuning module of the AD clock, and the phases of the data of multiple paths of AD are ensured to be consistent by changing the phase of the reference clock of the sampling AD conversion chip, so that the data phases of all the AD conversion chips are finally synchronized.
In the invention, each high-speed AD conversion chip of the data acquisition board samples and converts an input broadband intermediate frequency analog signal according to a high-speed AD sampling clock (such as CLK 1-CLK 4) sent by a clock chip II, then sends the signal to a data acquisition board FPGA chip, carries out 1bit quantization after speed reduction, digital filtering and IQ processing, and then sends the 1bit quantized data to a data processing board through a GTX signal transceiver and a digital optical fiber.
Furthermore, the data acquisition board high-speed AD conversion chip adopts two differential input ADC12D1600 chips with automatic synchronization function, and the ADC12D1600 chips can realize two differential 1.2GHz AD sampling. One path of AD data after sampling is divided into two parallel paths of DId and DI, and the other path of AD data is divided into two parallel paths of DQd and DQ. Thus the data rate of DId, DI, DQd, DQ can be reduced to 600MHz, and if triggered by the double edge of the clock DCLK, DId, DI, DQd, DQ can be further reduced to 300 MHz. The code rate of each path of serial differential data in the multi-path serial data output by the AD conversion chip is not higher than 300 Mbps. When the number of the data acquisition boards is 4, and the number of the AD conversion chips in each data acquisition board is 4, the sending effective data rate of the data acquisition boards is 9.6Gbps, and the receiving effective data rate of the processing boards is 38.4 Gbps.
In the invention, the AD synchronous acquisition device has a data transmission synchronization function. The data acquisition board increases the frame header when the GTX signal transceiver transmits each frame of data, and the data processing board judges the simultaneity of the data through the frame header, so that the calculated data are the data acquired at the same time. Meanwhile, the lengths of the transmission line from each data acquisition board to the GTX signal transceiver of the data processing board and the length of the synchronous working signal line from the data processing board to each data acquisition board are ensured to be equal in hardware.
In the invention, the digital optical module I and the digital optical module II adopt MCOT-MN-12TR modules, and the clock chip I and the clock chip II adopt AD9516 chips.
According to a second aspect of the present invention, there is provided a multi-channel high-speed AD synchronous acquisition method, as shown in fig. 1 and fig. 2, including the following steps:
(1) a data processing board local oscillator generates a base frequency clock 50MHz and sends the base frequency clock to a phase-locked loop, and the phase-locked loop performs phase-locked frequency multiplication on the base frequency clock to 1.2GHz and then sends the base frequency clock to a power divider; the power divider divides a 1.2GHz clock into two paths, one path is sent to N data acquisition boards through an analog optical module I, the other path is divided into N +1 paths of clocks through a clock chip I (a clock chip AD9516), wherein N paths of synchronous clocks (RCLK) are respectively sent to the N data acquisition boards through the N paths of digital optical modules I, and the 1 path of clock (FPGA _ CLK) enters a data processing board FPGA chip to serve as a working clock of the data processing board FPGA chip;
(2) the analog optical module II of each data acquisition board transmits a synchronous sampling Clock (CLK) transmitted by the analog optical module I to the clock chip II through the SMA, the clock chip II divides the synchronous sampling clock into an M-path sampling clock (such as CLK 1-CLK 4) and a 1-path working clock (such as 150MHz clock CLK5) which are in the same phase, and transmits each path of sampling clock to each corresponding high-speed AD conversion chip to be used as a sampling clock of the high-speed AD conversion chip, so that synchronous sampling of a plurality of AD conversion chips is ensured, and synchronization between the AD sampling chips is realized; meanwhile, the 1-path working clock is sent to the FPGA chip of the data acquisition board to be used as the working clock of the FPGA chip of the data acquisition board (figure 3);
(3) the data acquisition board high-speed AD conversion chip is an AD conversion chip with an automatic synchronization function, such as an ADC12D1600 chip, so as to realize the in-board synchronization of AD sampling, and the ADC12D1600 chip can realize differential two-way 1.2GHz AD sampling; the AD conversion chip of the data acquisition board is divided into 1 main AD conversion chip and M-1 slave AD conversion chips, the main AD conversion chip receives RCLK signals sent by the data processing board and controls DCLK clocks of the slave AD conversion chips so as to ensure that the initial phases of the DCLK clocks of the M AD conversion chips are completely consistent;
(4) the FPGA chip of the data acquisition board is added with a delay fine adjustment module of an AD clock, and the consistency of the data phases of multiple paths of AD is ensured by changing the reference clock phase of a sampling AD conversion chip;
(5) each high-speed AD conversion chip of the data acquisition board samples and performs analog-to-digital conversion on an input broadband intermediate-frequency analog signal according to a high-speed AD sampling clock (such as CLK 1-CLK 4) sent by a clock chip II, then sends the analog signal to the FPGA chip of the data acquisition board, performs 1bit quantization after speed reduction, digital filtering and IQ processing, and then sends the analog signal to the FPGA chip of the data processing board;
(6) the FPGA chip of the data acquisition board sends 1bit quantized data to the data processing board through a GTX signal transceiver and a digital optical fiber; preferably, the data acquisition board adds a frame header when the GTX signal transceiver transmits each frame of data, and the data processing board judges the simultaneity of the data through the frame header to ensure that the calculated data are the data acquired at the same time;
(7) the FPGA chip of the data processing board is also used for sending a synchronous working signal and an accompanying clock thereof to the N digital optical modules I through the LVDS interface chip, the digital optical modules I send the synchronous working signal and the accompanying clock thereof to the data acquisition boards, each data acquisition board analyzes the synchronous working signal through the FIFO by using the accompanying clock, and then the synchronous working signal is used as the start of data processing of the data acquisition boards, so that the synchronism of data processing implemented by the N data acquisition boards and the 1 data processing board is ensured.
The method has the advantages that the synchronization of the AD acquisition clock, the consistency of the AD data phase and the synchronization of data receiving and processing of the whole multi-channel high-speed acquisition device can be ensured, and the whole system can achieve reliable synchronization. According to the system and the method, the problem of reliable synchronization of the high-speed AD multi-path synchronization system under high-speed sampling is solved, and the system and the method are easy to expand. The method is one of key technologies for designing the broadband signal high-speed acquisition system, has wide application range, high reliability and easy engineering realization, can be widely applied to the broadband signal high-speed acquisition system in the microwave remote sensing field, and has wide market application prospect.
The invention has been described in detail with reference to specific embodiments and illustrative examples, but the description is not intended to be construed in a limiting sense. Those skilled in the art will appreciate that various equivalent substitutions, modifications or improvements may be made to the technical solution of the present invention and its embodiments without departing from the spirit and scope of the present invention, which fall within the scope of the present invention. The scope of the invention is defined by the appended claims.
Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.
Claims (10)
1. A multi-channel high-speed AD synchronous acquisition device is characterized by comprising a data processing board and N data acquisition boards; the data processing board comprises a local oscillator, a phase-locked loop, a power divider, a clock chip I, I, N digital optical modules I (N is more than or equal to 1) and an FPGA chip of the data processing board, wherein the local oscillator, the phase-locked loop and the power divider are sequentially connected, the local oscillator generates a base frequency clock and sends the base frequency clock to the phase-locked loop, and the phase-locked loop performs phase-locking frequency multiplication on the base frequency clock and sends the base frequency clock to the power divider; the power divider is respectively connected with an analog optical module I and a clock chip I, the clock chip I is connected with a digital optical module I and a data processing board FPGA chip, the power divider divides the clock power into two paths, one path of the power divider transmits a synchronous sampling clock CLK to N data acquisition boards through the analog optical module I, the other path of the power divider divides N +1 paths of clocks through the clock chip I, wherein the N paths of synchronous clocks RCLK are respectively transmitted to the N data acquisition boards through the N paths of digital optical modules I, and the 1 path of FPGA _ CLK clock enters the data processing board FPGA chip to serve as a working clock of the data processing board FPGA chip; the data processing board FPGA chip receives the data sent by the N acquisition boards through the digital optical module I, and sends the processed data to the ground;
the data acquisition board comprises an analog optical module II, an SMA (shape memory alloy), a clock chip II, a digital optical module II, M AD (analog to digital) conversion chips (M is more than or equal to 1) and a data acquisition board FPGA (field programmable gate array) chip, wherein the analog optical module II sends a synchronous sampling clock CLK transmitted by the analog optical module I to the clock chip II through the SMA, the clock chip II divides the synchronous sampling clock CLK into M sampling clocks and 1 working clock which are in the same phase, and sends each sampling clock to each corresponding high-speed AD conversion chip to be used as a sampling clock of the high-speed AD conversion chips, so that the plurality of AD conversion chips are synchronously sampled, and the AD sampling boards are synchronous; sending the 1-path working clock to a data acquisition board FPGA chip as a working clock of the data acquisition board FPGA chip;
the M AD conversion chips are divided into 1 main AD conversion chip and M-1 slave AD conversion chips which are respectively provided with an AD conversion chip with an automatic synchronization function so as to enable the AD sampling board to be synchronous, the main AD conversion chip receives RCLK signals sent by the data processing board and controls DCLK clocks of the slave AD conversion chips so as to ensure that the initial phases of the DCLK clocks of the M AD conversion chips are completely consistent; the data acquisition board FPGA chip receives the data transmitted by the AD conversion chip, and the data is quantized by 1bit and then sent to the data processing board through the digital optical module II.
2. The multi-channel high-speed AD synchronous acquisition device as claimed in claim 1, wherein the FPGA chip of the data processing board is further configured to send a synchronous working signal and its accompanying clock to N digital optical modules I, the digital optical modules I send the synchronous working signal and its accompanying clock to the data acquisition boards, each data acquisition board analyzes the synchronous working signal using the accompanying clock, and then uses the synchronous working signal as the start of data processing of the data acquisition boards, so that the data processing of the N data acquisition boards and the data processing of the 1 data processing board are synchronized.
3. The multi-channel high-speed AD synchronous acquisition device of claim 1, wherein the FPGA chip of the data acquisition board is provided with a delay fine-tuning module of an AD clock, and the phases of the data of multiple AD channels are consistent by changing the phase of a reference clock of the sampling AD conversion chip.
4. The multi-channel high-speed AD synchronous acquisition device of claim 1, wherein each AD conversion chip of the data acquisition board performs sampling and analog-to-digital conversion on an input broadband intermediate-frequency analog signal according to a high-speed AD sampling clock sent by a clock chip II, then sends the signal to a FPGA chip of the data acquisition board, performs 1-bit quantization after speed reduction, digital filtering and IQ processing, and sends the 1-bit quantized data to the data processing board through a GTX signal transceiver and a digital optical fiber.
5. The multi-channel high-speed AD synchronous acquisition device of claim 1, wherein the data acquisition board high-speed AD conversion chip is two differential input ADC12D1600 chips with automatic synchronization function.
6. The multi-channel high-speed AD synchronous acquisition device as claimed in claim 4, wherein the data acquisition board increases a frame header when the GTX signal transceiver transmits each frame of data.
7. The multi-channel high-speed AD synchronous acquisition device of claim 1, wherein the GTX signal transceiver transmission line from each data acquisition board to the data processing board, and the synchronous working signal line from the data processing board to each data acquisition board are equal in length.
8. The multi-channel high-speed AD synchronous acquisition device as claimed in claim 1, wherein the digital optical module I and the digital optical module II are MCOT-MN-12TR modules, and the clock chip I and the clock chip II are AD9516 chips.
9. A multichannel high-speed AD synchronous acquisition method is characterized by comprising the following steps:
(1) the data processing board generates a fundamental frequency clock by a local oscillator and sends the fundamental frequency clock to a phase-locked loop, and the phase-locked loop performs phase-locking frequency multiplication on the fundamental frequency clock and then sends the fundamental frequency clock to a power divider; the power divider divides the clock power into two paths, one path is sent to N data acquisition boards through an analog optical module I, the other path is divided into N +1 paths of clocks through a clock chip I, wherein the N paths of synchronous clocks RCLK are respectively sent to the N data acquisition boards through the N paths of digital optical modules I, and the 1 path of FPGA _ CLK clock enters a data processing board FPGA chip to serve as a working clock of the data processing board FPGA chip;
(2) the analog optical module II of each data acquisition board transmits a synchronous sampling clock CLK transmitted by the analog optical module I to a clock chip II through SMA, the clock chip II divides the synchronous sampling clock into an M-path sampling clock and a 1-path working clock which are in the same phase, and transmits each path of sampling clock to each corresponding high-speed AD conversion chip to be used as a sampling clock of the high-speed AD conversion chip, so that a plurality of AD conversion chips are synchronously sampled, and the synchronization among the AD sampling boards is completed; sending the 1-path working clock to a data acquisition board FPGA chip as a working clock of the data acquisition board FPGA chip;
(3) the AD conversion chip of the data acquisition board has an automatic synchronization function so as to synchronize the AD sampling in the board; the main AD conversion chip of the data acquisition board receives the RCLK signal sent by the data processing board and controls the DCLK clock of the slave AD conversion chip so as to enable the initial phases of the DCLK clock of the M AD conversion chips to be completely consistent;
(4) the FPGA chip of the data acquisition board is added with a delay fine adjustment module of an AD clock, and the phases of the data of multiple paths of AD are consistent by changing the phase of a reference clock of a sampling AD conversion chip;
(5) each AD conversion chip of the data acquisition board samples and converts an input broadband intermediate frequency analog signal into an analog-to-digital signal according to a high-speed AD sampling clock sent by a clock chip II, then sends the analog-to-digital signal to an FPGA chip of the data acquisition board, and performs 1bit quantization after speed reduction, digital filtering and IQ processing;
(6) the FPGA chip of the data acquisition board sends 1bit quantized data to the data processing board through a GTX signal transceiver and a digital optical fiber;
(7) the FPGA chip of the data processing board is also used for sending a synchronous working signal and an accompanying clock thereof to the N digital optical modules I through the LVDS interface chip, the digital optical modules I send the synchronous working signal and the accompanying clock thereof to the data acquisition boards, each data acquisition board analyzes the synchronous working signal by using the accompanying clock, and then the synchronous working signal is used as the start of data processing of the data acquisition boards, so that the synchronism of data processing implemented by the N data acquisition boards and the 1 data processing board is ensured.
10. The multi-channel high-speed AD synchronous collecting method of claim 9, wherein in the step (6), the data collecting board adds a frame header when the GTX signal transceiver transmits each frame of data, and the data processing board judges the simultaneity of the data through the frame header to ensure that the calculated data are collected at the same time.
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