CN109889211A - A kind of multi-channel radio frequency applied to phased-array radar is directly adopted and generation circuit - Google Patents
A kind of multi-channel radio frequency applied to phased-array radar is directly adopted and generation circuit Download PDFInfo
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Abstract
It is directly adopted the present invention provides a kind of multi-channel radio frequency applied to phased-array radar and generation circuit, Clock management and matching delay unit generates ADC/DAC clock and low-frequency clock signal；Radio frequency generates and sampling module realizes directly generating and directly sampling for radiofrequency signal；It stores processing module and the initial data after storage AD sampling is received by FPGA, filtering extraction is carried out inside FPGA, and transmission of the digital signal between FPGA and DA is realized by FPGA；The control signal that main module receives system generates synchronization signal and reset signal, while realizing that transmitting-receiving is synchronous inside main module, synchronization signal and reset signal are transmitted to from module by common board, for controlling the synchronization and reset function of all AD/DA chips from module.The invention avoids the conversion loss of system, ensure that the quality of signal, meet the synchronous requirement of radar system beam position, efficient spatial power combing, multichannel transmitting-receiving.
Description
Technical field
The present invention relates to a kind of digital display circuits, directly adopt and generate mainly for the multi-channel radio frequency of P-L wave band, may be implemented
The multi-channel synchronous of Connectors for Active Phased Array Radar and digital array antenna arrays of radar.
Background technique
Connectors for Active Phased Array Radar and digital array antenna arrays of radar are made of the channel multichannel TR, general active phased array
Radar transmit-receive timing control and beam point steering are executed by TR component, are realized.And the transmitted waveform of Digital Array Radar produces
Raw, echo AD transformation is also realized in digital TR component.Therefore, multi-channel digital TR high-precise synchronization problem has been drawn, comprising more
Synchronization between transmission channel digital waveform generator, more receiving channel digital samples keep between synchronization and multichannel transmitting-receiving
Between synchronization.
In the radar of transmitting DBF system, for transmitting gain and beam position needed for obtaining system, own in system
Waveform signal in channel must assure that stringent timing synchronization.In order to guarantee that each DDS chip is synchronized with each other, can use
The included automatic synchronizing function of DDS chip makes every DDS chip all in active synchronization mode by controlling register, can be real
The stationary problem of multiple DDS chips in now each digital T/R module (DTRM).It, can for the synchronization between multiple digital T/R modules
By synchronous to realizations such as isometric design, the multicircuit time signal high precision time bias technologies for guaranteeing timing driving circuit.
Extensive phased array is conciliate by the generation, modulation and reception that each digital channel independently completes radar waveform
It adjusts, difficult point is the synchronization work for generating by high precision timing signal, transmitting compensation, distribution being driven to realize each digital channel
Make.System is received for multi-channel digital, it is inadequate, wideband array that only obtaining, which has the single channel Acquisition Circuit of excellent performance,
Multiple channels be difficult to avoid that in parallel sampling asynchrony phenomenon occur, this can greatly affect system performance, especially
Wave beam forming performance.Need it is asynchronous on each channel sample caused by influence to analyze, find on this basis simple and easy
Method measure and eliminate the asynchronous time delay between channel.For multi-channel digital reception system, synchronization is influenced
Factor mainly have the synchronization of work clock, the synchronization of system reference signal and data transmission stationary problem, guarantee multichannel between
These three signals reach nanosecond class precision, so that it may meet the needs of Digital Array Radar.
It has realized directly to sample for 2GHz radio frequency below at this stage and directly generated with radio frequency, but be directed to phased-array radar
The multi-channel radio frequency of application directly samples and radio frequency directly generates digital display circuit, still without reasonable solution.
Summary of the invention
For overcome the deficiencies in the prior art, it is direct to provide a kind of multi-channel radio frequency applied to phased-array radar by the present invention
It generates and sampling system, the multi-channel radio frequency that Connectors for Active Phased Array Radar and digital array antenna arrays of radar may be implemented directly produces
The raw synchronization between sampling and multichannel.
The technical solution adopted by the present invention to solve the technical problems is: a kind of multichannel applied to phased-array radar is penetrated
Frequency directly generates and sampling system, includes n digital assembly and a common board.
The digital assembly includes radio frequency generation and sampling module, Clock management and matching delay unit and storage processing
Module；The radio frequency generates and sampling module includes that the 4 tunnel channels signal acquisition AD and 4 road signals generate the channel DA；Wherein, when
Clock management and matching delay unit generate radio frequency and generate and ADC/DAC clock and low-frequency clock signal needed for sampling module；It penetrates
Frequency generates and sampling module realizes directly generating and directly sampling for radiofrequency signal；It stores processing module and storage is received by FPGA
Initial data after AD sampling, carries out filtering extraction inside FPGA, and by FPGA realize digital signal FPGA and DA it
Between transmission；1 is arbitrarily selected in the digital assembly as main module, remaining digital assembly is used as from module；Main module
The control signal of reception system generates synchronization signal and reset signal, while realizing that transmitting-receiving is synchronous inside main module, passes through public affairs
It is total to plate synchronization signal and reset signal are transmitted to from module, for controlling the synchronization of all AD/DA chips from module and answering
Bit function.
The digital assembly external input single channel reference clock signal, it is real by way of frequency multiplication in clock buffer
The high speed reference clock of existing ADC and DAC, and low frequency signal all the way, the low frequency are generated using Clock management and matching delay unit
Signal is homologous with the high speed reference clock of ADC and DAC and phase is consistent, and the low frequency signal of main module is transmitted to all submodules,
And it is realized by the phase difference of master and slave module low frequency signal to programmable clock time delay module in Clock management and matching delay unit
Configuration, and then complete to control the accurate delay of the configuration of AD, DA and other associated clocks buffer and delay adjustment module,
To guarantee to be input to the clock same-phase of ADC or DAC chip；The divided effect of the output of clock buffer generates correspondence
The reference clock of JESD204B communication.
In the channel AD, radiofrequency signal is received through front end low-pass filtering, and single-ended signal is converted using balun
At AD is entered after differential signal, signal enters Digital Down Convert after AD is collected, and carries out the down-sampled processing of filtering extraction
Sampled data be transferred to FPGA；The AD carries out Digital Down Convert using internal NCO, reduces signal transmission rate；Sampling
Initial data is sent to FPGA by JESD204B interface, and filtering extraction is carried out inside FPGA；Carrying out, JESD204B is effective
Transmitting-receiving synchronous calibration is carried out before data transmit-receive, is carried out NCO synchronous calibration when changing NCO respective frequencies every time, is guaranteed sampling clock
Rising edge alignment at the time of A/D chip is sampled is entered, guarantees that the time error in sampling time is less than given threshold.
In the channel DA, data to be sent are transmitted to FPGA through optical fiber by optical fiber interface, and FPGA is through JESD204B
Data to be sent are transferred to DAC by interface, are interpolated into high data rate；Data are transformed into radio frequency letter after Digital Up Convert
Number, then sent through radio-frequency front-end balun, low-pass filter；DA guarantees constant time lag by SYSREF signal；Pass through
SYSREF signal carries out the synchronization of local multiframe clock；SYSREF signal is isometric to chip, and reference clock is isometric to DA chip, and
And the delay of SYSREF signal to each chip is adjustable.
The AD and DA is realized synchronous in plate by following scheme: the phase of guarantee input clock signal to each AD or DA
Potential difference is the integral multiple of 2 π；Guarantee that the phase of sysref signal to each AD or DA are identical；Guarantee each AD/DA chip output
The I/O port of SYNC signal to FPGA are isometric.
The beneficial effects of the present invention are: avoiding the frequency conversion of system in such a way that radio frequency is directly sampled and directly generated
Loss, the digitlization of the system made ensure that the quality of signal closer to antenna, by being generated to high-precision common signal,
Transmission compensation, driving distribution etc. processing, can get the accurate timing control in the channel TR each to antenna array, realize phased array
The multiple radio frequencies of radar directly sample and the Synchronization Design of direct generation circuit, meet radar system beam position, efficient spatial function
Rate synthesis, the synchronous requirement of multichannel transmitting-receiving.
Detailed description of the invention
Fig. 1 is digital display circuit schematic diagram of the invention；
Fig. 2 is digital assembly schematic diagram of the invention.
Specific embodiment
Present invention will be further explained below with reference to the attached drawings and examples, and the present invention includes but are not limited to following implementations
Example.
Referring to Fig. 1, this phased-array radar realizes that the digital display circuit of multi-channel synchronization method includes that n digital assembly is (each
Digital assembly includes that 4 tunnel signal acquisition ADC channels and 4 road signals generate the channel DAC) and a common board.
Referring to fig. 2, digital assembly includes at radio frequency generation and sampling module, Clock management and matching delay unit and storage
Manage module composition.Wherein, Clock management and matching delay unit are mainly for generation of needed for radio frequency generation and sampling module
ADC/DAC clock and low-frequency clock signal；Radio frequency generate and sampling module be mainly used for realize radiofrequency signal it is direct generation with
Directly sample；Storage processing module is mainly used for storing the original number after AD sampling by the JESD204B interface of FPGA
According to the JESD204B interface for carrying out filtering extraction inside FPGA, and passing through FPGA realizes high-speed digital signal in FPGA and height
Transmission between fast DA.
N digital assembly can be divided into 1 main module by function and n-1 is a from module, and main module receives the control of system
Signal generates sysref signal (synchronization signal) and RST signal (reset signal), and sysref signal and RST signal is recycled to realize
While transmitting-receiving is synchronous inside main module, sysref signal and RST signal are transmitted to common board, common board issues mainboard
After reset and synchronization signal are divided into the road n-1, other n-1 are input to from module, for controlling all AD/DA chips from module
Synchronous and reset function.
Digital assembly external input single channel reference clock signal, it is real by way of frequency multiplication of phase locked loop in clock buffer
The high speed reference clock of existing ADC and DAC, and low frequency signal all the way, the low frequency are generated using Clock management and matching delay unit
Signal is homologous with the high speed reference clock of ADC and DAC and phase is consistent, and the low frequency signal of main module is transmitted to all submodules,
And it is realized by the phase difference of master and slave module low frequency signal to programmable clock time delay module in Clock management and matching delay unit
Configuration, and then complete to control the accurate delay of the configuration of AD, DA and other associated clocks buffer and delay adjustment module,
To guarantee to be input to the clock same-phase of ADC or DAC chip；The divided effect of the output of clock buffer generates correspondence
The reference clock (i.e. the serdes reference clock of FPGA) of JESD204B communication.
The AD receiving channel course of work is as follows: radiofrequency signal is received through front end low-pass filtering, using balun single-ended
Signal enters ADC after being converted into differential signal, and signal enters Digital Down Convert after ADC is collected, has 48bit number on plate
It controls oscillator (NCO), it can be by the frequency of programming Control NCO, to control the frequency of down coversion.It is downconverted using NCO
Afterwards, filtering extraction is directly carried out, carries out down-sampled processing, sampled data is transferred to FPGA through JESD204B interface.High-speed AD can
To use internal NCO to carry out Digital Down Convert inside AD, signal transmission rate is reduced；Sample source data can directly pass through
JESD204B interface is sent to FPGA, and filtering extraction is carried out inside FPGA.Multichannel AD, which is synchronized, needs to realize that JESD204B is same
Step, NCO are synchronous synchronous with AD transformation.Before carrying out the transmitting-receiving of JESD204B valid data, system will do it the synchronous school of transmitting-receiving automatically
Standard, synchronizing process are mainly ensured by the communication protocol of JESD204B；When changing NCO respective frequencies every time, it is necessary to carry out
NCO synchronous calibration realizes that NCO is synchronous by the NCO accumulator of reset.The synchronisation source of NCO can be set by register, the source
SYSREF signal, the SYNC signal and SPI synchronization signal of JESD204B, and its output frequency and phase can be set into can be with
It is configured by the way that register is arranged, the especially wherein configuration of phase register, the NCO of different chips can be made by finely tuning
Output reaches synchronous regime as far as possible；ADC is synchronous comprising two aspects, that is, guarantee has sampling clock to enter A/D chip more is sampled
At the time of rising edge alignment, which is mainly guaranteed by SYSREF signal in hardware；When guaranteeing sampling time tADC
Between error it is as small as possible.
It is as follows that DA signal generates channels operation process: optical fiber interface comes in data to be sent through optical fiber transmission, FPGA
Data to be sent are received, according to demand customized signal processing function, FPGA is through JESD204B interface data to be sent
It is transferred to DAC.DAC possesses a series of interpolation filters, can be data interpolating to high data rate.Digital Up Convert module is gathered around
There is the digital controlled oscillator (NCO) of 48bit, NCO generates mixing frequencies, and NCO can pass through programming Control frequency.Data are through numerically
Radiofrequency signal is transformed into after frequency conversion, then through radio-frequency front-end balun, low-pass filter is sent.High speed D/A passes through SYSREF signal
To guarantee constant time lag；SYSREF is homologous with device clock, and is the integral multiple frequency dividing of sampling clock；By SYSREF signal into
The synchronization of row local multiframe clock；The opposite phase relation with device clock (sampling clock) of SYSREF signal must satisfy each
The requirement of chip device clock: SYSREF signal is isometric to chip, and reference clock to DA chip must be isometric, and SYSREF believes
It number must be adjusted to the delay of each chip；On the other hand, in the inside of SYSREF signal, crawl circuit must be relatively
Readily satisfy foundation and the retention time of device clock.Portion realizes the function by the following method in the chip.It can lead to
It crosses software and compensates PCB fine pitch wirings error bring phase mismatch, SYSREF signal phase is become by environment in chip design
It is small to change influence；It is immune to retention time bring sampling error is established that SYSREF grabs circuit；Meanwhile in data conversion process
In, the phase information between SYSREF and device clock can be obtained by register.The signal grabs circuit and guarantees SYSREF
It can accurately grab, and then can realize device synchronization.
System is as follows using core devices index:
Processor: FPGA selects XilinxV7 series, and main performance is as follows:
A) logic unit (Logic Cells): 412,160；
B) GTX 12.5Gb/s transceiver: > 48；
C) user IO:350；
D) highest supports DDR3 buffer memory rate: 1866MT/S
E) internal storage capacity: 38,205Kb.
AD selects TI company high-speed AD, and main performance is as follows:
A) 12bit resolution ratio；
B) highest supports the sampling of 3.2GSPS binary channels and the sampling of 6.4Gsps single channel；
C) maximum input AC coupling analog signals amplitude is 0.8Vp-p；
D) automatic synchronization calibration is supported；
E) standard JESD204B interface, highest support single channel 12.8Gbps, could support up 16 channel interfaces；
F) channels crosstalk is better than -63dB, and signal-to-noise ratio is better than 52dB, and number of significant digit is higher than 8；
G) it is internally integrated the NCO of 32bit control, Digital Down Convert function and configurable data is supported to extract.
DA selects TI company high-performance DA, and main performance is as follows:
A) 14bit resolution ratio；
B) highest supports the sampling of 9GSPS binary channels；
C) output signal power is configurable, maximum value 0dBm；
D) multi-chip synchronous calibration is supported；
E) standard JESD204B interface, highest support single channel 12.5Gbps, could support up 8 channel interfaces；
F) channels crosstalk is better than -55dB, and signal-to-noise ratio is better than 51dB；
G) it is internally integrated the NCO of 48bit control, supports Digital Down Convert function and configurable data interpolation；
H) chip interior integrates PLL and VCO.
Synchronizing in plate is the key that whole system is synchronous, and AD and DA, which is synchronized, in plate uses identical synchronization scheme, same in plate
Step central factor is two aspects: guaranteeing the integral multiple that input clock signal is 2 π to each AD or DA phase difference；Guarantee sysref
The phase of signal to each AD or DA are identical；Guarantee that the SYNC signal of each AD/DA chip output must be isometric to the I/O port of FPGA.
In systems, the frequency of clock signal is relatively high, and is easy to be led to clock phase by digital signal interference for analog signal
Position noise is bigger than normal, and causing clock to be trembled must tiltedly thus in the design account for from system design to reduce this respect influence.
The characteristics of in view of clock signal, carry out system design from the following aspects: a) externally input clock signal passes through different
Path guarantees that all cablings are isometric when carrying out PCB design to AD/DA chip；B) add between clock output and AD/DA signal
Add controllable time delay unit, which is adjusted by FPGA, so as to adjust AD/DA clock phase is entered；C) to the ginseng with AD/DA
The key factor that clock is clock jitter in whole system is examined, when later use locking phase changes and generates practical DA/AD work clock,
The shake can be amplified, so as to cause the increase of system unstable factor.Therefore it carries out using frequency multiplication side when reference clock source design
The mode of formula substitution locking phase generates reference clock, to improve the phase noise of output clock and reduce trembling for final output clock
It is dynamic.D) when carrying out PCB design, clock signal internal layer cabling as far as possible is placed between power supply and stratum, signal wire passes through micro-strip
The form of line reduces signal and radiates to the external world, while avoiding interference of the extraneous radiation signal to clock signal.
Claims (5)
- It include n digital assembly and a public affairs 1. a kind of multi-channel radio frequency applied to phased-array radar is directly adopted and generation circuit Plate altogether, it is characterised in that:The digital assembly includes radio frequency generation and sampling module, Clock management and matching delay unit and storage processing mould Block；The radio frequency generates and sampling module includes that the 4 tunnel channels signal acquisition AD and 4 road signals generate the channel DA；Wherein, clock Management and matching delay unit generate radio frequency and generate and ADC/DAC clock and low-frequency clock signal needed for sampling module；Radio frequency It generates and sampling module realizes directly generating and directly sampling for radiofrequency signal；It stores processing module and storage AD is received by FPGA Initial data after sampling carries out filtering extraction inside FPGA, and realizes digital signal between FPGA and DA by FPGA Transmission；1 is arbitrarily selected in the digital assembly as main module, remaining digital assembly is used as from module；Main module connects The control signal of receipts system generates synchronization signal and reset signal, while realizing that transmitting-receiving is synchronous inside main module, by public Synchronization signal and reset signal are transmitted to from module by plate, for controlling the synchronization and reset of all AD/DA chips from module Function.
- 2. a kind of multi-channel radio frequency applied to phased-array radar according to claim 1 is directly adopted and generation circuit, special Sign is:The digital assembly external input single channel reference clock signal, is realized by way of frequency multiplication in clock buffer The high speed reference clock of ADC and DAC, and low frequency signal all the way, low frequency letter are generated using Clock management and matching delay unit Number homologous with the high speed reference clock of ADC and DAC and phase is consistent, the low frequency signal of main module is transmitted to all submodules, and It is realized by the phase difference of master and slave module low frequency signal to programmable clock time delay module in Clock management and matching delay unit Configuration, and then the accurate delay for completing configuration and delay the adjustment module to AD, DA and other associated clocks buffer controls, from And guarantee the clock same-phase for being input to ADC or DAC chip；The divided effect of the output of clock buffer generates correspondence The reference clock of JESD204B communication.
- 3. a kind of multi-channel radio frequency applied to phased-array radar according to claim 1 is directly adopted and generation circuit, special Sign is:In the channel AD, radiofrequency signal is received through front end low-pass filtering, and single-ended signal is converted into difference using balun Enter AD after sub-signal, signal enters Digital Down Convert after AD is collected, and carries out adopting for the down-sampled processing of filtering extraction Sample data are transferred to FPGA；The AD carries out Digital Down Convert using internal NCO, reduces signal transmission rate；It samples original Data are sent to FPGA by JESD204B interface, and filtering extraction is carried out inside FPGA；Carrying out JESD204B valid data Transmitting-receiving synchronous calibration is carried out before transmitting-receiving, carries out NCO synchronous calibration when changing NCO respective frequencies every time, guarantees that sampling clock enters Rising edge alignment at the time of sampling to A/D chip guarantees that the time error in sampling time is less than given threshold.
- 4. a kind of multi-channel radio frequency applied to phased-array radar according to claim 1 is directly adopted and generation circuit, special Sign is:In the channel DA, data to be sent are transmitted to FPGA through optical fiber by optical fiber interface, and FPGA is through JESD204B interface Data to be sent are transferred to DAC, are interpolated into high data rate；Data are transformed into radiofrequency signal after Digital Up Convert, then It is sent through radio-frequency front-end balun, low-pass filter；DA guarantees constant time lag by SYSREF signal；Pass through SYSREF signal Carry out the synchronization of local multiframe clock；SYSREF signal is isometric to chip, and reference clock is isometric to DA chip, and SYSREF believes Number to each chip delay it is adjustable.
- 5. a kind of multi-channel radio frequency applied to phased-array radar according to claim 1 is directly adopted and generation circuit, special Sign is:The AD and DA is realized synchronous in plate by following scheme: the phase difference of guarantee input clock signal to each AD or DA For the integral multiple of 2 π；Guarantee that the phase of sysref signal to each AD or DA are identical；Guarantee the SYNC letter of each AD/DA chip output Number to FPGA I/O port it is isometric.
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