CN114124278B - Digital synchronization circuit and method for digital simultaneous multi-beam transmission - Google Patents
Digital synchronization circuit and method for digital simultaneous multi-beam transmission Download PDFInfo
- Publication number
- CN114124278B CN114124278B CN202111278488.0A CN202111278488A CN114124278B CN 114124278 B CN114124278 B CN 114124278B CN 202111278488 A CN202111278488 A CN 202111278488A CN 114124278 B CN114124278 B CN 114124278B
- Authority
- CN
- China
- Prior art keywords
- digital
- circuit
- clock
- adc
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
Abstract
The application provides a digital synchronous circuit and a method for digital simultaneous multi-beam transmission, wherein a clock circuit multiplies a clock provided by an external or on-board crystal oscillator to supply a ADC, DAC, FPGA working clock and SYSREF signals needed by synchronization; the ADC circuit collects the intermediate frequency signals into digital signals and transmits the digital signals to the FPAG for processing through JESD204B protocol; the FPGA receives digital signals sent by the ADC to perform phase measurement, calculates phase differences among the ADC channels and returns the phase differences to the clock circuit to perform clock phase adjustment; meanwhile, a digital channel equalization filter is built in the FPGA to correct the amplitude-phase error, and the DAC circuit finishes the data playback of the stored waveform to generate an intermediate frequency signal. The application improves the synchronization precision of the circuit.
Description
Technical Field
The application relates to a digital circuit synchronization technology, in particular to a digital synchronization circuit and a digital synchronization method for digital simultaneous multi-beam transmission.
Background
The digital simultaneous emission multi-beam is a new technology applied to an array system electronic countermeasure system, and can simultaneously emit a plurality of interference signals to interfere a target. The technology has higher requirements on the aspect of digital board synchronization, and the delay jitter requirement of multipath signals finally output by a digital-to-analog converter (DAC) at the digital board end is less than or equal to 10ps. The existing digital circuit mainly comprises an ADC (analog-to-digital converter), an FPGA (programmable logic gate array), a DAC (digital-to-analog converter), and a clock circuit, wherein the clock circuit provides ADC, FPGA, DAC working clock, an ADC chip synchronously collects intermediate frequency signals, and the sampling data is subjected to algorithm processing such as digital extraction, digital filtering and the like in the FPGA. The multi-channel high-speed DAC chip generates and receives data sent by the FPGA to generate a single-tone signal, a modulation signal, a communication signal and the like, and the existing circuit is synchronized by mainly adopting a deterministic delay relation in JESD204B protocol and an interval taking a sampling clock as a unit to adjust a synchronization error, so that the synchronization method is difficult to meet the synchronization precision within 10ps.
Disclosure of Invention
The application aims to provide a digital synchronization circuit and a digital synchronization method for digital simultaneous multi-beam transmission.
The technical solution for realizing the purpose of the application is as follows: a digital synchronous circuit for digital simultaneous multi-beam transmission consists of a clock circuit, an ADC circuit, a DAC circuit and an FPGA, wherein the ADC circuit and the FPGA, the DAC circuit and the FPGA all adopt JESD204B protocol with deterministic delay to construct a link; the clock circuit supplies a working clock of ADC, DAC, FPGA and SYSREF signals required by synchronization to a clock provided by an external or on-board crystal oscillator through frequency multiplication; the ADC circuit collects the intermediate frequency signals into digital signals and transmits the digital signals to the FPAG for processing through JESD204B protocol; the FPGA receives digital signals sent by the ADC to perform phase measurement, calculates phase differences among the ADC channels and returns the phase differences to the clock circuit to perform clock phase adjustment; meanwhile, a digital channel equalization filter is built in the FPGA to correct the amplitude-phase error, and the DAC circuit finishes the data playback of the stored waveform to generate an intermediate frequency signal.
Furthermore, the clock circuit consists of two stages, wherein the first stage adopts an HMC7044 chip, after an external reference clock is input, the external reference clock is multiplied by the HMC7044 to be the working clocks of the ADC, the DAC and the FPGA, and SYSREF reference signals are provided for JESD204B protocol synchronization, so that synchronous acquisition and synchronous transmission of signals are realized; the second stage clock adopts LTM2954, and after the low jitter clock given by the first stage clock circuit is phase-adjusted by the internal PLL, the clock signal and SYSREF signal with fixed phase relation are output.
Furthermore, the balun transformers TCM1-63AX+ are adopted at the front end of the ADC chip to perform balance-unbalance conversion on the radio frequency input signals, and impedance matching of the input end is realized while single-ended and differential conversion functions are performed.
Furthermore, the DAC circuit adopts balun transformers TCM1-63AX+ at the rear end of the DAC chip to convert complementary current signals output by the DAC chip into intermediate frequency analog signals.
Furthermore, the digital channel equalization filter connects DAC signals output by multiple channels back to the same ADC through an analog switch for data acquisition and storage, calculates the phase after acquisition of each channel through an FPGA, selects 1 channel as a reference channel, calculates the equalization filter coefficients of other channels and the reference channel, and adjusts the phase and amplitude errors through the equalization filter.
A digital synchronization method is based on the digital synchronization circuit for digital simultaneous multi-beam transmission, and realizes digital synchronization.
Compared with the prior art, the application has the remarkable advantages that: 1) The two-stage clock circuit is added, so that the clock phase delay is adjusted; 2) And a channel equalization filter is designed in the FPGA, so that the output synchronization performance is improved.
Drawings
Fig. 1 is a block diagram of a digital synchronization circuit for digital simultaneous multi-beam transmission in accordance with the present application.
Fig. 2 is a block diagram of a clock circuit of the present application.
Fig. 3 is a timing diagram of the synchronization of the HMC7044 output of the present application.
Fig. 4 is a block diagram of an ADC circuit of the application.
Fig. 5 is a circuit diagram of the ADC radio frequency input circuit of the application.
Fig. 6 is a circuit diagram of the DAC output matching circuit of the present application.
Fig. 7 is a diagram illustrating an ADC synchronization example of the present application.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
As shown in FIG. 1, the digital synchronous circuit for digital simultaneous multi-beam transmission comprises a secondary clock circuit, an ADC circuit, a DAC circuit and an FPGA, wherein the ADC and the FPGA and the DAC and the FPGA all adopt JESD204B protocol with deterministic delay to construct a link. The clock circuit multiplies the frequency of the clock provided by an external or on-board crystal oscillator to supply a ADC, DAC, FPGA working clock and SYSREF signals needed by synchronization; the ADC circuit collects the intermediate frequency signals into digital signals, the digital signals are transmitted to the FPAG for processing through a JESD204B protocol, the FPGA receives the digital signals sent by the ADC for phase measurement, phase differences among the ADC channels are calculated, and the digital signals are returned to the clock circuit for clock phase adjustment; meanwhile, a digital channel equalization filter is built in the FPGA to correct the amplitude-phase error, and the DAC circuit finishes the data playback of the stored waveform to generate an intermediate frequency signal. The specific design is described as follows.
Clock circuit
As shown in fig. 2, the clock design requires the following indicators to be considered with emphasis on the clock: clock phase noise or jitter of the clock; broadband noise of the clock; synchronization of clocks and inter-lane skew. The clock circuit mainly comprises two stages, wherein an HMC7044 chip is adopted in the first stage, after an external reference clock is input, the external reference clock is multiplied by the HMC7044 to be the working clocks of the ADC, the DAC and the FPGA, and SYSREF reference signals are provided for JESD204B protocol synchronization, so that synchronous acquisition and synchronous transmission of signals are realized. And the clock source and clock jitter brought by a transmission path and the like are purified by utilizing the jitter removing function of the HMC7044 chip. The second-stage clock adopts LTM2954, and the low-jitter clock given by the first-stage clock circuit is provided with the clock signals of the ADC and the DAC and SYSREF signals after the phase of the low-jitter clock is adjusted by an internal high-precision PLL (the phase value is calculated by an FPGA). The device clock and SYSREF that are finally output have a fixed phase relationship. In addition, in order to avoid different delay effects caused by transmission paths, the clock circuit, wirings of the ADC and the DAC need to be processed in equal length.
The synchronization relationship between the input reference clock (100 MHz) and the output clock signal and SYSREF signal of the HMC7044 is simulated by adopting ADIsimCLK_setup simulation software of the ADI functional network, and a simulation timing diagram is shown in figure 3. As can be seen, the HMC7044 output clock has a fixed phase relationship, as do the device clock and SYSREF.
(two) ADC circuits
The ADC is realized by designing a high-performance ADC chip ADC12DJ3200 of TI company. According to the requirement, the bandwidth of the radio frequency input signal is 1.4 GHz-2.4 GHz, and the ADC performs high intermediate frequency sampling in the frequency band. As shown in fig. 4, the ADC circuit performs balance-unbalance conversion on the radio frequency input signal by using a high bandwidth 1:1 balun transformer TCM1-63ax+ at the front end of the ADC chip, and performs a single-ended and differential conversion function, and meanwhile, inputs an impedance of 50Ω, so that impedance matching at the input end can be better realized. The radio frequency input coupling mode is alternating current coupling. TCM1-63AX+ is a high-performance balun transformer with large bandwidth, the input bandwidth is 10 MHz-6 GHz, the insertion loss is 1.5dB, the two-stage insertion loss is 3dB, and the balun transformer has lower phase and amplitude unbalance degree.
(III) DAC Circuit
The DAC employs ADI corporation chips AD9164, AD9164 being a high performance, single channel, 16 bit digital to analog converter supporting DAC sampling rates up to 12.6 GSPS. As shown in fig. 6, the DAC circuit converts the complementary current signal output from the DAC into an intermediate frequency analog signal using balun at the back end of the DAC. TCM1-63AX + balun with lower phase and amplitude imbalance is also sampled.
(IV) JESD204B protocol transport
As shown in fig. 3, the JESD204B transmission fixed delay is designed to satisfy the following key synchronization points: synchronizing sampling clocks; JESD204B link synchronization; and (5) baseband synchronous control. In the sampling clock synchronization process, the clock output by the HMC7044 has a fixed phase relation, the clock phase of each ADC and each DAC can be aligned by adjusting the equipment clock and SYSREF signals, the timing requirement of establishing a maintaining relation and a synchronizing signal is met, and meanwhile, an elastic buffer release point is arranged at the receiving end of the JESD204B protocol. The synchronization performance of the JESD204B link is then utilized to align the data of the multiple serial channel links or multiple ADCs, DACs, to the SYSREF using a system reference event signal (SYSREF) in order to synchronize the internal frame clocks of the transmitter and receiver. The baseband timing synchronization is a trigger signal for the internal working synchronization of the FPGA. The baseband timing synchronization signal adopts an external clock board to provide PPS second pulse signals, and the provided PPS second pulse signals are required to have a fixed phase relation with a clock, so that the FPGA can normally collect second pulses.
The following description will take 2 ADCs using JESD204B protocol synchronization as an example. The 2 ADC12DJ3200 devices are synchronous with the same host (namely FPGA), the FPGA performs data sampling under the same SYNC signal, and each ADC is assumed to have deviation of process, voltage, temperature or the like in the same clock domain, and data is sampled by a clock twice as much as the SYNC signal through data multi-level buffering, so that the data clock error can be ensured to be less than 1 clock cycle. The hardware schematic is shown in fig. 7: the board card employs an ADC12DJ3200 chip with a JESD204B interface, which supports JESD204B subclass 1. In the sub-class 1 system, the accuracy of the deterministic delay depends on the timing relationship between the device clock and SYSREF, as well as the distributed skew of these signals in the system. In addition to the setup time and hold time requirements (TSU and THOLD) of SYSREF, the tolerance of the application to deterministic delay uncertainty is critical to defining the application distribution skew requirements of SYSREF and device clocks. In the sub-class 1 system, a "receive buffer" is defined whose release time is referenced to the external SYSREF signal. Therefore, it is not affected by the power supply cycle variation in the JESD204B system. Therefore, in order to achieve data alignment of the outputs of the multi-chip ADC, the DLU time is guaranteed to meet the requirements of the system in the design. Through LMFC frame synchronization in JESD204B and setting a receiving buffer at a receiving end, synchronization among a plurality of devices is realized.
(V) FPGA
The design of the channel equalization filter in the FPGA is that DAC signals output by multiple channels are connected back to the same ADC through an analog switch for data acquisition and storage, the FPGA calculates the phase after acquisition of each channel, 1 channel is selected as a reference channel, the equalization filter coefficients of other channels and the reference channel are calculated, and the phase and amplitude errors are adjusted through the equalization filter. The specific operation is as follows:
(1) 1 channel in the 2-piece DAC is selected as a reference channel, and a DDS (direct digital synthesizer) is used for producing test signals, such as a linear frequency modulation signal, in the FPGA. After being output by the DAC, the data sequentially enter the ADC to be collected, the collected signals are buffered, and the obtained data are respectively recorded as: h is a ref (m) and h 1 (m)。
(2) The stored data are sent to a main control for processing; for h ref (m)、h 1 (m) FFT with corresponding points is performed respectively to obtain H ref (m)、H 1 (m)。
(3) Solving forThe filter coefficient is h=a + H。
(4) The equalization filter is designed using these coefficients.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (4)
1. The digital synchronous circuit for digital simultaneous multi-beam transmission is characterized by comprising a clock circuit, an ADC circuit, a DAC circuit and an FPGA, wherein the ADC circuit and the FPGA, the DAC circuit and the FPGA all adopt JESD204B protocol with deterministic delay to construct a link; the clock circuit supplies a working clock of ADC, DAC, FPGA and SYSREF signals required by synchronization to a clock provided by an external or on-board crystal oscillator through frequency multiplication; the ADC circuit collects the intermediate frequency signals into digital signals and transmits the digital signals to the FPAG for processing through JESD204B protocol; the FPGA receives digital signals sent by the ADC to perform phase measurement, calculates phase differences among the ADC channels and returns the phase differences to the clock circuit to perform clock phase adjustment; meanwhile, a digital channel equalization filter is built in the FPGA to correct amplitude and phase errors, and a DAC circuit finishes data playback of the stored waveforms to generate intermediate frequency signals;
the clock circuit consists of two stages, wherein the first stage adopts an HMC7044 chip, after an external reference clock is input, the HMC7044 is used for doubling the frequency to work clocks of the ADC, the DAC and the FPGA, and SYSREF reference signals are provided for JESD204B protocol synchronization, so that synchronous acquisition and synchronous transmission of signals are realized; the second-stage clock adopts LTM2954, and after the phase of the low-jitter clock given by the first-stage clock circuit is adjusted by an internal PLL, a clock signal and a SYSREF signal with a fixed phase relation are output;
the digital channel equalization filter is used for receiving DAC signals output by multiple channels back to the same ADC through an analog switch for data acquisition and storage, calculating the phase after acquisition of each channel through an FPGA, selecting 1 channel as a reference channel, calculating the equalization filter coefficients of other channels and the reference channel, and adjusting the phase and amplitude errors through the equalization filter.
2. The digital synchronization circuit for simultaneous digital multi-beam transmission according to claim 1, wherein the ADC circuit performs balun transformers TCM1-63ax+ on the front end of the ADC chip to perform balun-unbalanced conversion on the rf input signal, and performs single-ended and differential conversion functions while performing impedance matching on the input terminal.
3. The digital synchronization circuit for digital simultaneous multi-beam transmission according to claim 1, wherein the DAC circuit converts complementary current signals output from the DAC chip into intermediate frequency analog signals using balun transformers TCM1-63ax+ at the back end of the DAC chip.
4. A digital synchronization method, characterized in that digital synchronization is achieved based on a digital synchronization circuit for simultaneous digital multi-beam transmission according to any of claims 1-3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111278488.0A CN114124278B (en) | 2021-10-30 | 2021-10-30 | Digital synchronization circuit and method for digital simultaneous multi-beam transmission |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111278488.0A CN114124278B (en) | 2021-10-30 | 2021-10-30 | Digital synchronization circuit and method for digital simultaneous multi-beam transmission |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114124278A CN114124278A (en) | 2022-03-01 |
| CN114124278B true CN114124278B (en) | 2023-09-26 |
Family
ID=80379990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111278488.0A Active CN114124278B (en) | 2021-10-30 | 2021-10-30 | Digital synchronization circuit and method for digital simultaneous multi-beam transmission |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114124278B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116455394B (en) * | 2023-06-16 | 2023-09-15 | 成都铭科思微电子技术有限责任公司 | Multichannel ADC synchronization device and automatic synchronization method |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006029511A1 (en) * | 2004-09-13 | 2006-03-23 | Nortel Networks Limited | Method and apparatus for synchronizing internal state of frequency generators on a communications network |
| EP2990832A1 (en) * | 2014-08-29 | 2016-03-02 | Sercel | Data acquisition apparatus using one single local clock |
| CN106844864A (en) * | 2016-12-23 | 2017-06-13 | 西安空间无线电技术研究所 | A kind of multipath clock adjusting method based on phase motor synchronizing technology |
| WO2017203534A1 (en) * | 2016-05-24 | 2017-11-30 | Thotaka Tekhnologies India Private Ltd | Simultaneous mimo communication system |
| CN108631809A (en) * | 2018-04-09 | 2018-10-09 | 成都泰格微电子研究所有限责任公司 | A kind of multi-channel digital TR components |
| CN109889211A (en) * | 2018-12-24 | 2019-06-14 | 中国电子科技集团公司第二十研究所 | A kind of multi-channel radio frequency applied to phased-array radar is directly adopted and generation circuit |
| CN110366822A (en) * | 2017-03-03 | 2019-10-22 | 德克萨斯仪器股份有限公司 | Meet setting/retention time for the repeating signal relative to clock |
| CN110958018A (en) * | 2019-12-19 | 2020-04-03 | 中船重工（武汉）凌久电子有限责任公司 | Design method for generating multi-frequency synchronous clock system |
| CN112054867A (en) * | 2020-08-30 | 2020-12-08 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Large-scale digital array signal synchronous acquisition system |
| CN113162626A (en) * | 2021-04-29 | 2021-07-23 | 中国船舶重工集团公司第七二三研究所 | High-precision multichannel synchronous high-speed data acquisition and processing system and method |
| CN113467696A (en) * | 2021-06-30 | 2021-10-01 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Multichannel AD data synchronous transmission system |
| CN113535620A (en) * | 2021-06-29 | 2021-10-22 | 电子科技大学 | Multichannel synchronous high-speed data acquisition device |
-
2021
- 2021-10-30 CN CN202111278488.0A patent/CN114124278B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006029511A1 (en) * | 2004-09-13 | 2006-03-23 | Nortel Networks Limited | Method and apparatus for synchronizing internal state of frequency generators on a communications network |
| EP2990832A1 (en) * | 2014-08-29 | 2016-03-02 | Sercel | Data acquisition apparatus using one single local clock |
| WO2017203534A1 (en) * | 2016-05-24 | 2017-11-30 | Thotaka Tekhnologies India Private Ltd | Simultaneous mimo communication system |
| CN106844864A (en) * | 2016-12-23 | 2017-06-13 | 西安空间无线电技术研究所 | A kind of multipath clock adjusting method based on phase motor synchronizing technology |
| CN110366822A (en) * | 2017-03-03 | 2019-10-22 | 德克萨斯仪器股份有限公司 | Meet setting/retention time for the repeating signal relative to clock |
| CN108631809A (en) * | 2018-04-09 | 2018-10-09 | 成都泰格微电子研究所有限责任公司 | A kind of multi-channel digital TR components |
| CN109889211A (en) * | 2018-12-24 | 2019-06-14 | 中国电子科技集团公司第二十研究所 | A kind of multi-channel radio frequency applied to phased-array radar is directly adopted and generation circuit |
| CN110958018A (en) * | 2019-12-19 | 2020-04-03 | 中船重工（武汉）凌久电子有限责任公司 | Design method for generating multi-frequency synchronous clock system |
| CN112054867A (en) * | 2020-08-30 | 2020-12-08 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Large-scale digital array signal synchronous acquisition system |
| CN113162626A (en) * | 2021-04-29 | 2021-07-23 | 中国船舶重工集团公司第七二三研究所 | High-precision multichannel synchronous high-speed data acquisition and processing system and method |
| CN113535620A (en) * | 2021-06-29 | 2021-10-22 | 电子科技大学 | Multichannel synchronous high-speed data acquisition device |
| CN113467696A (en) * | 2021-06-30 | 2021-10-01 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Multichannel AD data synchronous transmission system |
Non-Patent Citations (5)
| Title |
|---|
| Design of JESD204B Multi-channel Data Acquisition and Playback System Based on SoPC;jiadong yuan et al.;2018 11th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics;全文 * |
| 基于JESD204B协议的雷达视频信号同步传输设计与实现;王林;;舰船电子对抗(05);全文 * |
| 多通道同步时钟技术;涂正林;赵晨光;;舰船电子对抗(05);全文 * |
| 数字通信系统相位均衡滤波器的FPGA实现;李海军;邳志刚;边莉;;黑龙江科技学院学报(05);全文 * |
| 时间同步领域数字多波束天线系统性能评估;刘魁星;无线电工程;全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114124278A (en) | 2022-03-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108631809B (en) | Multichannel digital TR assembly | |
| CN113467696B (en) | Multichannel AD data synchronous transmission system | |
| KR100697571B1 (en) | Synchronization device and semiconductor device | |
| CN111736517A (en) | Synchronous acquisition and processing card system based on multichannel ADC and FPGA | |
| CN108631782B (en) | Multichannel-based high-speed ADC phase self-correction method | |
| US20110291865A1 (en) | Method, system, and apparatus for interpolating an output of an analog-to-digital converter | |
| CN106374927A (en) | Multi-channel high-speed AD system based on FPGA and PowerPC | |
| Pupalaikis et al. | Technologies for very high bandwidth real-time oscilloscopes | |
| CN101604968A (en) | A kind of channel extensible multi-phase high-performance clock method for designing and system | |
| CN114124278B (en) | Digital synchronization circuit and method for digital simultaneous multi-beam transmission | |
| CN110492964B (en) | CLOCK source synchronization device and method based on CLOCK BUFF | |
| US8750430B2 (en) | Data receiver circuit | |
| CN113595713B (en) | Received data alignment method and system based on multi-channel acquisition | |
| CN115936130A (en) | Multi-DAC pulse output synchronization and phase adjustment method and system based on FPGA | |
| CN215768986U (en) | Digital radar intermediate frequency signal processing unit and digital phased array radar | |
| CN115097898A (en) | Multi-board synchronous waveform output device based on JESD204B protocol and communication equipment | |
| CN218772058U (en) | ADC interweaving and collecting device based on JESD204B bus | |
| CN109495090B (en) | Digital precise time delay matching circuit | |
| CN113960682A (en) | Multi-channel digital correlator based on FPGA and correlation method thereof | |
| Ji et al. | The synchronization design of multi-channel digital TR module for phased array radar | |
| Sun et al. | Scalable self-adaptive synchronous triggering system in superconducting quantum computing | |
| US8731098B2 (en) | Multiple gigahertz clock-data alignment scheme | |
| Huang et al. | Automatic calibration method of multi-component synchronization for ultra-fast parallelized sampling systems | |
| CN116722946B (en) | Scalable synchronous clock tree system and phased array radar | |
| CN112019215B (en) | Pulse width modulation single-distribution type multichannel ADC synchronization method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |