CN110366822A - Meet setting/retention time for the repeating signal relative to clock - Google Patents

Meet setting/retention time for the repeating signal relative to clock Download PDF

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Publication number
CN110366822A
CN110366822A CN201880014749.8A CN201880014749A CN110366822A CN 110366822 A CN110366822 A CN 110366822A CN 201880014749 A CN201880014749 A CN 201880014749A CN 110366822 A CN110366822 A CN 110366822A
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clock
phase
signal
circuit system
comparison
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CN110366822B (en
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P·J·克莱默
M·H·奇尔德斯
R·C·塔夫特
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Texas Instruments Inc
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Texas Instruments Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00286—Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

It in the described example, include: clock circuitry for capturing the clock of the repeating signal relative to clock and generating, in clock cycle (TCLOCK) in provide have efficient clock edge (101) and inactive clock edge (102) clock (100)；And signal capture circuit system, based on the predetermined set and retention time (t for determining setting/holding window (13)SETUP/tHOLD), repeating signal transformation (20,21/22) is captured in efficient clock edge.Clock phase adjustment circuit system is configured as adjustment clock phase, so that repeating signal transformation (20,21) occurs in the signal capture window (14) between setting/holding window (13).Clock phase adjustment can be based on: clock invalid edges are aligned along (102) with repeating signal transformation (21)；And/or the continuous phase that clock and repeating signal change relatively is averaged；And/or execute initial polarity reversion selectively to generate polarity inverted clock, then adjust the clock phase of polarity inverted clock.A kind of illustrative embodiments are JESD204B (subclasses 1), control signal relative to SYSREF temporal reference to adjust DEVCLK phase.

Description

Meet setting/retention time for the repeating signal relative to clock
Background technique
Integrated circuit including clocked digital logic is operated using data-signal and control signal.Data-signal (or Only " data ") it is the signal assessed by circuit.Control signal can be used for the change in integrated circuit effectively (assert), reset or Synchronizing function, and data can be considered as.
Clocked digital is designed, is completed at (rising edge edge or trailing edge edge) to control/number in the effective edge of clock It is believed that the assessment of number transformation (in rising edge edge or decline edge from invalid (de-asserted) to effective (asserted)). The signal evaluation is referred to as signal capture or latch.
Control/data-signal is latched along relevant setting and retention time based on to clock effective edge.It is arranged (setup) Control/data-signal before being clock effective edge edge must stablize (constant) so as to the minimum time predictably latched.It protects Hold the data that (hold) is clock effective edge after and must stablize (constant) minimum time predictably to latch.Clock Setting/retention time depends on circuit design, including operating parameter (such as settling time (settling time) and signal road Diameter timing requirements) and clock/signal frequency.
Using based on the predictable latch of setting/holding requirement is met, signal capture can be deterministic.Therefore, only When control/data shift signal meets clock setting/retention time, control/data-signal could be deterministically captured.Example Such as, control/data shift signal in efficient clock edge occurs in setting/holding window to be had relative to the clock Capture to effect being determined property of edge.
Summary of the invention
Described example include for clock generate device and method, the clock generate have clock phase adjustment with Clock effective edge is aligned along setting/holding window relative to repeating signal, to (change/make effectively) positioning for repeating signal To meet setting/holding requirement in signal capture window.
In the described example, a kind of circuit includes the clock module for capturing the repeating signal relative to clock. The clock module includes: signal input part, receives the repeating signal with repeating signal transformation；Clock circuitry, The clock for having efficient clock edge and inactive clock edge is provided in the clock cycle；And signal capture circuit system, base In determine setting/holding window predetermined set and retention time efficient clock edge capture repeating signal transformation.This when Clock module includes clock phase adjustment circuit system to adjust clock phase, so that repeating signal transformation occurs in setting/holding In signal capture window between window.
In the example of other descriptions, disclose a kind of for the system with multiple equipment and systematic clock generator Equipment, which provides system equipment clock and repeat control signal, the equipment include setting for receiving system The clock interface of standby clock, and the repeat control signal with repeat control signal transformation.The equipment includes: clock module, It is based on system equipment clock and repeat control signal generates internal unit clock, which includes clock circuitry, To provide the internal unit clock with efficient clock edge and inactive clock edge within the clock cycle；And signal capture electricity Road system is captured in efficient clock edge based on the predetermined set and retention time for determining setting/holding window and repeats to control Signal transformation processed.The clock module includes clock phase adjustment circuit system to adjust clock phase, so that repeat control signal Transformation occurs in the signal capture window between setting/holding window.
In the example further described, a kind of method for capturing the repeating signal relative to clock includes: to receive Repeating signal with repeating signal transformation；Generated within the clock cycle have efficient clock edge and inactive clock edge when Clock；Based on the predetermined set and retention time for determining setting/holding window, repeating signal is captured in efficient clock edge and is turned Become；And adjustment clock phase, so that repeating signal transformation occurs in the signal capture window between setting/holding window.
Detailed description of the invention
Fig. 1 provides example waveform, shows clock [10] relevant to Repetitive controller/data-signal [20], including It shows with clock effective edge along (t0) it is relevant setting and retention time (tSETUPAnd tHOLD), to establish setting/holding window [13] and previous signal capture window (tVALID) [14], and show: (a) for the signal capture of control signal [20B], control Signal [20B] is in t0Become effectively [21B] in signal capture window, and in t0It is captured [22C] and (determines in setting/holding window Property)；(b) for the signal capture of control signal [20D], signal [20D] is controlled in t0It (is being set after signal capture window Set/keep in window [13]) become effectively [21D], and be captured [22E] (uncertainty in the effective edge of next clock Ground)；And (c) captured for controlling the non-deterministic signal of signal [20F], signal [20F] is controlled illustratively in t0Signal Capture window (tVALID) [14] and t0Boundary between setting/holding window [13] becomes effectively [21F], so that signal capture Non-deterministically [22G1 or 22G2] occurs for [22G].
Fig. 2, which is provided, shows the example waveform that clock according to the present invention generates, which, which generates, has clock phase Adjustment is aligned with that will be arranged/keep window [13,103] relative to repeat control signal [20], so that control signal is positioned in To meet the setting limited/holding requirement in signal capture window [14], including exemplary clock phase adjustment is shown, wherein t0 Clock effective edge is delayed by [100,101] along [10,11], so that previous clock invalid edges turn along [10,12] and control signal Become [20,21] alignment [100,102], leads to t0Setting/holding window [13 to 103] and associated signal capture window [14 To 104] phase delay so that control signal transformation [21] occur in t0Signal capture of the clock effective edge along [100,101] In window [104], and in t0[22] are captured in setting/holding window [103].
Fig. 3 shows the exemplary RF sampling ADC [300] with double ADC [301A/301B], and is based on JESD204B DEVCLK (equipment clock) and SYSREF (timing rhohase benchmark) [310,320] repeat control signal of generation it is exemplary JESD204B serial line interface [303A/303B] is synchronous with JESD204B clock, and including exemplary clock distribution and synchronous mould Block [400], being provided based on SYSREF timing rhohase reference signal (source synchronous with DEVCLK) has JESD204B subclass 1 true The qualitative link sluggishness compliance local multiframe clock (LMFC) [100] synchronous with more equipment, the clock distribution and synchronization module The LMFC clock with DEVCLK phase adjustment is generated according to the present invention, when so that SYSREF meeting DEVCLK setting and keeps Between.
Fig. 4 A and Fig. 4 B show exemplary clock generator according to the present invention, which has clock Phase adjustment, so that repeat control signal meets clock setting and retention time: Fig. 4 A is shown with DEVCLK (clock) [401] phase adjustment is to provide showing for the signal capture window being aligned with SYSREF control (timing rhohase benchmark) signal [402] Example property JESD204B (subclass 1) clock distribution and synchronization module [400] comprising there is clock phase adjustment the adjustable of circuit to prolong Slow clock generator [420], which includes phase comparator [440] and controller [450] and optional averager [460]；And Fig. 4 B shows the example tunable delay clock generator [420] including exemplary multi-tap transmission line [430].
Fig. 5 provides example waveform, show clock phase according to the present invention adjustment with by CLOCK [100] setting/ Keep window relative to SYSREF control signal [520] alignment is repeated, so that SYSREF control signal framing will be repeated in signal To meet setting/holding requirement in Capture window, including exemplary clock phase adjustment is shown with by clock invalid edges edge [102B] and SYSREF control signal [521B] (in signal capture window) is aligned, and including adjusting for clock phase Example calibration mode [531,532] embodiment.
Specific embodiment
Described example include clock generate, with clock phase adjust with by clock effective edge along setting/holding Window is aligned relative to repeating signal, so that repeating signal (transformation/change is effective) is located in (effective) signal capture window To meet setting/holding requirement and design example (illustrative embodiments).
In the present specification, " clock " refers to has cycle T under assigned frequencyCLOCKAnd with effective edge edge and in vain The clock signal at edge, the convention used according to the present invention, effective edge edge and invalid edges edge are rising clock edge respectively under Clock edge drops." control signal " refers to the Repetitive controller for needing to capture in effective the being determined property of edge of clock or data letter Number." setting " and " holding " time (" setting/holding " time) are required to make a reservation for by design/manufacture of clocked digital circuit design, And setting/holding window relative to clock effective edge edge is established, during setting/holding window, control signal can be by It deterministically captures, wherein control signal transformation occurs during signal capture window previous, is used so that control signal meets In clock setting/holding requirement that deterministic signal captures.In interested operation time period, clock and control signal are both It is the frequency for repeating and fixing.
It is adjusted based on clock phase in short, clock is generated will be arranged/keep window relative to repetition (control/data) Signal alignment, to repeating signal is located in signal capture window to meet setting/holding requirement.For capture relative to The clock module of the repeating signal of clock includes: clock circuitry, and providing within the clock cycle has efficient clock edge With the clock at inactive clock edge；And signal capture circuit system, based on determine setting/holding window predetermined set and Retention time captures repeating signal transformation in efficient clock edge.When clock phase adjustment circuit system is configured as adjustment Clock phase, so that repeating signal transformation occurs in the signal capture window between setting/holding window.Clock phase adjustment can To be based on: clock invalid edges are aligned along with repeating signal transformation；And/or the continuous phase ratio for changing clock and repeating signal Relatively it is averaged；And/or execute initial polarity reversion selectively to generate polarity inverted clock, and then adjustment polarity reversion The clock phase of clock.One illustrative embodiments is JESD204B (subclass 1), relative to SYSREF timing control benchmark To adjust DEVCLK phase.
Fig. 1 shows example waveform, shows the timing for capturing the control signal relative to clock, such as with clock Digital Logic is implemented.The instruction of these example waveforms is for example in the clocked digital design for controlling signal (certainty) latch Needed for relative to it is illustrative setting and the retention time signal capture.
With cycle TCLOCKClock 10 include the time t in present clock period0The effective edge at place is along 11.It is illustrative Setting and retention time tSETUPAnd tHOLDClock effective edge is indicated for along t0, thus limit setting/holding window 13 (according to Clocked digital logic parameter (including clock frequency) makes a reservation for).In t0Before the setting of the effective edge of clock/holding window 13 It is signal capture window (tVALID) 14, signal capture window 14 illustratively include previous clock invalid edges along 12 (although this It is not the requirement to useful signal Capture window).
As clock speed increases to lucky (giga) oversampling clock rate, TCLOCKPeriod reduces, so that for being arranged/keeping Signal capture window (the t that deterministic data in window latchesVALID) correspondingly constrained,
tVALID=TCLOCK-tSETUP-tHOLD,
Its magnitude that can have 100-200ps, and correspondingly increase the constraint to timing allowance, to meet setting and protect Requirement is held, including the requirement under circuit board rank and system level.
/ data-signal capture (become effective/transformation for controlling) timing be illustrated as and t0Clock effective edge edge is related, The timing includes illustrative setting/holding window 13 and previous signal capture window 14.It illustrates for control signal 20B's Signal latch (21B/21C), the signal latch (21D/21E) for control signal 20D and the signal lock for control signal 20F Deposit (21F/21G) comprising the certainty and non-deterministic signal of control signal relevant to clock setting/holding window 13 are caught It catches.
With reference to clock 10 and t0Clock effective edge is along 11 relevant control signal 20B, in t0Setting/holding window 13 it Before (especially in t0Be arranged before the time starts) t0T before clock effective edge edge0In signal capture window 14, at 21B Signal 20B is controlled to become effectively (transformation).As a result, control signal 20B meets setting/holding requirement, and in t0Signal capture window (especially in t in mouth 130In retention time) it is captured at 22C by (deterministically).
With reference to clock 10 and t0Clock effective edge is along 11 relevant control signal 20D, t previous0Signal capture window After 14 and in t0After the setting time starts, signal 20D is controlled at 21D and is become effectively (transformation), this is for t0Clock is effective It is deterministically late for edge.As a result, control signal 20D is in next TCLOCKIn at 22E (i.e. in next clock effective edge In the retention time on edge) it is captured by (non-determinedly).In fact, believing for any once control in setting/holding window Number transformation, capture is all non-deterministic, because cannot determine that it will be captured or under in effective edge for certain One effective edge is captured.
With reference to clock 10 and t0Clock effective edge is along 11 relevant control signal 20F, nominally control signal 20F is in t0 Signal capture window 14 and t0Become effectively (transformation) at boundary 21F between setting/holding window.Since variation is the result is that shadow The signal path and logical design, this boundary transition for ringing timing allowance are considered intrinsic uncertainty, so that control Signal 20F processed is non-determinedly (unpredictably) in t0In t in clock cycle0It is captured at 22G1 in setting/holding window, Or it is captured at 22G2 within next clock cycle.
If the temporal constraint explanation in Fig. 1 will deterministically capture (latch) control signal, they need to be positioned In the signal capture window before setting/holding window, wanted to provide enough timing allowances with meeting setting/holding It asks.Will control signal framing the considerations of meeting setting/holding requirement (timing allowance) in signal capture window factor can be with Including considering with the difference of control/data and clock path (such as using for controlling/the dc-couple of data and for clock AC coupled) relevant signal path and logical design variation, since upper frequency clock signal is relative to lower frequency Differential signal amplitude caused by the influence of control/data-signal impedance discontinuity (and relevant propagation delay), and system Make the change of variation, aging and temperature or supply voltage.
Fig. 2, which is provided, shows the example waveform that clock according to the present invention generates, which, which generates, has clock phase tune It is whole to be aligned with that be arranged/keep window relative to repeating signal, so that repeating signal is located in signal capture window with full Sufficient setting/holding requirement.
Clock 10 includes effective edge at 11 along t0, wherein being directed to t0The illustrative setting and holding on clock effective edge edge Time tSETUPAnd tHOLDLimit setting/holding window 13.In t0It is letter before the setting of the effective edge of clock/holding window 13 Number Capture window (tVALID) 14, signal capture window 14 illustratively includes previous clock invalid edges along 12.
Repeat control signal 20 becomes effective (transformation) at 21, is being directed to t0The signal capture window on clock effective edge edge After 14.In the example shown, control signal 20 is substantially in t0T in setting/holding window 130The effective edge of clock Transformation 21.As a result, the control signal becomes effectively, (assertion) will not be deterministically in t0TCLOCKIn be captured, and right and wrong Deterministically in t0Clock effective edge edge or the effective edge of next clock are captured.
Clock phase adjustment according to the present invention is for effective relative to repeat control signal by clock setting/holding window Ground alignment, so that control signal is positioned in previous signal capture window to meet the setting/holding requirement limited.Example Such as, phase adjustment clock 100 postpones relative to clock 10, to postpone t0Clock effective edge is along 11/101 and associated adopts Sample/holding window 13/103 will control signal transformation 21 in t0Alignment in signal capture window 14/104.
In the example shown, t0Clock effective edge is delayed by 100/101 along 10/11, so that previous clock invalid edges edge 12 are aligned 100/102 with control signal transformation 20/21.Clock phase adjustment effectively delays setting/holding window 13/ 103 and associated signal capture window 14/104.
As clock phase adjustment as a result, control signal transformation 21 is positioned in effective signal capture window 100/ In 104, so that control signal is in t0Time t is setSETUPBecome effectively before, to meet in t0The determination of the effective edge of clock The setting requirements of property signal capture.As a result, being directed to t0The retention time t on clock effective edge edgeHOLDPeriod captures 22 control letters Number.
Therefore, illustrative clock phase is adjusted, the clock of control signal transformation 21 and clock effective edge between without Edge alignment is imitated, so that it is guaranteed that being located in effective signal capture window 100/104, in t0The setting on clock effective edge edge/ It keeps changing before window 103 and (becoming effective).The clock phase is adjusted to meet for deterministically capturing repeat control signal Setting/holding require provide maximum timing allowance.
Since clock 10/100 is that periodically, clock phase adjustment will not be based on the t of phase shift0Clock is effective Edge (its effectively phase shift be arranged/keep window) for capture control signal 20 timing in generating ambiguity.Moreover, because Clock phase is influenced to control the timing of signal, so control signal effectively becomes main timing alignment.
According to the present invention with clock phase adjustment clock generation be used for effectively by setting/holding window relative to Repeating signal alignment, to repeating signal is located in signal capture window to meet setting/holding requirement.According to the present invention To meet setting/holding requirement clock phase adjustment can be applied to need based on setting relative to fixed frequency clock Set/keep any circuit for requiring and capturing Repetitive controller (or data) signal.
Fig. 3 shows the example RF sampling ADC 300 with double ADC 301A and 301B.ADC 300 includes with double The example JESD204B serial line interface of JESD204B link driver 303A and 303B.More equipment clocks are synchronous to be based on JESD204B The equipment clock DEVCLK 310 and timing rhohase benchmark SYSREF (repetition) that (subclass 1) generates control signal 320.JESD204B DEVCLK and SYSREF is provided by external JESD204 clock generator (not shown).
Example clock distribution and synchronization module 400 pass through ± 310/401 He of JESD204B differential clocks interface DEVCLK SYSREF ± 320/402 is received.Clock distribution and synchronization module 400 generate inside local multiframe clock (LMFC) 100, inside this Local multiframe clock 100 provides sampling clock for ADC 301A/301B, and is JESD204B LINK A/B driver 303A/ 303B provides JESD204B LMFC clock.
LMFC clock, which generates, is based on DEVCLK and SYSREF, to provide the conjunction of 1 certainty link sluggishness of JESD204B subclass Rule property, and more equipment are synchronous based on SYSREF timing rhohase reference control signal (source synchronous with DEVCLK).Clock distribution Clock phase adjustment is based on synchronization module 400 and generates LMFC clock, according to the present invention by the (setting/holding window of LMFC clock Mouthful) relative to SYSREF control signal alignment, so that SYSREF control signal is positioned in signal capture window, to meet The setting of the restriction of LMFC (DEVCLK of phase adjustment)/holding requirement, the operation requirement including RF sampling ADC 300.
Fig. 4 A and Fig. 4 B show example clock generator block 400, such as can be real in the RF sampling ADC of Fig. 3 Apply (clock distribution and synchronization module 400).It is raw that clock generator 400 implements the clock with clock phase adjustment according to the present invention At by DEVCLK (clock) setting/holding window relative to the alignment of SYSREF (control) timing reference signal is repeated, thus will SYSREF is located in phase shift signalling Capture window to meet setting/holding requirement.
Fig. 4 A shows example JESD204B (subclass 1) clock generator block 400, has for receiving DEVCLK The interface of 401 and SYSREF 402.Clock generator 410 includes adjustable delay clock generator 420 to generate clock 100 (LMFC), the phase of the clock 100 is adjusted DEVCLK be arranged/be kept window relative to SYSREF is repeated and control signal pair Together, so that SYSREF is located in signal capture window, to meet setting/holding requirement.
Clock generator 410 include clock phase adjust circuit, with control for adjustable delay clock generator 420 when Clock phase adjustment.Clock phase adjustment circuit includes phase comparator 440 and controller 450, and optional averager 460. The advantages of repeat control signal (such as SYSREF) is that it can be averaged, so that the absolute timing arrangement of clock and effectively letter The placed in the middle of number Capture window is not influenced by the shake (variation in period to period) of SYSREF control signal.
When each SYSREF control signal transformation, phase comparator 440 determines that clock 100 is high or low.Phase bit comparison As a result it is provided to (optional) averager 460.Averager is collected within the period determined by controller 450 from phase ratio Compared with device as a result, and providing the most common result to controller.
Based on the phase comparison result from averager 460, controller 450 is provided to adjustable delay clock generator 420 Clock phase adjustment control.
Fig. 4 B shows the example comprising (optional) input polarity inverse block 422 and example multi-tap transmission delay line 430 Adjustable delay clock generator 420.
Polarity reversion is optional.For example tunable delay clock generator 420, polarity reversion is included in clock phase To simplify phase adjustment (the clock phase adjusting range needed for reducing) in the adjustment circuit of position.Controller 450 is to polarity inverse block 422, which provide clock, inverts enable signal 451, to control clock polarity reversion.
Multi-tap transmission delay line 430 includes unit delay part 431-430N, these unit delay parts are defeated by tap Enter the N for being supplied to and being controlled by the delay selection signal 452 from controller 450 to 1 multiplexer 239.Based on from control The delay selection signal 452 of device 450, multiplexer 239 select (such as Fig. 3 of (delay) clock 100 of output phase adjustment In LMFC clock).Inhibit the shake adjusted from clock phase using on piece multi-tap transmission delay line 430.
With reference to Fig. 4 A/ Fig. 4 B, controller 450 implements example binary search algorithm to adjust clock delay, thus by pole Sex reversal signal 451 and delay selection signal 452 are supplied to adjustable delay clock generator 420.For example embodiment, clock synchronization Clock carries out phase adjustment (displacement) until invalid (decline) edge of clock is aligned with SYSREF transformation (rising edge edge).
The example binary search for clock phase adjustment is executed based on the step-length adjustment S with optional step sizes Routine.Clock delay is initialized as a quarter of maximum delay setting by controller 450.Then, when controller executes example Clock phase adjustment routine, instruction averager 460 collect the phase comparison result of selected quantity from phase comparator 440: if (a) Result from averager is "high", then when SYSREF changes, clock 100 is most of to be high, therefore controller is big with step-length Small S reduces clock delay (delay selection signal)；And (b) if the result from averager is " low ", when SYSREF turns When change, clock is largely low, therefore controller increases clock delay (delay selection signal) with step sizes S.
After the adjustment of each clock phase, controller 450 repeats example clock phase and adjusts routine, wherein optional step-length Size S changes.Routine is adjusted for example clock phase, for executing for the first time with second, S is the 1/ of maximum delay setting 4.For third time and all subsequent executions, S is the half of the preceding value of S.
Once step sizes S is less than predetermined minimum adjusting step, then (delay) clock 100 of phase adjustment is invalid (decline) edge is substantially aligned with SYSREF transformation, and clock phase adjustment routine is completed.
Clock invalid edges are changed along with SYSREF control signal if clock phase adjustment does not have enough ranges Alignment, then example clock phase adjustment routine will make delay setting saturation, and useful signal Capture window will be not necessarily aligned The clock invalid edges (placed in the middle) that arrive will be that maximum is prolonged along (Fig. 2, clock invalid edges are aligned along 102 with control signal transformation 21) Twice of the value being arranged late.
It is configured as to repeat by the example binary search routine for clock phase adjustment that controller 450 is implemented SYSREF control signal transformation is centered at clock effective edge between setting/holding window, and is aligned with clock invalid edges edge. The example clock phase method of adjustment assumes that duty ratio is 50% clock.Example clock phase adjustment routine also assumes that SYSREF Controlling signal is that high level is effective, however the routine can be adapted for low level effectively changes.
Example clock phase adjustment routine also uses the fact that clock signal can be inverted polarity, and (Fig. 4 B, clock are anti- Turn the input polarity inverse block 422 that enable signal 451 is provided in adjustable delay clock generator 420).As described above, pole Sex reversal simplifies phase adjustment by the clock phase adjusting range needed for reducing, to optimize the sampling instance of SYSREF.
Fig. 5 provides example waveform, shows clock phase adjustment according to the present invention will be arranged/keep window phase Signal alignment is controlled for repeating SYSREF, so that SYSREF control signal framing be set in signal capture window to meet It sets/keeps and require.
DEVCLK 100 is not adjusted initially, so that SYSREF controls signal 520 in clock effective edge along 101A and clock Invalid edges carry out transformation 521A during clock is height between 102A.After clock phase adjustment, DEVCLK invalid edges edge 102B is aligned with SYSREF transformation 521B.
Clock phase adjustment may be embodied as automatic (such as in power-up) alignment routine.Calibration mode is by calibrating enabled letter Numbers 531 (to the clock generator 410 in Fig. 3 and Fig. 4 A) startings, and terminate 532 after clock phase adjustment, wherein DEVCLK Invalid edges are aligned along 102B with SYSREF control signal transformation 521B.
Within the scope of the claims, the modification in described embodiment is possible, and other embodiments are also It is possible.

Claims (20)

1. a kind of circuit comprising for capturing the clock module of the repeating signal relative to clock, the circuit includes:
Signal input part receives the repeating signal with repeating signal transformation；
Clock circuitry provides the clock with efficient clock edge and inactive clock edge within the clock cycle；
Signal capture circuit system, based on the predetermined set and retention time for determining setting/holding window, on efficient clock side The repeating signal transformation is captured at；And
Clock phase adjustment circuit system adjusts clock phase, so that repeating signal transformation occurs in setting/holding window In signal capture window between mouthful.
2. circuit according to claim 1, wherein the clock has clock high level and clock low within the clock cycle Level, and the clock phase adjustment circuit system includes:
Phase-comparison circuit system, each selected repeating signal transformation is determined the clock level be clock height also It is that clock is low, and generates corresponding comparison of signal phase；And
The clock phase adjustment circuit system is configured as adjusting clock phase based on the comparison of signal phase.
3. circuit according to claim 2, wherein the clock phase adjustment circuit system includes: averager circuit system System, is used to be averaged the continuous phase comparison signal of selected quantity, and generate corresponding averager result；And when described Clock phase-adjusting circuit system is for the averager result based on the comparison of signal phase of the selected quantity come when adjusting Clock phase.
4. circuit according to claim 1, wherein the clock phase adjustment circuit system is configured as: selectively holding The initial polarity of the row clock is inverted to generate polarity inverted clock；And adjust the clock phase of the polarity inverted clock Position.
5. circuit according to claim 1, wherein the clock is consolidating for the duty ratio with substantially 50 percent Determine frequency clock, and wherein the clock phase adjustment circuit is configured as controlling at the inactive clock edge and the repetition Signal transformation alignment processed.
6. circuit according to claim 5, in which:
The clock phase adjustment circuit system includes phase-comparison circuit system, the phase that repeating signal is changed with it is described The phase of clock is compared, and generates corresponding comparison of signal phase；
The clock phase adjustment circuit system is configured as adjusting clock phase with predetermined process；And
For each step,
The phase-comparison circuit system is configurable to generate corresponding clock phase comparison signal, and
The clock phase adjustment circuit system is configured as adjusting clock phase based on the comparison of signal phase.
7. circuit according to claim 6, wherein the clock phase adjustment circuit system is configured as: selectively holding The initial polarity of the row clock is inverted to generate polarity inverted clock；And adjust the clock phase of the polarity inverted clock Position.
8. circuit according to claim 6, in which:
The clock phase adjustment circuit system includes averager circuit system, and the comparison of signal phase of selected quantity is made even , and corresponding averager result is generated；And
The clock phase adjustment circuit system is configured as adjusting clock phase based on the averager result.
9. a kind of for the equipment with multiple equipment and the system of systematic clock generator, the systematic clock generator is provided System equipment clock and repeat control signal, the equipment include:
Clock interface receives the system equipment clock and the repeat control signal with repeat control signal transformation；
Clock module generates internal unit clock based on the system equipment clock and the repeat control signal, when described Clock module includes:
Clock circuitry, based on the system equipment clock is provided within the clock cycle have efficient clock edge and in vain The internal unit clock of clock edge；
Signal capture circuit system, based on the predetermined set and retention time for determining setting/holding window on efficient clock side The repeat control signal transformation is captured at；And
Clock phase adjustment circuit system adjusts clock phase, so that repeat control signal transformation occurs in setting/guarantor It holds in the signal capture window between window.
10. equipment according to claim 9, wherein the system equipment clock has clock high level within the clock cycle And clock low, and the clock phase adjustment circuit system includes:
Phase-comparison circuit system determines that the clock level is clock height for each selected repeat control signal transformation Or clock is low, and generates corresponding comparison of signal phase；And
The clock phase adjustment circuit system is configured as adjusting clock phase based on the comparison of signal phase.
11. equipment according to claim 9, in which:
The clock phase adjustment circuit system includes averager circuit system, by the continuous phase comparison signal of selected quantity It is averaged, and generates corresponding averager result；And
The clock phase adjustment circuit system is configured as the described average of the comparison of signal phase based on the selected quantity Device result adjusts clock phase.
12. equipment according to claim 9, wherein the clock phase adjustment circuit system is configured as: selectively The initial polarity reversion of the system equipment clock is executed, to generate polarity reverse system equipment clock；And adjust the pole The clock phase of sex reversal system equipment clock.
13. equipment according to claim 9, wherein the system equipment clock is accounted for substantially 50 percent The fixed frequency clock of empty ratio, and wherein clock phase adjustment be configured as by the inactive clock edge with it is described heavy Control signal transformation alignment again.
14. equipment according to claim 13, in which:
The clock phase adjustment circuit system includes phase-comparison circuit system, the phase that repeat control signal is changed with The phase of the clock is compared, and generates corresponding comparison of signal phase；
The clock phase adjustment circuit system is configured as adjusting clock phase with predetermined process；And
For each step,
The phase-comparison circuit system is configurable to generate corresponding clock phase comparison signal, and
The clock phase adjustment circuit system is configured as adjusting clock phase based on the comparison of signal phase.
15. equipment according to claim 9, wherein the systematic clock generator is JESD204B (subclass 1) clock hair Raw device provides JESD204B overall situation equipment clock as the system equipment clock, and provides JESD204B SYSREF timing Reference signal is as the repeat control signal.
16. a kind of method for capturing the repeating signal relative to clock, which comprises
Receive the repeating signal with repeating signal transformation；
The clock with efficient clock edge and inactive clock edge is generated within the clock cycle；
Based on the predetermined set and retention time for determining setting/holding window, the repetition is captured in efficient clock edge and is believed Number transformation；And
Clock phase is adjusted so that the signal capture window between setting/holding window occurs for repeating signal transformation It is interior.
17. according to the method for claim 16, wherein the clock is the duty ratio with substantially 50 percent Fixed frequency clock, and wherein clock phase is adjusted to change the inactive clock edge and the repeat control signal Alignment.
18. method described in 620 according to claim 1, wherein based on the system equipment clock and the Repetitive controller is believed Number transformation continuous phase be relatively averaged to adjust clock phase.
19. according to the method for claim 16, wherein anti-to generate polarity based on initial polarity reversion is selectively executed Transfer from one department to another to unite equipment clock and adjusts the clock phase of the polarity reverse system equipment clock then to adjust clock phase.
20. according to the method for claim 16, wherein adjusting clock phase according to binary search routine, in which:
The clock phase adjustment circuit system adjusts clock phase with predetermined process；
For each step, the phase-comparison circuit system generates corresponding clock phase comparison signal, and the clock Phase-adjusting circuit system is based on the comparison of signal phase and adjusts clock phase.
CN201880014749.8A 2017-03-03 2018-03-05 Satisfying set/hold time for repeated signals with respect to clock Active CN110366822B (en)

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