CN101604968A - A kind of channel extensible multi-phase high-performance clock method for designing and system - Google Patents
A kind of channel extensible multi-phase high-performance clock method for designing and system Download PDFInfo
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Abstract
The invention provides a kind of channel extensible multi-phase high-performance clock method for designing and system, method of the present invention mainly is to utilize the clock source to produce global clock, a plurality of clock splitters that are tree-like cascade distribution are extended to multichannel clock with this global clock, programmable delay is regulated the clock phase of every passage, and last logic translator is realized the conversion of clocked logic to the subscriber equipment logic; System of the present invention adopts inside and outside two kinds of global clock sources, wherein internal clock source has adopted oscillator to add fraction frequency device, 11: 5 clock splitter is realized clock source selection and clock along separate routes, wherein 1 tunnel output clock is used for after buffer drives and other device synchronization or the expansion of clock passage, all the other 4 tunnel output clocks are realized phase adjusted by 4 programmable delay respectively, realize clock ECL-CMOS logical transition by buffer at last.The clock signal of output is pervasive to be used in the multichannel multiphase clock, is particularly useful for parallel alternate type analog to digital converter.
Description
Technical field
The present invention is mainly used in multichannel multi-phase signals/data and takes place and data collecting field, is particularly useful for parallel alternately analog-digital converter, and it is a kind of method and system that can effectively produce the multichannel multi-phase high-performance clock.
Background technology
Development along with modern communication, Radar Technology, wideband digital oscilloscope technology, digital medical imaging technique and advanced digital test technology etc., increasing high performance system requires to realize digitlization in AFE (analog front end) as much as possible, so that give full play to the advantage of Digital Signal Processing in design and realization.Therefore, a typical High Speed High Precision ADC (analog-digital converter) of using as high-performance clock becomes both at home and abroad extensively one of critical component of research and development.Wherein, TIADC (Time-Interleaved Analog-to-Digital, parallel alternately analog-digital converter) is considered to one of the most promising ultrahigh speed high-precision adc framework, and its theory diagram as shown in Figure 1.In the ideal case, M passage TIADC utilizes M sheet sample rate to be S, the conversion figure place is the ADC of B, one group of number of active lanes is that M, adjacency channel phase difference are parallel alternation under the clock control of 2 π/M, the digital signal of each road ADC output merges according to the analog-to-digital conversion order and forms way word output (y[n]), thereby realize that the equivalence sampling rate is M * S, the conversion figure place is the analog digital conversion of B.In theory, TIADC provides a kind of effective solution for improving the ADC sample rate simultaneously and changing figure place.Yet because of the imperfection of each channel circuit, there is the clock mismatch in actual TIADC system, has reduced output signal-to-noise ratio (SNR) and the undistorted dynamic range (SFDR) of TIADC.Wherein, TIADC clock phase deviation is exported y[n in numeral] frequency spectrum in introduced the each harmonic and the corresponding image frequency component of input signal.And clock jitter is exported y[n to numeral] influence of frequency spectrum shows as and raised noise floor.Simultaneously, because mismatch parameter obtains difficulty, and reason such as backoff algorithm complexity, TIADC time mismatch is difficult to effectively eliminate by digital signal processing algorithm.Therefore, the adjustable multichannel multiphase clock technology of utmost point low jitter and clock phase deviation becomes one of core technology of high-performance TIADC system.
In addition, the multichannel multiphase clock takes place also to be widely used with the other field of data acquisition in data, for example, for carrying out analog to digital and digital-to-analog conversion, a plurality of ADC on digitizer and the signal generator and DAC produce the timing signal that data and signal provide different sequential, for digital code type generator, analyzer provide multiple timings control signal etc.
The clock generator that is applied to TIADC has three leading indicators: the first, and the delay precision of clock delay device and delay scope.Fig. 1 has described M passage TIADC system principle and clock sequential.Equivalent sampling rate (the F of this TIADC system
s) be M * S hertz, system clock cycle (T
s) (M * S) second, adjacency channel clock skew (Δ ψ) was that (the phase delay Δ is T to 2 π/M to be 1/
s), interchannel maximum clock phase difference (ΔΦ
s) be 2 π M-1)/M (phase delay Δ
sBe (M-1) T
s).This shows, increase TIADC number of active lanes (M) or raising single channel ADC sample rate (S) and all will reduce adjacency channel clock skew (Δ ψ) and increase interchannel maximal phase potential difference (ΔΦ s), promptly improve the clock delay precision and enlarge the delay scope.The clock delay precision has determined TIADC minimum clock deviation, and high-speed, high precision TIADC clock jitter tolerance limit is a picosecond; The second, clock delay independent regulation ability.In order to regulate each channel delay value realizing the TIADC of different sample rates, and compensation is because the clock jitter that clock passage physical characteristic otherness causes, but each road clock delay must independent regulation; The 3rd, clock jitter.Clock jitter is that all ADC systems all will face the problems, and also is the key technology difficult problem of clock circuit design, and the clock jitter tolerance limit of high-speed, high precision TIADC is psec (ps) level.
Document shows, existing multichannel multiphase clock technical scheme all is difficult to satisfy multichannel (M＞2) high-speed, high precision (＞200MSPS, 12bit) TIADC system clock requirement. mainly show: many schemes adopt digital dock administrative unit (DCM) technology based on FPGA to realize the multichannel multiphase clock, but the present intrinsic tens psec clock jitters of fpga chip.Therefore, can not satisfy the utmost point low jitter requirement of TIADC clock based on the clock design of existing fpga chip; In addition, adopting delay line technique also is the mainstream technology scheme that realizes the multichannel multiphase clock, but this technology can not satisfy the adjustable requirement of TIADC clock delay; At last, special multichannel programmable delay Clock management chip can directly be realized multichannel multiphase clock circuit, typical case's representative of these special chips comprises the LMK03000/02000 of National Semiconductor, and (LMK03000 postpones scope 0～2,250 psecs postpone precision 150ps, and clock jitter is less than 1.0ps), and the AD9510/6/7 of Analog Devices Inc (AD9517 postpones scope 0～10,100ps postpones precision 50ps, and clock jitter is less than 0.3ps) etc.Analyze as can be known, be subject to the parameters such as delay scope, delay precision, clock jitter or output clock port number of clock chip self based on the clock design of special chip.For example, the clock designing requirement clock delay range delta of 4 passage 320MSPS 12bit TIADC systems
sBe 9,375ps (i.e. (M-1) T
s, M is 4 here, T
sBe 1/320MHz), postponing precision is ten picosecond, more than two special clock chip all can not satisfy index request fully.
Summary of the invention
Problem to be solved by this invention is the deficiency that overcomes existing clock technology, for TIADC system and other multi channel signals/data take place to provide channel extensible multi-phase high-performance clock method for designing and system with acquisition system.
A kind of channel extensible multi-phase clock circuit method for designing the steps include:
1) the clock source module produces global clock, is sent to the clock shunt module, as shown in Figure 2;
2) the clock shunt module is made up of a plurality of clock splitters that are tree-shaped cascade, and the global clock of importing is carried out multistage expansion, and the output multichannel is with the frequency in-phase clock, and described multichannel reaches the clock delay module with same channels number with the frequency in-phase clock;
3) after each clock delay device of clock delay module carries out the phase place adjustment to the clock that receives respectively, send into clock output interface module separately;
4) the clock output interface module is isolated clock circuit and clock application circuit, and according to the requirement of clock application circuit logic, respectively the clock that receives is carried out logical transition and output.
Described passage expansion can be enlarged by the shunt of the clock splitter in clock shunt module number, or is increased by the clock splitter cascade number of plies, or realizes by many clock trees are in parallel.
The shared global clock source of described each channel clock.
Described each channel clock phase place is by clock delay device independent regulation.
A kind of channel extensible multi-phase high-performance clock Circuits System, it comprises clock source module, clock shunt module, clock delay module and clock output interface module, as shown in Figure 3, it is characterized in that described clock source module comprises an internal clock source, clocking; One external clock input interface receives and the buffering external timing signal; Described clock shunt module comprises a clock splitter, selects internal clocking source signal or external timing signal, drives selected clock source signals and produces five road clocks; Described clock delay module comprises four programmable delay, wherein four road clocks of difference receive clock shunt module output, and independently carry out phase adjusted respectively; Described clock output interface module comprises an EB(extended buffer), receives also residue one road clock of buffered clock shunt module output; Four translation buffers, four tunnel out of phase clocks of difference receive clock Postponement module output, it is penetrated grade coupled logical transition is the CMOS logic.
All modules of described system adopt penetrates grade coupled logic as the clock transfer logic.
The clock chip that all modules of described system adopt can both support to be up to the clock signal of 1.2GHz frequency.
The internal clock source of described clock source module is oscillator+fraction frequency device.
Described clock output interface module adopts buffer but not the special logic transducer realizes penetrating grade coupled logic to the CMOS logical transition.
Global clock is isometric to the transmission path of each road programmable delay of clock Postponement module.
Beneficial effect: the present invention utilizes the same frequency homophase passage expansion of clock trees realization clock, utilizes the clock phase of each passage of programmable delay independent regulation, produces channel extensible multi-phase high-performance clock with the method.Exportable 10MHz～the 1.2GHz of system of the present invention, single channel clock delay are that 10ns, clock delay precision are 10ps, the single channel clock jitter high-performance clock signal less than 1.5ps, 4 passages when 80MHz.In one exemplary embodiment of the present invention, clock system of the present invention is applied to the TIADC system of 4 passages, every passage 80MHz sample rate, 12bit conversion figure place.
Description of drawings
Fig. 1 M passage TIADC theory diagram and clock timing diagram
Fig. 24 tunnel tree-like clock circuit configuration diagram
Fig. 34 passage multiphase clock schematic block circuit diagram
Fig. 4 external clock interface circuit
Fig. 5 internal clocking source circuit
Fig. 6 clock shunt circuit
The clock programmable delay circuit of Fig. 7 passage 4
The clock output interface circuit of Fig. 8 passage 4
Fig. 9 system pictorial diagram
Figure 10 output interface circuit test waveform figure
4 passages, the 90 degree phase difference clock waveform figure of Figure 11 system output
Figure 12 8 passage multi-phase clock systems are provided with schematic diagram
Embodiment
Below in conjunction with accompanying drawing and embodiment method and system of the present invention is described in further detail.Be without loss of generality, describe with method of the present invention should be used in 4 passages, every passage 80MHz sample rate, 12bit conversion figure place TIADC system.
Fig. 3 is 4 passage multiphase clock schematic block circuit diagram, the present invention adopts the global clock source of two kinds of different modes: outside input clock mode and internal clock source mode, the selection in clock source realizes by the clock splitter, oscillator+frequency divider pattern has been adopted in the internal clock source design: the 320MHz high frequency clock signal that oscillator produces is the 80MHz intermediate frequency clock signal of designing requirement by 4 frequency divider frequency reducings; Adopt 11: 5 clock splitter, wherein one tunnel output clock is used for after EB(extended buffer) drives and other device synchronization or the expansion of clock passage, all the other 4 tunnel output clocks are respectively after 4 programmable delay postpone, by the clock signal of translation buffer output as 4 way ADC.
Fig. 4 is the external clock interface circuit, and this circuit and internal clocking source circuit are collectively referred to as clock source circuit.CVDD represents the clock circuit power supply among the figure, down together.The effect of external clock interface circuit is to insert the clock signal that is produced by external clock generation equipment, or with other external function device clock synchronizations, and realize the expansion of clock passage.Consider the performance requirement of clock utmost point low jitter, it is that acp chip carries out the external clock Interface design that the present invention adopts with high-frequency clock buffer MC100EP16D.In order to protect internal circuit, and avoid, but adopt the AC coupled design of isolating exterior clock DC component here because distinct device bias level difference causes logical miss.
Fig. 5 is the internal clocking source circuit, and its effect is the clock signal that produces the low jitter of the 80MHz utmost point.Present existing 80MHz intermediate frequency clock source chip generally adopts the CMOS logic, and CMOS logical signal self shake reaches tens psecs, is difficult to reach the low jitter index request; Secondly, the ECL logical timer source chip of low jitter is mainly used in high frequency occasion (more than the 200MHz), and frequency is too high; Moreover clock jitter can be by clock division (high frequency-low frequency conversion) effective attenuation 20Log (k) decibel (k is a divider ratio).Based on the above-mentioned fact, the present invention has adopted high frequency high-performance ECL logical timer chip and frequency divider collaborative work, realizes the design of intermediate frequency clock source circuit.In the specific design, the present invention has selected the VCSO of VECTRON company (surface acoustic wave oscillator) chip (frequency is 320MHz, and shake is less than 0.5ps) and MC100EVEL33D 4 frequency dividers (shake is less than 0.5ps) for use.
Fig. 6 is the clock shunt circuit, and its effect is the clock source to be controlled select and realize the expansion of clock passage.Help reducing clock jitter in view of shortening clock chain circuit, the present invention has selected for use 1: 5 clock splitter of monolithic MC100EP14D to realize.This chip has following characteristics: when frequency was lower than 1GHz, its clock jitter was less than 0.18ps; Can just realize clock source selection by the level of control pin SEL; Between this chip directly cascade with realize, the expansion of clock passage.
Fig. 7 is the clock programmable delay circuit, and its effect is to realize that by programming the clock phase of place path is regulated and the elimination of clock jitter.The present invention selects for use MC100EP195D to design.This delayer has 10ps and postpones step-length (delay precision), and 10bit postpones control word, and (promptly can produce 1,023 kind of different delay, the delay scope reaches 10,230ps), and shakes less than characteristics such as 1.16ps when 1.2GHz.In theory, the clock circuit adjacency channel ideal delay interval delta of 320MHz TIADC system is 3,125ps (1/320MHz), be zero-lag with passage 0 even, then passage 1, passage 2, passage 3 postponed be respectively 3,125ps, 6 with respect to the ideal time of passage 0,250ps, 9,375ps.Adopt the MC100EP195D chip, can realize then being 0ps from the 0 road to the 3 tunnel delay, 3,120ps, 6,250ps and 9,370ps, corresponding control word D is set to respectively: [0000000000], [0100111000], [1001110001], [1110101001].Certainly, this delayer can realize that also maximum delay is 10ns, and postponing precision is other length of delays of 10ps.
Fig. 8 is the clock output interface circuit, and its effect is to isolate clock circuit and application circuit, and requires to finish the clocked logic conversion according to application circuit, and realizes single-ended-differential conversion.Because clock of the present invention has adopted the ECL transmission logic, directly output (MC100EP195D output) is the ECL clock, and the CMOS logic is often adopted in the intermediate frequency application scenario, can only receive single-ended CMOS logic clock signal as common commercial intermediate frequency ADC chip majority, therefore, the logical transition circuit that needs design low jitter and transmission delay.The logical transition circuit generally adopts special chip to realize, but the shake of ECL-CMOS logical transition chip is very big, and as MC100EPT21 chip commonly used, its clock jitter has substantially exceeded the jitter toleration of high-speed, high precision clock up to 3.5ps.For this reason, in order to be applicable to intermediate frequency (CMOS logic) and high frequency (ECL logic) application scenario simultaneously, the present invention has adopted the ECL-CMOS logical transition circuit of no special logic transducer at the clock circuit output interface circuit, utilizes buffer (translation buffer among Fig. 3) to realize logical transition and clock output.The present invention selects for use high speed low jitter CMOS logic inverter MC74VHC04D chip as buffer.It is 0.8V that this chip requires the logic swing of input, can be reached MC100EP195D chip drives more than the 1.0V, output CMOS logic clock signal by logic swing.This chip clock jitter and transmission delay error can be ignored.AVDD represents applications circuit supply power supply in the circuit diagram, can directly export the ECL clock by ac coupling capacitor CX4, by logical transition circuit output CMOS logical timer, its circuit description is as follows: ac coupling capacitor C27 isolates the direct current biasing of MC100EP195D output ECL clock signal, its value is generally got 0.1uF～0.01uF, and (clock frequency is high more, capacitance is more little), for the 80MHz clock, capacitance is 0.1uF; The direct current biasing that potentiometer R10 resets clock signal is half of MC74VHC04D supply power voltage, is that ECL clocked logic high-low level more than the 1.0V all surpasses the requirement of the MC74VHC04D input signal amplitude of oscillation to guarantee the amplitude of oscillation; MC74VHC04D is the clock buffer chip, and it is output as the cmos clock signal.
Fig. 9 is system's pictorial diagram, and as one exemplary embodiment of the present invention, clock system has been applied in the TIADC system of a cover 4 passage 320MHz12bit, is clock circuit in the great circle of circuit board center among the figure.System of the present invention has taked following circuit layout routing strategy: 1. clock circuit and ADC are integrated on the circuit board, disturb and phase error to avoid long Distance Transmission to introduce; 2. clock circuit and ADC independence on power supply and layout has been avoided the phase mutual interference, and helps both and independently expand or upgrade; 3. take into full account high frequency clock signal coupling and transmission line effect, adopt design of 6 layer circuit boards and interference shielding measure; 4. each clock channel transfer feature unanimity, length difference transmit the clock jitter of introducing less than 15ps less than 1 inch by signal; 5. in order to make each channel clock transmission characteristic unanimity, reduce the channel time mismatch error, 4 channel clocks are the center of circle with the clock splitter, are fan-shaped placement-and-routing.
Figure 10 is output interface circuit test waveform figure, and last waveform is the ECL clock signal of input, and following waveform is the cmos clock signal of output.Test shows that the input waveform is that direct current biasing is zero ECL logical timer, and the amplitude of oscillation is 1.4V, and output waveform is that direct current biasing is 2.5V, and the amplitude of oscillation is the CMOS logical timer of 5V.This interface circuit of test shows, this clock generator can be exported the clock of ECL and CMOS logic simultaneously.
Figure 11 is 4 passage multiphase clock oscillograms of system's output, the oscilloscope phase difference measurement shows that the adjacency channel clock skew is that 90 ± 1.0 degree (are 3.125 ± 0.009ns), promptly for 4 passage 320MSPS TIADC system applies, the system phase delay error that the present invention realizes is ± 9ps.
Figure 12 is that 8 passage multi-phase clock systems are provided with schematic diagram, the i.e. 4 channel clock systems cascade that realizes with two the present invention realizes 8 new channel clock systems of a cover: with the short radio frequency line of sub-miniature A connector, first clock system external clock output interface is connected to another clock system external clock input interface, according to demand configurating programmable delayer.
In addition, the clock jitter method of testing based on the ADC output signal-to-noise ratio commonly used has been adopted in the clock jitter test, its principle is summarized as follows: 4 road clocks of enable clock circuit output carry out the analog digital conversion and control to 4 road ADC, because of the ADC output signal-noise ratio mainly determines that by clock jitter, intrinsic DNL (DNL) and the thermal noise of ADC known signal to noise ratio, DNL and thermal noise can calculate corresponding clock jitter.The 4 channel clocks shake of calculating thus is respectively [1.535 1.679 1.132 1.315] ps.Consider the external clock source of test employing and the shake that the ADC chip has 0.6ps and 0.3ps respectively, so the 4 channel clocks shake that native system is realized is less than 1.5ps.
Claims (10)
1. a channel extensible multi-phase high-speed high-performance clock design method the steps include:
1) the clock source module produces global clock, is sent to the clock shunt module;
2) the clock shunt module is made up of a plurality of clock splitters that are tree-shaped cascade, and the global clock of importing is carried out multistage expansion, and the output multichannel is with the frequency in-phase clock, and described multichannel reaches the identical clock delay module of number of active lanes with the frequency in-phase clock;
3) after each clock delay device of clock delay module carries out the phase place adjustment to the clock that receives respectively, send into the identical clock output interface module of number of active lanes;
4) the clock output interface module is isolated clock circuit and clock application circuit, and according to the requirement of clock application circuit logic, respectively the clock that receives is carried out logical transition and output.
2. channel extensible multi-phase high-speed high-performance clock design method as claimed in claim 1, it is characterized in that the passage expansion can be by the number expansion along separate routes of described clock shunt module clock splitter, or by the increase of the clock splitter cascade number of plies, or by the realization in parallel of many clock trees.
3. channel extensible multi-phase high-speed high-performance clock design method as claimed in claim 1 is characterized in that the shared global clock source of described each channel clock.
4. channel extensible multi-phase high-speed high-performance clock design method as claimed in claim 1 is characterized in that each channel clock phase place independently adjusted by described clock delay device.
5. channel extensible multi-phase high-speed high-performance clock system, it comprises clock source module, clock shunt module, clock delay module and clock output interface module, it is characterized in that described clock source module comprises an internal clock source, clocking; One external clock input interface receives and the buffering external timing signal; Described clock shunt module comprises a clock splitter, selects internal clocking source signal or external timing signal, drives selected signal and produces five road clocks; Described clock delay module comprises four programmable delay, wherein four road clocks of difference receive clock shunt module output, and independently carry out phase adjusted respectively; Described clock output interface module comprises an EB(extended buffer), receives also residue one road clock of buffered clock shunt module output; Four translation buffers, four tunnel out of phase clocks of difference receive clock Postponement module output, it is penetrated grade coupled logical transition is the CMOS logic.
6. channel extensible multi-phase high-speed high-performance clock system as claimed in claim 5 is characterized in that described all clock modules adopt to penetrate grade coupled logic as the clock transfer logic.
7. channel extensible multi-phase high-speed high-performance clock system as claimed in claim 5 is characterized in that clock chip that described all modules adopt can both support to be up to the clock signal of 1.2GHz frequency.
8. channel extensible multi-phase high-speed high-performance clock system as claimed in claim 5, the internal clock source that it is characterized in that described clock source module is oscillator+fraction frequency device.
9. channel extensible multi-phase high-speed high-performance clock system as claimed in claim 5 is characterized in that described clock output interface module adopts buffer but not the special logic transducer realizes penetrating grade coupled logic to the CMOS logical transition.
10. channel extensible multi-phase high-speed high-performance clock system as claimed in claim 5 is characterized in that global clock is isometric to the transmission path of each road programmable delay of clock Postponement module.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102664701A (en) * | 2012-04-19 | 2012-09-12 | 中国科学技术大学 | System and method for dynamically adjusting multichannel and wide-range clock transmission delay |
| CN102890528A (en) * | 2012-09-13 | 2013-01-23 | 曙光信息产业(北京)有限公司 | Low-cost clock multiplex method |
| CN103728893A (en) * | 2013-12-31 | 2014-04-16 | 中国电子科技集团公司第二十二研究所 | High-precision time-sequence control circuit of ground penetrating radar |
| CN105847714A (en) * | 2016-05-24 | 2016-08-10 | 中国科学院长春光学精密机械与物理研究所 | Delayed correction system for input image data of CMOS |
| CN106200762A (en) * | 2016-06-24 | 2016-12-07 | 浪潮电子信息产业股份有限公司 | A kind of clock network |
| CN106530668A (en) * | 2016-12-14 | 2017-03-22 | 天津光电通信技术有限公司 | Miniature collector |
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| CN113156293A (en) * | 2021-03-01 | 2021-07-23 | 南京极景微半导体有限公司 | Multi-channel clock buffer test system and method |
| CN115017081A (en) * | 2022-06-30 | 2022-09-06 | 重庆秦嵩科技有限公司 | Multi-path SRIO interface clock resource sharing system based on domestic FPGA |
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| CN102664701A (en) * | 2012-04-19 | 2012-09-12 | 中国科学技术大学 | System and method for dynamically adjusting multichannel and wide-range clock transmission delay |
| CN102890528A (en) * | 2012-09-13 | 2013-01-23 | 曙光信息产业(北京)有限公司 | Low-cost clock multiplex method |
| CN103728893A (en) * | 2013-12-31 | 2014-04-16 | 中国电子科技集团公司第二十二研究所 | High-precision time-sequence control circuit of ground penetrating radar |
| CN103728893B (en) * | 2013-12-31 | 2016-05-11 | 中国电子科技集团公司第二十二研究所 | A kind of GPR high accuracy sequential control circuit |
| CN105847714A (en) * | 2016-05-24 | 2016-08-10 | 中国科学院长春光学精密机械与物理研究所 | Delayed correction system for input image data of CMOS |
| CN106200762A (en) * | 2016-06-24 | 2016-12-07 | 浪潮电子信息产业股份有限公司 | A kind of clock network |
| CN106530668A (en) * | 2016-12-14 | 2017-03-22 | 天津光电通信技术有限公司 | Miniature collector |
| CN109217869A (en) * | 2017-07-03 | 2019-01-15 | 美国莱迪思半导体公司 | PLL phase rotator system and method |
| CN109217869B (en) * | 2017-07-03 | 2024-04-05 | 美国莱迪思半导体公司 | PLL phase rotator system and method |
| CN108182161A (en) * | 2018-01-02 | 2018-06-19 | 沈阳东软医疗系统有限公司 | A kind of data processing system and method |
| CN108182161B (en) * | 2018-01-02 | 2020-06-16 | 东软医疗系统股份有限公司 | Data processing system and method |
| CN110244609A (en) * | 2019-05-31 | 2019-09-17 | 西安交通大学 | A kind of hardware circuit for eliminating semiconductor laser interference signal amplitude modulation |
| CN113156293A (en) * | 2021-03-01 | 2021-07-23 | 南京极景微半导体有限公司 | Multi-channel clock buffer test system and method |
| CN115017081A (en) * | 2022-06-30 | 2022-09-06 | 重庆秦嵩科技有限公司 | Multi-path SRIO interface clock resource sharing system based on domestic FPGA |
| CN115017081B (en) * | 2022-06-30 | 2023-06-23 | 重庆秦嵩科技有限公司 | Multipath SRIO interface clock resource sharing system based on domestic FPGA |
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