CN111736517A - Synchronous acquisition and processing card system based on multichannel ADC and FPGA - Google Patents
Synchronous acquisition and processing card system based on multichannel ADC and FPGA Download PDFInfo
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- CN111736517A CN111736517A CN202010788163.6A CN202010788163A CN111736517A CN 111736517 A CN111736517 A CN 111736517A CN 202010788163 A CN202010788163 A CN 202010788163A CN 111736517 A CN111736517 A CN 111736517A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
Abstract
The invention discloses a synchronous acquisition processing card system based on a multichannel ADC (analog to digital converter) and an FPGA (field programmable gate array), which comprises a clock management unit, a plurality of ADC chips, two FPGA chips, a plurality of groups of DDR3 chips and a power distribution network. The clock management unit generates a plurality of paths of synchronous sampling clocks and a reference clock, and the plurality of ADC chips are used for collecting and converting intermediate-frequency signals accessed by the SMP. The invention relates to the technical field of ultra-high-speed data acquisition and processing, a sampling clock management unit provides a sampling clock and a reference clock required by synchronous sampling of a plurality of ADCs (analog to digital converters), the number of ADC channels is convenient to expand, and data acquisition, processing and caching are completed by an ADC + FPGA + DDR3 framework, so that the invention has the advantages of more synchronous acquisition channels, large data storage capacity, strong processing capacity, wide data transmission bandwidth and the like, and can meet the market demand of array signal processing on multichannel synchronous data acquisition.
Description
Technical Field
The invention relates to the technical field of ultra-high-speed data acquisition and processing, in particular to a synchronous acquisition and processing card system based on a multi-channel ADC (analog to digital converter) and an FPGA (field programmable gate array).
Background
The synchronous acquisition and processing card system of the multichannel ADC and the FPGA is mainly applied to the occasions requiring synchronous acquisition and processing of multichannel data, such as array signal processing, a multichannel radio monitoring direction-finding system, a communication radar testing instrument and the like, and the application requires that an acquisition and processing board has high-speed and high-precision data acquisition capacity, can synchronously acquire multichannel input signals, and performs high-speed data processing and high-speed data transmission.
Most of the current acquisition and processing boards in the industry are constructed by 1-2 ADC chips and FPGA chips, and have the defects of low sampling rate, incapability of adapting to multi-path synchronous high-speed high-precision acquisition and storage, small transmission bandwidth, poor signal processing and data processing capabilities and the like.
Disclosure of Invention
The invention aims to solve the problems and provides a synchronous acquisition and processing card system based on a multi-channel ADC and an FPGA.
In order to achieve the purpose, the invention adopts the following technical scheme:
a synchronous acquisition and processing card system based on a multichannel ADC (analog to digital converter) and an FPGA (field programmable gate array) comprises a clock management unit, a plurality of ADC chips, two FPGA chips, a plurality of groups of DDR3 chips and a power distribution network, wherein the clock management unit generates a multi-path synchronous sampling clock and a reference clock, the ADC chips are used for acquiring and converting intermediate-frequency signals accessed by the SMP, the plurality of AD chips are communicated with an FPGA1, the FPGA1 is communicated with the FPGA2, the FPGA1 realizes high-speed sampling data output through a high-speed VPX connector of a board card, and the FPGA2 is communicated with a control computer or another synchronous acquisition and processing card through the high-speed VPX connector of the board card.
As a further description of the above technical solution:
the clock management unit comprises a 100MHz crystal oscillator, a voltage-controlled oscillator VCXO chip and a phase-locked loop PLL chip supporting JESD204B with low phase noise, the clock management unit is used for carrying out equal length processing on a sampling clock and a reference clock and then distributing the processed sampling clock and the reference clock to a plurality of ADC chips, each ADC chip corresponds to one sampling clock and one reference clock and simultaneously provides a synchronous data receiving clock for FPGA1 and FPGA 2;
the clock management unit can generate multiple sampling clocks with the maximum 2500MHz, each output clock has the same phase, and the clock phases are independently adjusted;
the clock management unit outputs a differential reference clock to the outside of the board card, receives the differential reference clock input from the outside of the board card, and is used for expanding synchronous cascading use among the board cards.
As a further description of the above technical solution:
the multi-channel intermediate frequency signals accessed by the SMPs on the multiple ADC chips are connected to the multi-channel SMP connectors on the board through P2 and P6 interfaces of a VPX connector and radio frequency cables, each multi-channel SMP connector corresponds to one ADC, the multi-channel intermediate frequency signals are respectively transmitted to the multiple ADC chips through the SMPs, the intermediate frequency signals are coupled through a front-end transformer, single-ended signals are converted into differential signals and then input into the ADC chips, the sampling rate of the ADC chips is 14bit/1000Msps or 12bit/2500Msps for sampling, the sampling data of the multiple ADC chips are input into FPGA1 for processing through a JESD204B protocol, the synchronous receiving of clocks and data is completed in the FPGA1, and the FPGA1 performs time frequency analysis through FFT and triggers data acquisition, storage and forwarding according to the level.
As a further description of the above technical solution:
the FPGA1 selects Virtex-7 series XC7VX690T-2FFG1927I chips, the FPGA1 is used for receiving and processing multi-path sampling data output by a plurality of ADC chips, buffering the triggered and collected data to a DDR3 memory or directly forwarding and outputting the data through a VPX connector, and transmitting the processed data to the FPGA 2;
the FPGA2 selects Virtex-7 series XC7K325T-2FFG900I chips for further operating data sent by the FPGA1, caches and packs an operation result and transmits the operation result to the upper computer, and the FPGA2 also forwards various control instructions and data of the upper computer to the FPGA 1;
the FPGA1 and the FPGA2 are connected through a group of GTX-X4, at least twenty pairs of LVDS are connected in parallel between the FPGA1 and the FPGA2, JTAG strings of the FPGA1 and the FPGA2 form a daisy chain, and a JTAG debugging interface adopts a J30J connector and outputs the JTAG debugging interface to a front panel of the board card.
As a further description of the above technical solution:
the FPGA1 is connected to a P3 port of a VPX connector of the board card through a group of GTX-X8 high-speed serial buses and is used for outputting high-speed sampling data;
the FPGA2 is connected to a P1 port of a VPX connector of the board card through two groups of GTX-X4 high-speed serial buses and used for outputting a signal processing result;
the line rate of each lane of the high-speed serial bus GTX is 6.25Gbps at most, and the data transmission requirement of 5GB/s at most is met.
As a further description of the above technical solution:
the FPGA1 and the FPGA2 are respectively externally connected with two groups of DDR3 memories, the capacity of each group of DDR3 memory is 128MB to 512MB, the data bit width is 32bit, the two groups of DDR3 are combined into one group of memory with the data bit width of 64bit, and the multiple groups of DDR3 memories are used for caching the sampling data or the signal processing result of the ADC chip.
As a further description of the above technical solution:
the FPGA2 is externally connected with an RS-422/RS-485 interface chip, and is used for carrying out remote data transmission or control through an RS-422/RS-485 bus, wherein the highest transmission data rate is 10 Mbps;
the FPGA2 is externally connected with two MLVDS interface chips, supports eight-path MLVDS bus communication, and is used for real-time data interaction among different boards in the same equipment, and the transmission rate is more than 125 Mbps.
As a further description of the above technical solution:
the FPGA2 is externally connected with a gigabit network PHY chip, the gigabit network PHY chip is connected with an RJ45 connector of a board card front panel through a GMII mode and used for board card debugging, and the gigabit network PHY chip is connected with a VPX connector through an SGMII mode and used for external data interaction or used for board card debugging.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
1. in the invention, the sampling clock management unit provides a sampling clock and a reference clock required by synchronous sampling of a plurality of ADCs, the number of ADC channels is conveniently expanded, the sampling rate of an ADC chip is 14bit/400MSPS or 12bit/2500MSPS, data acquisition, processing and caching are completed by an ADC + FPGA + DDR3 framework, and the FPGA selects XC7VX690T-2FFG1927I chips with high speed GTX quantity and rich resources, so that the invention has the advantages of large number of synchronous acquisition channels, large data storage capacity, strong processing capacity, wide data transmission bandwidth and the like, and can meet the market demand of array signal processing on multichannel synchronous data acquisition.
2. In the invention, 2 pieces of FPGA are adopted for cooperative processing, wherein one piece is used for receiving and processing a plurality of pieces of ADC data, and the other piece is used as a coprocessor and is responsible for an external data interaction interface, so that the balance of cost, volume and power consumption is realized, and the application requirements of different occasions are met by flexibly cutting the number of channels.
Drawings
FIG. 1 is a schematic block diagram of one embodiment of the present invention;
FIG. 2 is a schematic diagram of a clock distribution structure according to the present invention;
fig. 3 is a schematic diagram of a board connection structure according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The first embodiment is as follows:
referring to fig. 1, a synchronous acquisition and processing card system based on a multichannel ADC and an FPGA includes a clock management unit, N ADC chips, two FPGA chips, four sets of DDR3 chips, and a power distribution network, where N analog intermediate frequency signals input from a VPX connector P6 or P2 are respectively connected to multiple SMP access ends through radio frequency cables, coupled through a front-end transformer, converted into differential signals by single-ended signals, and input into corresponding ADC chips, the ADC chips select an AD9680BCPZ-1000 chip with a sampling rate of 14bit/1000Msps or an AD9625BBPZ-2.5 chip with a sampling rate of 12bit/2500Msps, sampling data of the multiple ADC chips are transmitted to an FPGA1 through a JESD204B protocol, an FPGA1 selects a Virtex-7 series XC7VX690T-2FFG 192690-1927I chip, and synchronous reception of clocks and data is completed in an FPGA 1; the FPGA1 performs time-frequency analysis through FFT and triggers data acquisition, storage and forwarding according to the level.
The FPGA1 is connected with a P3 port of a high-speed VPX connector of the board card through a group of GTX-X8 high-speed serial buses and is used for outputting high-speed sampling data; the FPGA2 is connected with a P1 port of a high-speed VPX connector of the board card through two groups of GTX-X4 high-speed serial buses and is used for outputting signal processing results and controlling data interaction; the FPGA1 and the FPGA2 are connected and communicated through GTX-X4; the line rate of each lane of the GTX high-speed serial bus is 6.25Gbps at most, supports RapidIO or Aurora high-speed serial data transmission protocol, and can meet the data transmission requirement of 5GB/s at most; at least twenty pairs of LVDS parallel connections are included between FPGA1 and FPGA2 for transferring data and control information to each other.
The FPGA1 and the FPGA2 are respectively externally connected with two groups of DDR3 memory chips, the DDR3 chips are MT41K256M16YW-125, the capacity of each group of DDR3 memory is 128MB to 512MB, the data bit width is 32bit, the two groups of DDR3 are combined into one group of memory with the data bit width of 64bit, and the memory can also be combined into two groups of ping-pong memories with the data bit width of 32bit for switching use.
As shown in fig. 2, the clock management unit includes a 100MHz crystal oscillator, a voltage controlled oscillator VCXO chip and a phase locked loop PLL chip supporting JESD204B with low phase noise, and the clock management unit performs equal length processing on the sampling clock and the reference clock and then distributes the processed sampling clock and reference clock to the multiple ADC chips, where each ADC chip corresponds to one sampling clock and one reference clock.
Each output clock has the same phase and the clock phases can be adjusted independently.
The clock management unit can output the differential reference clock to the outside of the board card and also can receive the differential reference clock input to the outside of the board card, and is used for expanding synchronous cascade use among the board cards.
JTAG strings of the FPGA1 and the FPGA2 form a daisy chain, a JTAG debugging interface adopts a J30J connector and outputs the JTAG debugging interface to a front panel of the board card, and four groups of the front panel of the board card comprise eight indicating lamps which are used for indicating a power supply, an ADC/FPGA working state, a clock state, a data transmission state and the like.
Example two:
in this embodiment, as shown in fig. 1, the FPGA2 is externally connected to an RS-422/485 interface chip, and the RS-422/485 chip selects MAX3491/MAX3485, and receives externally input timing information or mutual communication information through an RS-422/485 bus; the data transmission or control in a long distance is realized through an MLVDS bus or an RS-422/485 bus; the FPGA2 is externally connected with a gigabit network PHY chip, the chip type is 88E1111-B2-BAB1i000, the PHY chip is connected with an RJ45 connector of a front panel of the board card through a GMII mode and used for debugging the board card, and the PHY chip is connected with a VPX connector through an SGMII mode and used for external communication or used for debugging the board card.
In the embodiment, an MLVDS data transmission bus for communication among a plurality of boards and an RS-422/485 data transmission bus for communication among equipment are added, so that the communication capacity among boards or equipment with different distances is expanded, and the data transmission requirements of various application occasions are met.
Example three:
in this embodiment, as shown in fig. 3, the board 1, the board 2, and the board 3 are three same synchronous acquisition and processing cards of the multi-channel ADC and the FPGA of embodiment 1, the board 1 outputs 1 path of reference clock and is connected to the reference clock input terminal of the board 2 through the backplane, and the board 2 outputs 1 path of reference clock and is connected to the reference clock input terminal of the board 3 through the backplane, so that the clocks of the 3 boards are synchronized, so that the total 3 × N sampling clocks and the 3 × N reference clocks of the board 1, the board 2, and the board 3 have a stable phase synchronization relationship, thereby synchronizing the sampling data of the 3 × N ADCs of the 3 boards, and implementing synchronous sampling of the 3 × N data. Within the tolerance range of the cascade clock, synchronous sampling of more ADC chips can be realized, and the application requirements of multi-channel data synchronous sampling processing such as array signal processing and the like are met.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.
Claims (8)
1. The synchronous acquisition and processing card system based on the multichannel ADC and the FPGA is characterized by comprising a clock management unit, a plurality of ADC chips, two FPGA chips, a plurality of groups of DDR3 chips and a power distribution network, wherein the clock management unit generates a plurality of synchronous sampling clocks and a plurality of reference clocks, the plurality of ADC chips are used for acquiring and converting intermediate-frequency signals accessed by the SMP, the plurality of ADC chips are communicated with an FPGA1, the FPGA1 is communicated with the FPGA2, the FPGA1 outputs sampling data in real time through a high-speed VPX connector of a board card, and the FPGA2 is communicated with a control computer or another synchronous acquisition and processing card through the high-speed VPX connector of the board card.
2. The synchronous acquisition and processing card system based on multichannel ADC and FPGA according to claim 1, wherein the clock management unit comprises a 100MHz crystal oscillator, a voltage controlled oscillator VCXO chip and a phase-locked loop PLL chip supporting JESD204B with low phase noise, the clock management unit is used for performing equal length processing on the sampling clock and the reference clock and then distributing the processed sampling clock and the reference clock to a plurality of ADC chips, each ADC chip corresponds to one path of sampling clock and one path of reference clock and provides synchronous data receiving clocks for FPGA1 and FPGA 2;
the clock management unit can generate multiple sampling clocks with the maximum 2500MHz, each output clock has the same phase, and the clock phases are independently adjusted;
the clock management unit outputs a differential reference clock to the outside of the board card, receives the differential reference clock input from the outside of the board card, and is used for expanding synchronous cascading use among the board cards.
3. The synchronous acquisition and processing card system based on the multichannel ADC and the FPGA as claimed in claim 1, wherein multiple paths of intermediate frequency signals accessed by the SMPs on the multiple ADC chips are connected to multiple paths of SMP connectors on the board through P2 and P6 interfaces of a VPX connector and a radio frequency cable, each path of SMP connector corresponds to one ADC, the multiple paths of intermediate frequency signals are respectively transmitted to the multiple ADC chips through the SMPs, the intermediate frequency signals are coupled through a front-end transformer, single-end signals are converted into differential signals, and then the differential signals are input into the ADC chips, the sampling rate of the ADC chips is up to 14bit/1000Msps or 12bit/2500Msps sampling, the sampling data of the multiple ADC chips are input into the FPGA1 through a JESD204B protocol for processing, synchronous reception of clock and data is completed in the FPGA1, and the FPGA1 performs time frequency analysis through FFT and triggers time frequency data acquisition, storage and forwarding according to the level.
4. The synchronous acquisition and processing card system based on the multichannel ADC and the FPGA as claimed in claim 1, wherein the FPGA1 adopts Virtex-7 series XC7VX690T-2FFG1927I chip, the FPGA1 is used for receiving and processing multi-path sampling data output by a plurality of ADC chips, buffering the data triggering acquisition to a DDR3 memory or directly outputting the data through a VPX connector, and transmitting the processed data to the FPGA 2;
the FPGA2 selects Virtex-7 series XC7K325T-2FFG900I chips for further operating data sent by the FPGA1, caches and packs an operation result and transmits the operation result to the upper computer, and the FPGA2 also forwards various control instructions and data of the upper computer to the FPGA 1;
the FPGA1 and the FPGA2 are connected through a group of GTX-X4, at least twenty pairs of LVDS are connected in parallel between the FPGA1 and the FPGA2, JTAG strings of the FPGA1 and the FPGA2 form a daisy chain, and a JTAG debugging interface adopts a J30J connector and outputs the JTAG debugging interface to a front panel of the board card.
5. The synchronous acquisition and processing card system based on the multichannel ADC and the FPGA as claimed in claim 1, wherein the FPGA1 is connected to the P3 port of the VPX connector of the board card through a set of GTX-X8 high-speed serial buses to output data in real time;
the FPGA2 is connected to a P1 port of a VPX connector of the board card through two groups of GTX-X4 high-speed serial buses and is communicated with a control computer or another synchronous acquisition and processing card;
the line rate of each lane of the high-speed serial bus GTX is 6.25Gbps at most, and the data transmission requirement of 5GB/s at most is met.
6. The synchronous acquisition and processing card system based on the multichannel ADC and the FPGA as claimed in claim 1, wherein the FPGA1 and the FPGA2 are externally provided with two sets of DDR3 memories respectively, each set of DDR3 memory has a capacity of 128MB to 512MB, a data bit width is 32bit, the two sets of DDR3 are combined into a set of memory with a data bit width of 64bit, and the multiple sets of DDR3 memories are used for caching sampling data or signal processing results of ADC chips.
7. The synchronous acquisition and processing card system based on the multichannel ADC and the FPGA as claimed in claim 1, wherein the FPGA2 is externally connected with an RS-422/RS-485 interface chip, and performs remote data transmission or control through an RS-422/RS-485 bus, and the transmission data rate is up to 10 Mbps;
the FPGA2 is externally connected with two MLVDS interface chips, supports eight-path MLVDS bus communication, and is used for real-time data interaction among different boards in the same equipment, and the transmission rate is more than 125 Mbps.
8. The synchronous acquisition and processing card system based on the multichannel ADC and the FPGA as claimed in claim 1, wherein the FPGA2 is externally connected with a gigabit network PHY chip, the gigabit network PHY chip is connected with the RJ45 connector of the front panel of the board card through a GMII mode for debugging the board card, and the gigabit network PHY chip is connected with the VPX connector through an SGMII mode for debugging the board card or for external communication.
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