CN211015495U

CN211015495U - Bus architecture and case type acquisition instrument with same

Info

Publication number: CN211015495U
Application number: CN202020167943.4U
Authority: CN
Inventors: 李旭杰
Original assignee: CHINA ORIENT INSTITUTE OF NOISE & VIBRATION
Current assignee: CHINA ORIENT INSTITUTE OF NOISE & VIBRATION
Priority date: 2020-02-12
Filing date: 2020-02-12
Publication date: 2020-07-14
Anticipated expiration: 2030-02-12

Abstract

The utility model relates to the technical field of network data cascade, and provides a bus architecture and a chassis type acquisition instrument with the same, wherein the bus architecture comprises a backboard and a board card, the backboard comprises an exchange PHY chip supporting 1588 protocol, the exchange PHY chip comprises a plurality of network physical layer interfaces, and two of the plurality of network physical layer interfaces are reserved interfaces; the board card comprises a network PHY chip supporting a 1588 protocol, and the network PHY chip is connected with a network physical layer interface except the reserved interface through an Ethernet. Because the network PHY chip of the board card is connected with the network physical layer interface of the backboard through the Ethernet, namely the backboard is directly connected with the board card through the network, the whole data transmission on the backboard has strong stability and anti-interference performance due to the characteristics of the network, and the connection between the backboard and the board card is simple, thereby reducing the manufacturing cost and having simple structure.

Description

Bus architecture and case type acquisition instrument with same

Technical Field

The disclosure relates to the technical field of network data cascade, in particular to a bus architecture and a chassis type acquisition instrument with the same.

Background

At present, the multi-board card machine box type acquisition instrument is widely adopted in dozens to hundreds of multi-channel acquisition instruments, and meanwhile, the board cards can be randomly replaced and combined, so that convenience is provided for modularization, function and performance change of the acquisition instrument. Two problems need to be solved when different board cards of a chassis type acquisition instrument are put together for use, namely how to gather and transmit data of all board cards in one chassis, how to accurately synchronize the acquired data among all board cards, and the synchronization precision directly determines the inter-channel phase consistency index of the acquisition instrument.

At present, common bus architectures of chassis type acquisition instruments include CPCI, PCIE and the like, but most chassis based on the bus architectures have high cost and high power consumption, and development of board cards based on the bus architectures has certain difficulty.

SUMMERY OF THE UTILITY MODEL

It is a primary object of the present disclosure to overcome at least one of the above-mentioned drawbacks of the prior art, and to provide a bus architecture and a chassis-type collection instrument having the same.

According to a first aspect of the present invention, there is provided a bus architecture, comprising:

the system comprises a backboard, a network interface module and a communication module, wherein the backboard comprises an exchange PHY chip supporting a 1588 protocol, the exchange PHY chip comprises a plurality of network physical layer interfaces, and two of the plurality of network physical layer interfaces are reserved interfaces;

and the board card comprises a network PHY chip supporting a 1588 protocol, and the network PHY chip is connected with the network physical layer interface except the reserved interface through the Ethernet.

In an embodiment of the present invention, the number of the switching PHY chips is plural, and two switching PHY chips are connected through the MAC layer;

two exchange PHY chips in the plurality of exchange PHY chips respectively comprise a reserved interface.

In an embodiment of the present invention, the switching PHY chip further includes:

a plurality of MAC layer interfaces;

the switching engine supports a 1588 protocol, and a plurality of network physical layer interfaces are connected with the switching engine through MAC layer interfaces.

In an embodiment of the present invention, the board card further includes:

the central processing unit is connected with the network PHY chip;

and the network PHY chip is connected with the AD chip.

In an embodiment of the present invention, the network PHY chip includes a clock input pin and a pulse output pin, and the AD chip includes a clock input pin and a reset pin, and the clock output pin and the pulse output pin are connected to the clock input pin and the reset pin, respectively.

The utility model discloses an in the embodiment, the integrated circuit board is a plurality of, and each network PHY chip of a plurality of integrated circuit boards all is connected with network physical layer interface through ethernet.

According to a second aspect of the present invention, there is provided a bus architecture, comprising:

the backplane comprises a switching PHY chip supporting 1588 protocol;

the board card comprises a network PHY chip supporting a 1588 protocol;

the network PHY chip is connected with the exchange PHY chip through the Ethernet.

According to a third aspect of the present invention, there is provided a case type collecting instrument, comprising a body, wherein the body comprises the bus framework and the case;

the bus architecture is arranged in the chassis.

The utility model discloses an in the embodiment, integrated circuit board detachably sets up at quick-witted incasement to after the integrated circuit board breaks away from quick-witted case, can be connected through the ethernet with the host computer.

In an embodiment of the present invention, the plurality of bodies are connected to each other through an ethernet.

The utility model discloses a bus framework comprises backplate and integrated circuit board, and the host computer is spread into through the backplate to the data that the integrated circuit board will be gathered. Because the network PHY chip of the board card is connected with the network physical layer interface of the backboard through the Ethernet, namely the backboard is directly connected with the board card through the network, the whole data transmission on the backboard has strong stability and anti-interference performance due to the characteristics of the network, and the connection between the backboard and the board card is simple, thereby reducing the manufacturing cost and having simple structure. Compared with the traditional bus architecture, the cost and the power consumption are greatly reduced, and because the platform supporting the network is very popular, the development difficulty of the board card is also greatly reduced, and the board card is also beneficial to upgrading and replacing. Based on the network connection mode, the connection is less, the anti-interference capability is strong, and the product stability is greatly improved compared with the prior art.

Drawings

Various objects, features and advantages of the present disclosure will become more apparent from the following detailed description of preferred embodiments thereof, when considered in conjunction with the accompanying drawings. The drawings are merely exemplary illustrations of the disclosure and are not necessarily drawn to scale. In the drawings, like reference characters designate the same or similar parts throughout the different views. Wherein:

FIG. 1 is a schematic diagram of an application architecture of a bus architecture, shown in accordance with an exemplary embodiment;

FIG. 2 is a partial architectural diagram illustrating a bus architecture in accordance with an exemplary embodiment.

The reference numerals are explained below:

10. a back plate; 11. a switching PHY chip; 111. a network physical layer interface; 112. an MAC layer interface; 113. a switching engine; 12. reserving an interface; 20. a board card; 21. a network PHY chip; 22. a central processing unit; 23. an AD chip; 30. a case.

Detailed Description

Exemplary embodiments that embody features and advantages of the present disclosure are described in detail below in the specification. It is to be understood that the disclosure is capable of various modifications in various embodiments without departing from the scope of the disclosure, and that the description and drawings are to be regarded as illustrative in nature, and not as restrictive.

In the following description of various exemplary embodiments of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration various exemplary structures, systems, and steps in which aspects of the disclosure may be practiced. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps may be utilized and structural and functional modifications may be made without departing from the scope of the present disclosure. Moreover, although the terms "over," "between," "within," and the like may be used in this specification to describe various example features and elements of the disclosure, these terms are used herein for convenience only, e.g., in accordance with the orientation of the examples in the figures. Nothing in this specification should be construed as requiring a specific three dimensional orientation of structures in order to fall within the scope of this disclosure.

An embodiment of the present invention provides a bus architecture, please refer to fig. 1 and fig. 2, the bus architecture includes: the backplane 10, the backplane 10 includes a switching PHY chip 11 supporting 1588 protocol, the switching PHY chip 11 includes a plurality of network physical layer interfaces 111, and two of the plurality of network physical layer interfaces 111 are reserved interfaces 12; the board 20, the board 20 includes a network PHY chip 21 supporting 1588 protocol, and the network PHY chip 21 is connected to the network physical layer interface 111 except the reserved interface 12 through ethernet.

The utility model discloses a bus architecture of an embodiment comprises backplate 10 and integrated circuit board 20, and the host computer is gone into through backplate 10 to the data that integrated circuit board 20 will gather. Because the network PHY chip 21 of the board card 20 is connected to the network physical layer interface 111 of the backplane 10 through the ethernet, that is, the backplane 10 and the board card 20 are directly connected through the network, due to the characteristics of the network, the whole data transmission on the backplane 10 has strong stability and anti-interference performance, and the connection with the board card 20 is simple, so that the manufacturing cost is reduced, and the structure is simple. Compared with the traditional bus architecture, the cost and the power consumption are greatly reduced, and because the platform supporting the network is very popular, the development difficulty of the board card 20 is also greatly reduced, and the upgrading and the replacement of the board card 20 are also facilitated. Based on the network connection mode, the connection is less, the anti-interference capability is strong, and the product stability is greatly improved compared with the prior art.

In one embodiment, since the backplane 10 and the board card 20 are connected through a network, the transmission capability of the network is strong, so that the connection lines between the backplane 10 and the board card 20 are also greatly reduced, thereby ensuring the connection stability between the backplane 10 and the board card 20.

In one embodiment, the switching PHY chip 11 of the backplane 10 supports 1588 protocol, and the network PHY chip 21 of the board 20 also supports 1588 protocol, so that data aggregation and synchronization of each board 20 can be satisfied. The different boards 20 implement data summarization through the switching function of the switching PHY chip 11 of the backplane 10.

In an embodiment, the switching PHY chip 11 includes a plurality of network physical layer interfaces 111, that is, the switching PHY chip 11 employs a multi-port network switching chip supporting 1588 protocol, and in a specific use, since it is required to ensure that the bus architecture can be connected to an upper computer, the network physical layer interface 111 must ensure one reserved interface 12, and the two reserved interfaces 12 here are capable of implementing serial connection between two bus architectures. When there is one switching PHY chip 11, it has two reserved interfaces 12, when there are two switching PHY chips 11, each switching PHY chip 11 has one reserved interface 12, and when there are three or more switching PHY chips 11, it is only necessary to ensure that two of the switching PHY chips 11 have one reserved interface 12.

In one embodiment, the number of switching PHY chips 11 with different numbers of network PHY interfaces 111 may be selected according to the number of boards 20.

In one embodiment, the switching PHY chip 11 of the backplane 10 supports the 1588 protocol, and can calculate the retention time of the 1588 synchronization packet in the switching process, thereby improving the synchronization accuracy of the 1588 protocol.

In one embodiment, the network PHY chip 21 of the board card 20 supports the 1588 protocol, and can capture the 1588 timestamp at the frontmost physical layer of the network, so that the time synchronization error of the 1588 protocol is minimized, and the synchronization precision can reach about 10ns by matching with the switching PHY chip 11 of the backplane 10, thereby realizing time and frequency synchronization of each board card 20, and meeting the inter-channel phase difference requirement of a single independent acquisition instrument.

In one embodiment, since the board 20 is connected to the backplane 10 via ethernet, that is, after the board 20 is separated from the bus architecture, the board 20 can be an independent acquisition instrument due to the convenience of the network interface, which greatly improves the utilization rate of the board 20, that is, the board 20 can be directly connected to the host computer via ethernet.

In one embodiment, as shown in fig. 1, there are a plurality of switching PHY chips 11, and two switching PHY chips 11 are connected to each other through a MAC layer; two switching PHY chips 11 of the plurality of switching PHY chips 11 each include a reserved interface 12. In order to match the number of the boards 20, that is, the switching PHY chips 11 may be multiple, and the switching PHY chips 11 are interconnected through the MAC layer, the interconnection of the multiple switching PHY chips 11 satisfies the application of the chassis-type acquisition instrument with more boards.

In one embodiment, the board card 20 is connected to the backplane 10 through a network, only four lines are needed for hundreds of megabytes, and only eight lines are needed for gigabytes, so that the connection stability is greatly enhanced.

In one embodiment, the switching PHY chip 11 further includes: a plurality of MAC layer interfaces 112, the MAC layer interfaces 112; the switching engine 113 supporting the 1588 protocol, and the plurality of network physical layer interfaces 111 are all connected with the switching engine 113 through the MAC layer interface 112.

In one embodiment, as shown in fig. 2, the switching PHY chip 11 is composed of a plurality of network physical layer interfaces 111, a plurality of MAC layer interfaces 112, and a switching engine 113 supporting 1588 protocol, and each network physical layer interface 111 is connected to the switching engine 113 through each MAC layer interface 112. For example, the PHY1 of the switch PHY chip 11 is connected to the switch engine 113 via MAC1, the PHY2 of the switch PHY chip 11 is connected to the switch engine 113 via MAC2, and the

PHYs

1 and 2 are connected to the network PHY chips 21 of the two boards 20, respectively.

As shown in fig. 2, the board card 20 further includes: the central processing unit 22, the central processing unit 22 is connected with the network PHY chip 21; the AD chip 23, the network PHY chip 21 and the AD chip 23 are connected.

In one embodiment, the network PHY chip 21 includes a clock output pin and a pulse output pin, and the AD chip 23 includes a clock input pin and a reset pin, which are connected to the clock input pin and the reset pin, respectively. The working clock of the AD chip 23 directly or indirectly originates from the network PHY chip 21, and it is ensured that the sampling frequencies are consistent when different board cards 20 sample. And the work reset signal of the AD chip 23 directly or indirectly comes from the network PHY chip 21, so as to ensure that different board cards 20 start AD sampling at the same time.

In one embodiment, as shown in fig. 2, the board 20 includes a network PHY chip 21, a central processing unit 22(CPU), and an AD chip 23. The CPU is connected to the network PHY chip 21 through rmii to perform data transmission and reception, performs correlation control on the network PHY chip 21 through spi, and reads the correlation 1588 synchronization timestamp. Because the network PHY chip 21 supports 1588 synchronization, the time marking of the 1588 synchronization message is completed at the forefront of the whole network, and the synchronization error is reduced to the greatest extent. The clock output pin and the pulse output pin of the network PHY chip 21 are connected to the working clock input pin (Clk) and the reset pin (Sync) of the AD chip 23, respectively, to control the sampling clock of the AD and to start the AD sampling.

In one embodiment, there are a plurality of boards 20, and each of the network PHY chips 21 of the plurality of boards 20 is connected to the network PHY layer interface 111 through an ethernet. The plurality of boards 20 are connected to the network physical layer interface 111 through ethernet, that is, the bus architecture is enabled to collect multi-channel data.

In one embodiment, the bus architecture is a bus architecture of a multi-board card box type acquisition instrument, and the bus architecture is composed of two parts, namely an acquisition board card (board card 20) and a backplane 10, all the acquisition board cards in the chassis 30 are connected with the backplane 10 through a standard ethernet, and the backplane 10 completes data cascade and assists the acquisition board cards to complete data acquisition synchronization. And the acquisition board cards realize the synchronization of the acquired data through 1588.

The backplane 10 is composed of one or more switching PHY chips 11 supporting 1588, and the switching PHY chips 11 can finally converge data to a network physical layer interface 111 through a switching function to output the data to the outside. Because the exchange PHY chip 11 supports the 1588 protocol, the time of 1588 message data residing in the exchange chip in exchange transmission can be calculated, and meanwhile, the acquisition board card is informed, so that the 1588 synchronous time synchronization precision is improved. The switching PHY chips 11 of the backplane 10 may be connected in series in any number in an MAC interconnection manner, so as to increase the number of the backplane 10 connected to the acquisition boards.

And each acquisition board communicates with the outside through the Ethernet. The Ethernet part of the acquisition board card consists of a network PHY chip 21 supporting 1588, and the network PHY chip 21 can automatically capture a timestamp generated when the 1588 message passes through for 1588 synchronous calculation. The data communication between the acquisition board card and the backplane 10 is completed through only one ethernet, and the ethernet simultaneously realizes the uploading of the acquired data and the interaction of 1588 synchronous messages. Through 1588 pairs, the internal time and the internal clock error of the network PHY chip 21 of different sampling board cards in the case 30 can be about 10ns, so that the requirement of phase consistency between channels of single independent acquisition equipment is met. And the acquisition board card in the chassis 30 is used independently without the help of any accessories except the power supply after being separated from the chassis 30.

An embodiment of the utility model provides a bus architecture, include: a backplane 10, the backplane 10 comprising a switching PHY chip 11 supporting 1588 protocol; the integrated circuit board 20 comprises a network PHY chip 21 supporting a 1588 protocol; the network PHY chip 21 is connected to the switching PHY chip 11 via ethernet.

In one embodiment, the bus architecture is composed of a backplane 10 and a board 20, and the board 20 transmits the acquired data to the upper computer through the backplane 10. Because the network PHY chip 21 of the board card 20 is connected to the network physical layer interface 111 of the backplane 10 through the ethernet, that is, the backplane 10 and the board card 20 are directly connected through the network, due to the characteristics of the network, the whole data transmission on the backplane 10 has strong stability and anti-interference performance, and the connection with the board card 20 is simple, so that the manufacturing cost is reduced, and the structure is simple.

In one embodiment, the backplane 10 and the board 20 are configured in accordance with the backplane 10 and the board 20 of the bus architecture described above.

The utility model also provides a case type collector, which comprises a body, wherein the body comprises the bus framework and the case 30; the bus structure is disposed in the chassis 30.

In one embodiment, the board 20 is removably disposed in the housing 30 so that the board 20 can be connected to the host computer via the ethernet network after being detached from the housing 30. Since the connection between the board 20 and the outside is network connection, the board 20 can be used independently after being separated from the chassis 30, that is, directly connected to an upper computer, so as to implement data transmission.

In one embodiment, the body is multiple, and the multiple bodies are connected through the Ethernet.

In one embodiment, the chassis-type collection instrument may be composed of one bus architecture and the chassis 30, or may be composed of a plurality of bus architectures and the chassis 30 connected in series, that is, the two bus architectures are interconnected through the reserved interface 12.

In one embodiment, the bus architecture of the chassis type acquisition instrument is composed of a backplane 10 and board cards 20, the backplane 10 is composed of 1 to n network PHY chips 21 according to the number of the board cards 20, and the network PHY chips 21 are interconnected through MAC. The board card 20 is connected to the backplane 10 via 4 or 8 network signals. Besides being connected with the acquisition board through a network, the back board 10 reserves two network physical layer interfaces 111 for the cascade synchronization between the bodies. Through the 1588 synchronization protocol, the internal clocks and frequencies of the network PHY chips 21 on the different boards 20 are calibrated with reference to the internal time and frequency of the network PHY chip 21 on the master board. Based on the calibrated frequency, each network PHY chip 21 will generate a clock with a suitable frequency as a working master clock of the AD, and based on the calibrated time, each network PHY chip 21 will generate an edge pulse at the same fixed time as a synchronous acquisition signal of the AD, so that all board cards 20 will start to acquire simultaneously, and the sampling clocks are consistent, thereby achieving the accurate synchronization effect of all acquisition channels. The switching PHY chip 11 on the backplane 10 also supports 1588 functions, and when data of different boards 20 are cascaded, the residence time of the 1588 synchronization packet on the switching chip due to data switching can be calculated, that is, the residence time of the 1588 packet in fig. 2 from the PHY1 to the PHY2, or vice versa, can be calculated. The path delay can be accurately calculated by the time board card 20, so that the time difference between the acquisition board cards is accurately calculated, and then calibration is performed, thereby solving the problem of equal path delay requirements in the 1588 synchronization process.

The utility model discloses a bus architecture, backplate 10 adopt the exchange PHY chip 11 that supports 1588, and integrated circuit board 20 adopts the network PHY chip 21 that supports 1588. The switching PHY chip 11 on the backplane 10 solves the problem of data cascading between boards. The switching PHY chip 11 itself supports the 1588 protocol, and can help the board 20 obtain an accurate path delay time in 1588 message transmission. The network PHY chip 21 on the board card 20 also supports the 1588 protocol, the 1588 message timestamp is obtained at the forefront end of the network, the synchronization precision of about 10ns is finally realized among the acquisition board cards, and the requirement of phase consistency among channels of high-precision independent instruments is met.

Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. The present invention is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and exemplary embodiments be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

It will be understood that the invention is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A bus architecture, comprising:

a backplane (10), the backplane (10) comprising a switch PHY chip (11) supporting 1588 protocol, the switch PHY chip (11) comprising a plurality of network physical layer interfaces (111), two of the plurality of network physical layer interfaces (111) being reserved interfaces (12);

the board (20), the board (20) includes a network PHY chip (21) supporting 1588 protocol, and the network PHY chip (21) is connected with the network physical layer interface (111) except the reserved interface (12) through Ethernet.

2. The bus architecture according to claim 1, wherein said switching PHY chips (11) are plural, and two of said switching PHY chips (11) are connected to each other through a MAC layer;

wherein two of said switching PHY chips (11) of said plurality of switching PHY chips (11) each comprise one of said reserved interfaces (12).

3. The bus architecture according to claim 1, characterized in that said switching PHY chip (11) further comprises:

a plurality of MAC layer interfaces (112), wherein the MAC layer interfaces (112) are provided;

the switching engine (113) supports 1588 protocol, and a plurality of network physical layer interfaces (111) are connected with the switching engine (113) through the MAC layer interface (112).

4. The bus architecture of claim 1, wherein the board (20) further comprises:

the central processing unit (22), the said central processing unit (22) is connected with said network PHY chip (21);

an AD chip (23), the network PHY chip (21) being connected to the AD chip (23).

5. The bus architecture according to claim 4, characterized in that the network PHY chip (21) comprises a clock output pin and a pulse output pin, and the AD chip (23) comprises a clock input pin and a reset pin, the clock output pin and the pulse output pin being connected to the clock input pin and the reset pin, respectively.

6. The bus architecture according to any of claims 1 to 5, characterized in that the plurality of boards (20) is provided, and each of the network PHY chips (21) of the plurality of boards (20) is connected to the network physical layer interface (111) via an Ethernet.

7. A bus architecture, comprising:

a backplane (10), the backplane (10) comprising a switching PHY chip (11) that supports 1588 protocol;

the device comprises a board card (20), wherein the board card (20) comprises a network PHY chip (21) supporting 1588 protocol;

wherein the network PHY chip (21) is connected to the switch PHY chip (11) via an Ethernet network.

8. A chassis-type collector comprising a body, characterized in that said body comprises a bus architecture according to any one of claims 1 to 7 and a chassis (30);

wherein the bus architecture is disposed within the chassis (30).

9. The chassis-type collection instrument of claim 8, wherein the board (20) is detachably disposed in the chassis (30) so as to be connectable to an upper computer via an ethernet network after the board (20) is detached from the chassis (30).

10. The chassis-type collection instrument of claim 8, wherein the plurality of bodies are connected by ethernet.