CN111865467A - Clock synchronization system and method between distributed chassis board cards for time delay test - Google Patents
Clock synchronization system and method between distributed chassis board cards for time delay test Download PDFInfo
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- CN111865467A CN111865467A CN202010698413.7A CN202010698413A CN111865467A CN 111865467 A CN111865467 A CN 111865467A CN 202010698413 A CN202010698413 A CN 202010698413A CN 111865467 A CN111865467 A CN 111865467A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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Abstract
The invention discloses a clock synchronization system and a clock synchronization method among distributed chassis board cards for time delay test, wherein the clock synchronization system comprises n board cards, a chassis exchange network and a SEDERS; the n cards are in communication connection with the chassis exchange network through the SEDERS; and each board card is in communication connection with each other through the internal network of the distributed case. The distributed case structure supports a clock calibration function, provides a high-precision synchronous clock for each board card in the distributed case, and provides precision guarantee for the time delay test of network equipment. The clock synchronization method provided by the invention eliminates the influence of network instability, network card buffer effect on information packets, operating system process scheduling and the like on clock synchronization precision when a software clock synchronization method is adopted, and provides a high-precision clock with a level of ten microseconds for network equipment delay test.
Description
Technical Field
The invention belongs to the technical field of data network communication, and particularly relates to a system and a method for clock synchronization among distributed chassis board cards for time delay testing.
Background
The calculation time interval of subtracting the receiving time from the sending time during the time delay test of the network equipment is small in the magnitude of the time delay units of the store-and-forward or direct-connection exchange, and the requirement on the clock of the test equipment is high during the actual test, so that the sending end and the receiving end are required to have accurate clock synchronization. For the chassis of the single board card, the same clock source can be used for sending and receiving, and clock synchronization is not needed. In a distributed chassis, the transmitter and receiver may be located on different boards, requiring that the different boards must be precisely clocked.
The PTP (Precision Time Protocol) Protocol is a Precision clock synchronization Protocol defined in IEEE-1588, and the PTP Protocol is designed mainly for environments where a subnet is good and internal components are relatively stable, and a system is relatively localized and networked. The PTP protocol is widely applied to a distributed system due to the advantages of simple implementation, small occupied network and computing resources and the like.
The PTP protocol may be implemented by hardware or software. When implemented in hardware, accuracy on the order of nanoseconds can be achieved, and when implemented in software, accuracy on the order of milliseconds can generally be achieved. When implementing sub-millisecond accuracy in a network using software, there are a number of factors that affect the unreliable time synchronization. The factors including the instability of the network, the caching effect of the network card on the information packet and the influence of the process scheduling of the operating system are usually unpredictable and uncontrollable, and the final failure of clock synchronization is caused, so that the tested delay error is large.
Disclosure of Invention
The invention aims to solve the problem of the deficiency of the existing clock synchronization method, and provides a system and a method for synchronizing clocks among distributed chassis board cards for time delay testing.
The technical scheme of the invention is as follows: a clock synchronization system among distributed chassis board cards for time delay test comprises n board cards, a chassis exchange network and a SEDERS;
the n cards are in communication connection with the chassis exchange network through the SEDERS; and each board card is in communication connection with each other through the internal network of the distributed case.
The invention has the beneficial effects that: the distributed case structure comprises a plurality of board cards, wherein the board cards are interconnected through a case internal switching network, and the board cards are connected with the case switching network through SEDERS. The network card chip comprises a network card clock with the precision greater than microsecond level, and the clock supports the clock calibration function, provides a high-precision synchronous clock for each board card in the distributed chassis, and provides precision guarantee for the time delay test of network equipment.
Furthermore, each board card has the same internal structure and comprises a CPU and a network card chip; a CPU clock is arranged in the CPU; the network card chip supports an IEEE1588 protocol and is internally provided with a network card clock;
the CPU is in communication connection with the network card chip; the network card chip is in communication connection with the chassis exchange network through the SEDERS.
The beneficial effects of the further scheme are as follows: in the invention, a clock synchronization program can be operated on the CPU of each board card in the distributed chassis, and the master board card and the slave board card are used for clock synchronization.
Based on the system, the invention also provides a method for synchronizing the clocks among the distributed chassis board cards for the time delay test, which comprises the following steps:
s1: negotiating a clock synchronization program of each board card, and determining a master board card and a slave board card;
s2: calibrating a main CPU clock and a main network card clock;
s3: synchronizing the calibrated main CPU clock and the main network card clock;
s4: calibrating a master network card clock and a slave network card clock;
s5: synchronizing the calibrated master network card clock and the slave network card clock;
s6: and synchronizing the clock of the main CPU and the clock of the slave CPU to finish the clock synchronization between the distributed chassis boards.
The invention has the beneficial effects that: the clock synchronization method provided by the invention eliminates the influence of network instability, network card buffer effect on information packets, operating system process scheduling and the like on clock synchronization precision when a software clock synchronization method is adopted, and provides a high-precision clock with a level of ten microseconds for network equipment delay test.
Further, in step S1, the master board card includes a master CPU clock and a master network card clock, and the slave board card includes a slave CPU clock and a slave network card clock.
Further, step S2 includes the following sub-steps:
s21: clearing a clock counter of the main network card to complete initialization of the clock of the main network card;
s22: reading a first time stamp T1 of a main CPU clock and a first time stamp T2 of a main network card clock after initialization through an assembly instruction;
s23: after the interval of 10 mus, reading the second time stamp T3 of the main CPU clock and the second time stamp T4 of the main network card clock again through an assembling instruction;
s23: calculating an offset value T of the main CPU clock and the main network card clock according to the fact that the first timestamp of the main CPU clock is T1, the first timestamp of the main network card clock is T2, the second timestamp of the main CPU clock is T3 and the second timestamp of the main network card clock is T4, and the calculation formula is as follows:
T＝[(T3－T1)－(T4－T2)]/(T3-T1)；
s24: and writing the deviation value T of the main CPU clock and the main network card clock into a calibration register to finish the calibration of the main CPU clock and the main network card clock.
In step S3, the method for synchronizing the calibrated master CPU clock and the master network card clock includes: and reading the time stamp of the main CPU, and writing the time stamp into a clock counter of the main network card to complete the synchronization of the clock of the main CPU and the clock of the main network card.
The beneficial effects of the further scheme are as follows: in the invention, the software clock synchronization program on the CPU is used for reading the time stamp of the main CPU, and the clock of the main CPU and the clock of the main network card can be directly accessed for the clock synchronization program, thereby being convenient for completing the synchronization.
Further, step S4 includes the following sub-steps:
s41: sending a PTP SYNC message to a slave board card by using the master board card, and recording a first sending timestamp T5;
s42: receiving a PTP SYNC message by using a slave board card, and recording a first receiving time stamp T6;
s43: sending a PTP FOLLOW _ UP message carrying a first sending timestamp T5 to a slave board card by using a master board card;
s44: receiving a PTP FOLLOW _ UP message by using a slave board card, and storing a first transmission time stamp T5 of the PTP FOLLOW _ UP message;
s45: sending a PTP SYNC message to the slave board card again by using the master board card, and recording a retransmission timestamp T7;
s46: the slave board card is used for receiving the PTP SYNC message again, and a re-receiving time stamp T8 is recorded;
s47: sending a PTP FOLLOW _ UP message carrying a resending time stamp T7 to the slave board card again by using the master board card;
s48: the slave board card is used for receiving the PTP FOLLOW _ UP message again, and a re-receiving time stamp T8 of the PTP FOLLOW _ UP message is stored;
S49: calculating a first deviation value T' of the master-slave network card clock according to the first sending time stamp T5, the first receiving time stamp T6, the second sending time stamp T7 and the second receiving time stamp T8, wherein the calculation formula is as follows:
T′＝[(T7－T5)－(T8－T6)]/(T7-T5)；
s410: and writing the first deviation value T' of the master network card clock and the slave network card clock into a slave network card calibration register to finish the calibration of the master network card clock and the slave network card clock.
The beneficial effects of the further scheme are as follows: in the invention, the slave card obtains four time stamps of T1, T2, T3 and T4, (T3-T1) - (T4-T2) which are deviation values of the slave network card clock and the master network card clock in (T3-T1) time, so that the master network card clock and the slave network card clock can be calibrated conveniently. When the master board card and the slave board card are designed to carry out message interaction, the receiving and sending timestamps of the messages are recorded in the network card chip, so that the buffer effect of the network card on information packets and the influence of the process scheduling of an operating system are eliminated, and the clock synchronization precision is greatly improved.
Further, step S5 includes the following sub-steps:
s51: sending a PTP SYNC message to the slave board card by using the master board card, and recording a second sending time stamp T9;
s52: receiving a PTP SYNC message by using the slave board card, and recording a second receiving time stamp T10;
S53: sending a PTP FOLLOW _ UP message carrying a second sending timestamp T9 to the slave board card by using the master board card;
s54: receiving the PTP FOLLOW _ UP message by using the slave board card, and storing a second sending time stamp T9 of the PTP FOLLOW _ UP message;
s55: sending a PTP DELAY message by using the slave board card, and recording a third sending time stamp T11;
s56: receiving the PTP DELAY message by using the main board card, and recording a third receiving time stamp T12;
s57: sending a PTP DELAY _ REQ message carrying a third receiving timestamp T12 to the slave board card by using the master board card;
s58: receiving the PTP DELAY _ REQ message by using the slave board card, and storing a third receiving time stamp T12 in the PTP DELAY _ REQ message;
s59: calculating a second offset value T' ″ of the master and slave network card clocks according to the second sending timestamp T9, the second receiving timestamp T10, the third sending timestamp T11, and the third receiving timestamp T12 by:
T＇＇＝[(T10－T9)－(T11－T12)]/2；
s510: the second offset value T' ″ of the master-slave network card clock is written in the slave network card clock, completing the synchronization of the master network card clock and the slave network card clock.
Further, step S6 includes the following sub-steps:
s61: simultaneously reading a slave CPU clock stamp T13 and a slave network card clock stamp T14 by using a slave card;
s62: calculating the deviation value T' ″ of the master CPU clock and the slave CPU clock according to the CPU clock stamp T13 and the slave network card clock stamp T14 to complete the synchronization of the master CPU clock and the slave CPU clock, wherein the calculation formula is as follows:
T″＇＝T13－T14。
Drawings
FIG. 1 is a block diagram of a clock synchronization system between boards of a distributed chassis;
FIG. 2 is a flow chart of a method for clock synchronization between boards of a distributed chassis;
FIG. 3 is a flow chart of master-slave clock calibration;
FIG. 4 is a flow chart of master-slave clock synchronization;
in the figure, 1, a board card; 2. a chassis switching network; 3. SEDERS.
Detailed Description
The embodiments of the present invention will be further described with reference to the accompanying drawings.
As shown in fig. 1, the present invention provides an n-block board 1, a chassis switching network 2, and a SEDERS3 of a clock synchronization system among distributed chassis boards for delay testing;
the n board cards 1 are in communication connection with the chassis exchange network 2 through SEDERS 3; and each board card 1 is in communication connection through the internal network of the distributed case.
In the embodiment of the present invention, as shown in fig. 1, each board card 1 has the same internal structure, and includes a CPU and a network card chip; a CPU clock is arranged in the CPU; the network card chip supports an IEEE1588 protocol and is internally provided with a network card clock;
the CPU is in communication connection with the network card chip; the network card chip is in communication connection with the chassis switching network 2 through the SEDERS 3. A clock synchronization program can run on a CPU of each board card in the distributed case, and the master board card and the slave board card are used for clock synchronization.
The CPU is a general-purpose processor, can adopt an Intel Zhiqiang series processor or a Feiteng FT1500a processor, comprises a CPU clock with the precision of more than microsecond level on the CPU, can adopt a 2Ghz Zhiqiang processor, and has the precision of the CPU clock of 0.5 nanosecond level. The network card chip is a gigabit Ethernet network card chip supporting IEEE1588 and SEDERS interfaces, the network card chip comprises a network card clock with the precision greater than microsecond level, and the network card chip can adopt Intel I350 or Intel 82580 and the like, and the clock supports the clock calibration function. A clock synchronization program runs on a CPU of each board card in a case, firstly, the clock synchronization program on each board card negotiates, wherein one board card negotiates as a master board card, and the other board cards negotiate as slave board cards. And the master board card is respectively in clock synchronization with all the slave board cards, and after the synchronization is finished, all the board card clocks are synchronous clocks. And all the board cards use the CPU clocks on the board cards as board card clocks.
Based on the above system, the present invention further provides a method for synchronizing clocks between distributed chassis boards for delay testing, as shown in fig. 2, including the following steps:
s1: negotiating a clock synchronization program of each board card, and determining a master board card and a slave board card;
S2: calibrating a main CPU clock and a main network card clock;
s3: synchronizing the calibrated main CPU clock and the main network card clock;
s4: calibrating a master network card clock and a slave network card clock;
s5: synchronizing the calibrated master network card clock and the slave network card clock;
s6: and synchronizing the clock of the main CPU and the clock of the slave CPU to finish the clock synchronization between the distributed chassis boards.
In the embodiment of the present invention, as shown in fig. 3, in step S1, a master CPU clock and a master network card clock are disposed in the master card, and a slave CPU clock and a slave network card clock are disposed in the slave card.
In the embodiment of the present invention, as shown in fig. 3, step S2 includes the following sub-steps:
s21: clearing a clock counter of the main network card to complete initialization of the clock of the main network card;
s22: reading a first time stamp T1 of a main CPU clock and a first time stamp T2 of a main network card clock after initialization through an assembly instruction;
s23: after the interval of 10 mus, reading the second time stamp T3 of the main CPU clock and the second time stamp T4 of the main network card clock again through an assembling instruction;
s23: calculating an offset value T of the main CPU clock and the main network card clock according to the fact that the first timestamp of the main CPU clock is T1, the first timestamp of the main network card clock is T2, the second timestamp of the main CPU clock is T3 and the second timestamp of the main network card clock is T4, and the calculation formula is as follows:
T＝[(T3－T1)－(T4－T2)]/(T3-T1)；
S24: and writing the deviation value T of the main CPU clock and the main network card clock into a calibration register to finish the calibration of the main CPU clock and the main network card clock.
In the embodiment of the present invention, as shown in fig. 4, in step S3, the method for synchronizing the calibrated master CPU clock and the master network card clock includes: and reading the time stamp of the main CPU, and writing the time stamp into a clock counter of the main network card to complete the synchronization of the clock of the main CPU and the clock of the main network card. In the invention, the software clock synchronization program on the CPU is used for reading the time stamp of the main CPU, and the clock of the main CPU and the clock of the main network card can be directly accessed for the clock synchronization program, thereby being convenient for completing the synchronization.
In the embodiment of the present invention, as shown in fig. 2, step S4 includes the following sub-steps:
s41: sending a PTP SYNC message to a slave board card by using the master board card, and recording a first sending timestamp T5;
s42: receiving a PTP SYNC message by using a slave board card, and recording a first receiving time stamp T6;
s43: sending a PTP FOLLOW _ UP message carrying a first sending timestamp T5 to a slave board card by using a master board card;
s44: receiving a PTP FOLLOW _ UP message by using a slave board card, and storing a first transmission time stamp T5 of the PTP FOLLOW _ UP message;
s45: sending a PTP SYNC message to the slave board card again by using the master board card, and recording a retransmission timestamp T7;
S46: the slave board card is used for receiving the PTP SYNC message again, and a re-receiving time stamp T8 is recorded;
s47: sending a PTP FOLLOW _ UP message carrying a resending time stamp T7 to the slave board card again by using the master board card;
s48: the slave board card is used for receiving the PTP FOLLOW _ UP message again, and a re-receiving time stamp T8 of the PTP FOLLOW _ UP message is stored;
s49: calculating a first deviation value T' of the master-slave network card clock according to the first sending time stamp T5, the first receiving time stamp T6, the second sending time stamp T7 and the second receiving time stamp T8, wherein the calculation formula is as follows:
T′＝[(T7－T5)－(T8－T6)]/(T7-T5)；
s410: and writing the first deviation value T' of the master network card clock and the slave network card clock into a slave network card calibration register to finish the calibration of the master network card clock and the slave network card clock.
In the invention, the slave card obtains four time stamps of T1, T2, T3 and T4, (T3-T1) - (T4-T2) which are deviation values of the slave network card clock and the master network card clock in (T3-T1) time, so that the master network card clock and the slave network card clock can be calibrated conveniently. When the master board card and the slave board card are designed to carry out message interaction, the receiving and sending timestamps of the messages are recorded in the network card chip, so that the buffer effect of the network card on information packets and the influence of the process scheduling of an operating system are eliminated, and the clock synchronization precision is greatly improved.
In the embodiment of the present invention, as shown in fig. 2, step S5 includes the following sub-steps:
s51: sending a PTP SYNC message to the slave board card by using the master board card, and recording a second sending time stamp T9;
s52: receiving a PTP SYNC message by using the slave board card, and recording a second receiving time stamp T10;
s53: sending a PTP FOLLOW _ UP message carrying a second sending timestamp T9 to the slave board card by using the master board card;
s54: receiving the PTP FOLLOW _ UP message by using the slave board card, and storing a second sending time stamp T9 of the PTP FOLLOW _ UP message;
s55: sending a PTP DELAY message by using the slave board card, and recording a third sending time stamp T11;
s56: receiving the PTP DELAY message by using the main board card, and recording a third receiving time stamp T12;
s57: sending a PTP DELAY _ REQ message carrying a third receiving timestamp T12 to the slave board card by using the master board card;
s58: receiving the PTP DELAY _ REQ message by using the slave board card, and storing a third receiving time stamp T12 in the PTP DELAY _ REQ message;
s59: calculating a second offset value T' ″ of the master and slave network card clocks according to the second sending timestamp T9, the second receiving timestamp T10, the third sending timestamp T11, and the third receiving timestamp T12 by:
T＇＇＝[(T10－T9)－(T11－T12)]/2；
s510: the second offset value T' ″ of the master-slave network card clock is written in the slave network card clock, completing the synchronization of the master network card clock and the slave network card clock.
In the embodiment of the present invention, as shown in fig. 2, step S6 includes the following sub-steps:
s61: simultaneously reading a slave CPU clock stamp T13 and a slave network card clock stamp T14 by using a slave card;
s62: calculating the deviation value T' ″ of the master CPU clock and the slave CPU clock according to the CPU clock stamp T13 and the slave network card clock stamp T14 to complete the synchronization of the master CPU clock and the slave CPU clock, wherein the calculation formula is as follows:
T″＇＝T13－T14。
the working principle and the process of the invention are as follows: a clock synchronization program runs on a CPU of each board card in the distributed case, firstly, the clock synchronization program on each board card negotiates, wherein one board card negotiates as a master board card, and the other board cards negotiate as slave board cards. And the master board card is respectively in clock synchronization with all the slave board cards, and after the synchronization is finished, all the board card clocks are synchronous clocks. And all the board cards use the CPU clocks on the board cards as board card clocks. The clock synchronization process of the master board card and the slave board card mainly comprises the following steps: firstly, calibrating a main CPU clock and a main network card clock, and synchronizing the main CPU clock and the main network card clock; and finally, the slave board completes the synchronization of the master CPU clock and the slave CPU clock by calculating the offset of the slave CPU clock and the slave network card clock. Because there may be some deviation between the CPU clock frequency and the nominal frequency, clock synchronization needs to be repeated at certain time intervals to eliminate the deviation.
The invention has the beneficial effects that: the distributed case structure comprises a plurality of board cards, wherein the board cards are interconnected through a case internal switching network, and the board cards are connected with the case switching network through SEDERS. The network card chip comprises a network card clock with the precision greater than microsecond level, and the clock supports the clock calibration function, provides a high-precision synchronous clock for each board card in the distributed chassis, and provides precision guarantee for the time delay test of network equipment. The clock synchronization method provided by the invention eliminates the influence of network instability, network card buffer effect on information packets, operating system process scheduling and the like on clock synchronization precision when a software clock synchronization method is adopted, and provides a high-precision clock with a level of ten microseconds for network equipment delay test.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (9)
1. A clock synchronization system among distributed chassis board cards for time delay test is characterized by comprising n board cards (1), a chassis exchange network (2) and a SEDERS (3);
the n board cards (1) are in communication connection with the chassis exchange network (2) through the SEDERS (3); and each board card (1) is in communication connection with each other through the internal network of the distributed case.
2. The system for synchronizing the clocks among the distributed chassis board cards for the delay test according to claim 1, wherein each board card (1) has the same internal structure and comprises a CPU and a network card chip; a CPU clock is arranged in the CPU; the network card chip supports an IEEE1588 protocol and is internally provided with a network card clock;
the CPU is in communication connection with the network card chip; the network card chip is in communication connection with the chassis exchange network (2) through the SEDERS (3).
3. A clock synchronization method between distributed chassis board cards for time delay test is characterized by comprising the following steps:
s1: negotiating a clock synchronization program of each board card, and determining a master board card and a slave board card;
s2: calibrating a main CPU clock and a main network card clock;
s3: synchronizing the calibrated main CPU clock and the main network card clock;
s4: calibrating a master network card clock and a slave network card clock;
S5: synchronizing the calibrated master network card clock and the slave network card clock;
s6: and synchronizing the clock of the main CPU and the clock of the slave CPU to finish the clock synchronization between the distributed chassis boards.
4. The method according to claim 3, wherein in step S1, the master board card has a master CPU clock and a master network card clock, and the slave board card has a slave CPU clock and a slave network card clock.
5. The method for clock synchronization between distributed chassis board cards for latency testing according to claim 3, wherein the step S2 includes the following sub-steps:
s21: clearing a clock counter of the main network card to complete initialization of the clock of the main network card;
s22: reading a first time stamp T1 of a main CPU clock and a first time stamp T2 of a main network card clock after initialization through an assembly instruction;
s23: after the interval of 10 mus, reading the second time stamp T3 of the main CPU clock and the second time stamp T4 of the main network card clock again through an assembling instruction;
s23: calculating an offset value T of the main CPU clock and the main network card clock according to the fact that the first timestamp of the main CPU clock is T1, the first timestamp of the main network card clock is T2, the second timestamp of the main CPU clock is T3 and the second timestamp of the main network card clock is T4, and the calculation formula is as follows:
T＝[(T3－T1)－(T4－T2)]/(T3-T1)；
S24: and writing the deviation value T of the main CPU clock and the main network card clock into a calibration register to finish the calibration of the main CPU clock and the main network card clock.
6. The method for synchronizing clocks between boards in a distributed chassis for delay testing according to claim 3, wherein in step S3, the method for synchronizing the calibrated clock of the main CPU and the clock of the main board is as follows: and reading the time stamp of the main CPU, and writing the time stamp into a clock counter of the main network card to complete the synchronization of the clock of the main CPU and the clock of the main network card.
7. The method for clock synchronization between distributed chassis board cards for latency testing according to claim 3, wherein the step S4 includes the following sub-steps:
s41: sending a PTP SYNC message to a slave board card by using the master board card, and recording a first sending timestamp T5;
s42: receiving a PTP SYNC message by using a slave board card, and recording a first receiving time stamp T6;
s43: sending a PTP FOLLOW _ UP message carrying a first sending timestamp T5 to a slave board card by using a master board card;
s44: receiving a PTP FOLLOW _ UP message by using a slave board card, and storing a first transmission time stamp T5 of the PTP FOLLOW _ UP message;
s45: sending a PTP SYNC message to the slave board card again by using the master board card, and recording a retransmission timestamp T7;
S46: the slave board card is used for receiving the PTP SYNC message again, and a re-receiving time stamp T8 is recorded;
s47: sending a PTP FOLLOW _ UP message carrying a resending time stamp T7 to the slave board card again by using the master board card;
s48: the slave board card is used for receiving the PTP FOLLOW _ UP message again, and a re-receiving time stamp T8 of the PTP FOLLOW _ UP message is stored;
s49: calculating a first deviation value T' of the master-slave network card clock according to the first sending time stamp T5, the first receiving time stamp T6, the second sending time stamp T7 and the second receiving time stamp T8, wherein the calculation formula is as follows:
T′＝[(T7－T5)－(T8－T6)]/(T7-T5)；
s410: and writing the first deviation value T' of the master network card clock and the slave network card clock into a slave network card calibration register to finish the calibration of the master network card clock and the slave network card clock.
8. The method for clock synchronization between distributed chassis board cards for latency testing according to claim 3, wherein the step S5 includes the following sub-steps:
s51: sending a PTP SYNC message to the slave board card by using the master board card, and recording a second sending time stamp T9;
s52: receiving a PTP SYNC message by using the slave board card, and recording a second receiving time stamp T10;
s53: sending a PTP FOLLOW _ UP message carrying a second sending timestamp T9 to the slave board card by using the master board card;
S54: receiving the PTP FOLLOW _ UP message by using the slave board card, and storing a second sending time stamp T9 of the PTP FOLLOW _ UP message;
s55: sending a PTP DELAY message by using the slave board card, and recording a third sending time stamp T11;
s56: receiving the PTP DELAY message by using the main board card, and recording a third receiving time stamp T12;
s57: sending a PTP DELAY _ REQ message carrying a third receiving timestamp T12 to the slave board card by using the master board card;
s58: receiving the PTP DELAY _ REQ message by using the slave board card, and storing a third receiving time stamp T12 in the PTP DELAY _ REQ message;
s59: calculating a second offset value T' of the master-slave network card clock according to the second sending time stamp T9, the second receiving time stamp T10, the third sending time stamp T11 and the third receiving time stamp T12, wherein the calculation formula is as follows:
T″＝[(T10－T9)－(T11－T12)]/2；
s510: and writing the second offset value T' of the master network card clock and the slave network card clock into the slave network card clock to complete the synchronization of the master network card clock and the slave network card clock.
9. The method for clock synchronization between distributed chassis board cards for latency testing according to claim 3, wherein the step S6 includes the following sub-steps:
s61: simultaneously reading a slave CPU clock stamp T13 and a slave network card clock stamp T14 by using a slave card;
s62: calculating the deviation value T' of the master-slave CPU clock according to the CPU clock stamp T13 and the slave network card clock stamp T14, and completing the synchronization of the master CPU clock and the slave CPU clock, wherein the calculation formula is as follows:
T″＇＝T13－T14。
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