CN114745061A - Integrated receiving system of broadband large dynamic optical network signal - Google Patents

Abstract

The application relates to an integrated receiving system of broadband large dynamic optical network signals. The system comprises: the device comprises a coherent light receiving module, a high-speed ADC module, a clock module, an FPGA module, an optical port module and a power circuit module; the coherent light receiving module is used for demodulating the received light signal; the high-speed ADC module is used for carrying out analog-to-digital conversion on the demodulated analog electric signal; the FPGA module comprises a Virtex Ultrascale + module and is used for controlling the high-speed ADC module to realize analog-to-digital conversion, and acquiring and caching digital signals output by the high-speed ADC module; the clock module is used for providing a sampling clock and a starting signal of the high-speed ADC module and a reference clock of the FPGA module, and the optical port module is used for outputting cached sampling data. The high-speed ADC module and the FPGA module in the system can select the universal ADC module and the universal FPGA module according to actual requirements, the system is high in compatibility, and the development cost of the system can be reduced.

Description

Integrated receiving system of broadband large dynamic optical network signal

Technical Field

The application relates to the technical field of broadband signal sampling, in particular to an integrated receiving system of broadband large dynamic optical network signals.

Background

The optical wave communication is used as one of the bases of the next generation broadband communication network due to the characteristics of extremely large bandwidth resources, good networking capability, strong anti-interference capability, low cost and the like. Optical network technology is an Optical Transport Network (OTN) formed by using optical cross-connect (OXC) and optical add-drop multiplexing (OADM) technologies for point-to-point wavelength division multiplexing systems. However, with the development of communication systems, the signal specifications of the optical network wavelength division multiplexing system carrier are more and more, including different symbol rates, different modulation formats, and the like, which bring great difficulties to the construction of next-generation reconfigurable optical networks. In the face of the challenge of the modern complex communication environment to the optical network design, the design of the broadband large dynamic optical network signal integrated receiving architecture is imperative.

The existing coherent light receiving module is a customized DSP module, and can be matched with a product of a specified manufacturer only, so that the compatibility of the system is poor, and the system cannot be adapted to different rates and various modulation formats.

Disclosure of Invention

In view of the above, it is necessary to provide an integrated receiving system for broadband large dynamic optical network signals. The system can adapt to multi-rate, multi-modulation format optical network signals.

An integrated receiving system for broadband large dynamic optical network signals, the integrated receiving system comprising: the device comprises a coherent light receiving module, a high-speed ADC module, a clock module, an FPGA module, an optical port module and a power circuit module.

The coherent light receiving module is used for receiving an input optical signal and demodulating the optical signal.

And the high-speed ADC module is used for carrying out analog-to-digital conversion on the analog electric signal obtained after demodulation.

The FPGA module comprises a Virtex Ultrascale + module and is used for controlling the high-speed ADC module to realize analog-to-digital conversion, acquiring digital signals output by the high-speed ADC module and caching the acquired sampling data.

The clock module is used for providing a sampling clock and a starting signal of the high-speed ADC module and a reference clock of the Virtex Ultrascale + module high-speed transceiver.

And the optical port module is used for outputting the sampling data cached in the FPGA module.

The power circuit module is used for providing power for the coherent light receiving module, the high-speed ADC module, the clock module, the FPGA module and the optical port module, and performing power management and monitoring.

Further, the coherent light receiving module comprises an integrated coherent receiver and an integrated tunable laser component.

The integrated adjustable laser component is connected with the integrated coherent receiver; the integrated coherent receiver is coupled to the high-speed ADC.

Further, the high-speed ADC module comprises a high-speed analog-to-digital conversion module with a multi-chip sampling rate as high as 56 GSPS; the high-speed analog-to-digital conversion module is connected with the coherent light receiving module and the FPGA module.

And the high-speed analog-to-digital conversion modules synchronously sample under the action of a starting signal provided by the sampling clock module.

Further, the high-speed analog-to-digital conversion module is an AAD08S056G module; the number of the high-speed analog-to-digital conversion modules is 4.

The output end of the AAD08S056G module is connected with the high-speed transceiver of the Virtex Ultrascale + module through a CML interface,

the SPI signal and the SYNC signal of the AAD08S056G module are connected to the Virtex Ultrascale + module, the SPI signal is used for configuring the AAD08S056G module, and the SYNC signal is used for synchronous sampling among the four AAD08S056G modules.

The sampling clock of the four AAD08S056G, the reference clock of the high-speed transceiver of the Virtex Ultrascale + module and the data processing clock are the same source clock, and are provided by the clock module.

Further, the clock module includes: the device comprises a phase-locked medium oscillator, a multi-path power divider and a clock chip.

The phase-locked medium oscillator is used for outputting a 13dB sinusoidal clock signal; the multi-path power divider is used for dividing the sinusoidal clock signal into a plurality of paths of clock signals, and the plurality of paths of clock signals are used as reference clock sources of the high-speed ADC module.

The phase-locked medium oscillator is also used for outputting a homologous 100MHz low-frequency clock, and the 100MHz low-frequency clock is used as a reference clock source of the Virtex Ultrascale + module receiving end and a source of a high-speed ADC module synchronous starting signal.

The clock chip is used for providing a reference clock for high-speed signal transmission for the Virtex Ultrascale + module.

Further, the optical port module comprises a QSFP28 module; the QSFP28 module is connected with the Virtex Ultrascale + module.

Further, the FPGA module further includes: and the high-speed cache FPGA module is used for caching the sampling data.

The input port of the high-speed cache FPGA module is connected with the Virtex Ultrascale + module, and the output port of the high-speed cache FPGA module is connected with the optical port module.

Further, the optical port module comprises a QSFP28 module and an SFP + optical network port; the QSFP28 module and the SFP + optical network port are both connected with the cache FPGA module.

Further, the integrated receiving system also comprises a network management module,

the network management module comprises: the device comprises a RK3399 chip, a Xilinx XC6SLX45T-2FGG484C chip, an integrated dense analog-to-digital conversion module and a digital-to-analog conversion module.

The RK3399 chip is connected with the FPGA module through an SGMII interface, and the integrated dense analog-to-digital conversion module and the digital-to-analog conversion module are both connected with the coherent light receiving module and the RK3399 chip; the RK3399 chip is connected with the coherent light receiving module.

Further, the power circuit module includes an ATCA power management module and a power module.

The power module includes: the DC/DC switching power supply circuit, the DC/DC LDO power supply circuit and the DC/DC bus power supply circuit; the DC/DC switching power supply circuit is used for providing various digital power supplies with voltage ranging from-5V to +5V for the digital circuit; the DC/DC LDO power supply circuit is used for providing various analog power supplies with the voltage ranging from-5.2V to +10V for the analog circuit; the DC/DC bus power supply circuit is used to provide a +12V bus power supply with 30A output current and maximum 360W output power.

The ATCA power supply management module comprises a power-on time sequence control circuit which is used for controlling the power-on time sequence of various digital or analog power supplies.

The integrated receiving system for broadband large dynamic optical network signals comprises: the device comprises a coherent light receiving module, a high-speed ADC module, a clock module, an FPGA module, an optical port module and a power circuit module; the coherent light receiving module is used for receiving an input optical signal and demodulating the optical signal; the high-speed ADC module is used for performing analog-to-digital conversion on the analog electric signal obtained after demodulation; the FPGA module comprises a Virtex Ultrascale + module and is used for controlling the high-speed ADC module to realize analog-to-digital conversion, acquiring digital signals output by the high-speed ADC module and caching the acquired sampling data; the clock module is used for providing a sampling clock and a starting signal of the high-speed ADC module and a reference clock of the Virtex Ultrascale + module high-speed transceiver; the optical port module is used for outputting sampling data cached in the FPGA module; the power circuit module is used for providing power for the system and carrying out power management and monitoring. The high-speed ADC module and the FPGA module in the system can select the universal ADC module and the universal FPGA module according to actual design requirements, the system is high in compatibility, and the development cost of the system can be reduced.

Drawings

FIG. 1 is a block diagram of an integrated receiving system for broadband large dynamic optical network signals according to an embodiment;

FIG. 2 is a block diagram of an integrated receiving system for broadband large dynamic optical network signals in another embodiment;

FIG. 3 is a block diagram of a coherent light demodulation block in accordance with one embodiment;

fig. 4 is a block diagram of a network management module in another embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

In one embodiment, as shown in fig. 1, there is provided an integrated receiving system for broadband large dynamic optical network signals, the integrated receiving system comprising: the device comprises a coherent light receiving module 10, a high-speed ADC module 20, a clock module 30, an FPGA module 40, an optical port module 50 and a power circuit module 60.

The coherent optical receiving module 10 is configured to receive an input optical signal and demodulate the optical signal.

And the high-speed ADC module 20 is used for performing analog-to-digital conversion on the analog electric signal obtained after demodulation.

The FPGA module 30 includes a Virtex Ultrascale + module 301, and is configured to control the high-speed ADC module 20 to implement analog-to-digital conversion, acquire a digital signal output by the high-speed ADC module 20, and cache acquired sampling data. Preferably, the Virtex Ultrascale + module 30 is a Xilinx Virtex Ultrascale + FPGA chip with model number XCVU13P-FLGA 2577. The Virtex Ultrascale + module controls the ADC module to sample through the JESD204B protocol. The Virtex Ultrascale + series XCVU13P-FLGA2577 FPGA chip of Xilinx company has a high-speed GTY transceiver which can reach 32.75Gbps at most and has 128 pairs. In 128 pairs of GTY interfaces, 64 pairs of high-speed ADC modules need to be occupied, and FPGA chips of XCVU13P-FLGA2577 models are used for receiving digital signals converted by the high-speed ADC modules; reserving 64 pairs of GTY interfaces for data interaction between the FPGA chip of XCVU13P-FLGA2577 model and the extended cache FPGA module; and the number of other interfaces is not less than 100 (2 banks).

And the clock module 40 is used for providing a sampling clock and a starting signal of the high-speed ADC module and a reference clock of the Virtex Ultrascale + module high-speed transceiver.

And the optical interface module 50 is used for outputting the sampling data buffered in the FPGA module 40.

The power circuit module 60 is configured to provide power to the coherent light receiving module 10, the high-speed ADC module 20, the clock module 30, the FPGA module 40, and the optical interface module 50, and perform power management and monitoring.

The integrated receiving system of the broadband large dynamic optical network signal demodulates optical signals with different specifications under the 128G rate level based on a coherent light receiving scheme; performing digital-to-analog conversion to acquire front-end data by using a domestic 56G8bit ADC module; and the FPGA product with a high-speed SERDES interface and a high-throughput HBM is applied to realize the correct acquisition and caching of high-speed electric signals.

In the above integrated receiving system for broadband large dynamic optical network signals, the system includes: the device comprises a coherent light receiving module, a high-speed ADC module, a clock module, an FPGA module, an optical port module and a power circuit module; the coherent light receiving module is used for receiving an input optical signal and demodulating the optical signal; the high-speed ADC module is used for performing analog-to-digital conversion on the analog electric signal obtained after demodulation; the FPGA module comprises a Virtex Ultrascale + module and is used for controlling the high-speed ADC module to realize analog-to-digital conversion, acquiring digital signals output by the high-speed ADC module and caching the acquired sampling data; the clock module is used for providing a sampling clock and a starting signal of the high-speed ADC module and a reference clock of the Virtex Ultrascale + module high-speed transceiver; the optical port module is used for outputting sampling data cached in the FPGA module; the power circuit module is used for providing power for the system and carrying out power management and monitoring. The high-speed ADC module and the FPGA module in the system can select the universal ADC module and the universal FPGA module according to actual design requirements, the system is high in compatibility, and the development cost of the system can be reduced.

Further, the coherent light receiving module comprises an integrated coherent receiver and an integrated tunable laser component; the integrated adjustable laser component is connected with the integrated coherent receiver; the integrated coherent receiver is connected to a high-speed ADC.

Specifically, the coherent optical receiving module adopts an Integrated Coherent Receiver (ICR) and an integrated tunable laser component (ITLA) to demodulate and detect optical signals of multiple C-band modulation formats (QPSK/PM-QPSK/4QAM, 16QAM, 64 QAM). Preferably, the integrated coherent receiver is FUJITSU MICRO ICR, and the integrated tunable laser component is MICRO-ITLA.

Furthermore, the high-speed ADC module comprises a high-speed analog-to-digital conversion module with a multi-chip sampling rate as high as 56 GSPS; the high-speed analog-to-digital conversion module is connected with the coherent light receiving module and the FPGA module; the high-speed analog-to-digital conversion modules synchronously sample under the action of the starting signal provided by the sampling clock module.

Further, the high-speed analog-to-digital conversion module is an AAD08S056G module; the number of the high-speed analog-to-digital conversion modules is 4; the output end of the AAD08S056G module is connected with the high-speed transceiver of the Virtex Ultrascale + module through a CML interface; an SPI signal and a SYNC signal of the AAD08S056G module are connected to the Virtex Ultrascale + module, the SPI signal is used for configuring the AAD08S056G module, and the SYNC signal is used for synchronous sampling among four AAD08S056G modules; the sampling clock of the four AAD08S056G, the reference clock of the high-speed transceiver of the Virtex Ultrascale + module and the data processing clock are the same source clock and are provided by the clock module.

Specifically, the high-speed analog-to-digital conversion module selects an AAD08S056G chip, the AAD08S056G chip is used for 128-channel 8-bit sampling, the sampling rate can reach 56GSPS at most, and the data transmission is a 16-channel JESD204B protocol; the AAD08S056G chip supports a 128-channel @56000Msps analog-to-digital sampling function; supporting input of the highest bandwidth of 18.5 GHz; external SYNC input is supported to realize multi-board synchronization; each chip consumes as little as 3W.

Compared with the prior art, the invention has the advantages that: the direct sampling of the optical network signal integrated receiving architecture is realized through 4 AAD08S056G chips, the single-channel sampling speed is 56GHz at most, and the optical network signal integrated receiving architecture has the characteristics of wide instantaneous bandwidth, large dynamic range, strong data storage capacity, high sampling clock precision and the like.

Further, the clock module includes: the phase-locked loop comprises a phase-locked medium oscillator, a multi-path power divider and a clock chip; the phase-locked medium oscillator is used for outputting a 13dB sinusoidal clock signal; the multi-path power divider is used for dividing the sinusoidal clock signal into a plurality of paths of clock signals, and the plurality of paths of clock signals are used as reference clock sources of the high-speed ADC module; the phase-locked medium oscillator is also used for outputting a homologous 100MHz low-frequency clock, and the 100MHz low-frequency clock is used as a reference clock source of a Virtex Ultrascale + module receiving end and a source of a high-speed ADC module synchronous starting signal; the clock chip is used for providing a reference clock for high-speed signal transmission for the Virtex Ultrascale + module.

Specifically, the clock module adopts a phase-locked medium oscillator as a clock source, and a clock chip Si5347 is used as a reference clock for high-speed signal transmission.

Further, the optical port module comprises a QSFP28 module; the QSFP28 module is connected with a Virtex Ultrascale + module.

Further, the FPGA module further includes: the high-speed cache FPGA module is used for caching the sampled data; the input port of the high-speed cache FPGA module is connected with the Virtex Ultrascale + module, and the output port of the high-speed cache FPGA module is connected with the optical port module.

Specifically, when the cache space of the Virtex Ultrascale + module in the FPGA module cannot meet the system requirement, one high-speed cache FPGA module can be expanded. Preferably, the cache FPGA module adopts a 1SM21BEU2F55E2VG chip of Intel Stratix 10MX series, which supports 96-channel serial data channels (transceivers), wherein the 72-channel rate is 28.3Gbps, and the 24-channel rate is 26.0 Gbps. The HBM (512GByte/s,8G) is stored on the internal integration chip. In a 96-path high-speed channel, 64 channels are occupied by data interaction with a previous-stage FPGA, a channel 1 is reserved for an optical module, and a channel 10 is reserved for an optical network interface; and the number of other interfaces is not less than 100 (2 banks). The optical signal transceiving interface is an LC interface.

Further, the optical port module comprises a QSFP28 module and an SFP + optical network port; the QSFP28 module and the SFP + optical network interface are both connected with the cache FPGA module.

Specifically, the optical interface module includes QSFP28 and SFP + optical network port, the Intel Stratix 10MX FPGA reserves 1 channel for the QSFP28 optical module, reserves 12 channels for the SFP + optical network port, and the optical signal transceiving interface is an LC interface. And after the SFP + module completes photoelectric conversion, the SFP + module is directly connected with a high-speed port of the high-speed cache FPGA module. And a high-performance SFP + optical module is selected and matched, and the sensitivity is-16 dBm.

Further the Intel stratx 10MX series of 1SM21BEU2F55E2VG chips support the HBM 3D memory protocol stack including a plurality of memory chips and optional base logic chips connected together by through-silicon vias (TSVs). The memory bandwidth of one HBM 2 protocol stack exceeds 1Tbps, and multiple protocol stacks can be integrated into one device.

Furthermore, the integrated receiving system also comprises a network management module; the network management module comprises: the device comprises a RK3399 chip, a Xilinx XC6SLX45T-2FGG484C chip, an integrated dense analog-to-digital conversion module and a digital-to-analog conversion module; the RK3399 chip is connected with the FPGA module through an SGMII interface, and the integrated dense analog-to-digital conversion module and the digital-to-analog conversion module are both connected with the coherent light receiving module and the RK3399 chip; the RK3399 chip is connected with the coherent light receiving module.

Specifically, the network management module adopts an RK3399 chip and a Xilinx XC6SLX45T-2FGG484C chip to realize intelligent monitoring of the state of the acquisition system, and mainly completes basic configuration of a Virtex Ultrascale + module, signal loss alarm, frame loss alarm, input and output signal type and rate, channel parameters, signal error rate statistics, branch time slot allocation, port time slot allocation, line service bearing condition, equipment power supply state, board card temperature information and state monitoring and control of other peripheral equipment. The network management protocol is based on a TCP/IP protocol, and an access port is opened for the lower management equipment and the upper management equipment, so that a third-party network management system can conveniently access data.

Preferably, the integrated dense analog-to-digital conversion module is an AD5628 chip, and the digital-to-analog conversion module is a DA7091 chip. And the ICR is externally connected with an AD5628 chip and a DA7091 chip and is used for providing an output amplitude control signal and output peak envelope detection parameters of the ICR. The AD5628 chip and the DA7091 chip are communicated with the network management module through the SPI protocol and the high-speed serial interface respectively to complete instruction transmission. The ITLA is connected with a network management module through an RS232 protocol to configure the wavelength and the amplitude, and the wavelength alignment with an input optical signal is completed.

Further, the power circuit module comprises an ATCA power management module and a power module; the power module includes: the DC/DC switching power supply circuit, the DC/DC LDO power supply circuit and the DC/DC bus power supply circuit; the DC/DC switching power supply circuit is used for providing various digital power supplies with voltage ranging from-5V to +5V for the digital circuit; the DC/DC LDO power supply circuit is used for providing various analog power supplies with the voltage ranging from-5.2V to +10V for the analog circuit; the DC/DC bus power supply circuit is used for providing a +12V bus power supply with 30A output current and maximum 360W output power; the ATCA power supply management module comprises a power-on time sequence control circuit which is used for controlling the power-on time sequence of various digital or analog power supplies.

In an embodiment, as shown in fig. 2, the embodiment provides a multichannel broadband large dynamic optical network signal integrated receiving system based on Virtex ultra + FPGA, which includes a coherent light receiving module, a domestic ADC module, a sampling clock module, a Xilinx Virtex ultra + FPGA, a cache FPGA module (Intel Stratix 10MX module), an optical interface module, a network management module, and a power supply module.

As shown in fig. 3, the coherent optical receiving module employs an Integrated Coherent Receiver (ICR) and an integrated tunable laser component (ITLA) to demodulate and detect optical signals of multiple C-band modulation formats (QPSK/PM-QPSK/4QAM, 16QAM, 64 QAM). And the ICR is externally connected with an AD5628 chip and a DA7091 chip and is used for providing an output amplitude control signal and output peak envelope detection parameters of the ICR. The AD5628 chip and the DA7091 chip are communicated with the network management module through the SPI protocol and the high-speed serial interface respectively to complete instruction transmission. The ITLA is connected with the network management module through the RS232 protocol to configure the wavelength and the amplitude, and the wavelength alignment with the input optical signal is completed.

The domestic ADC module of the invention adopts 4 AAD08S056G modules to realize 4-path synchronous sampling. The AAD08S056G converts the input analog signal into an 8-bit digital signal, and after scrambling data, the data is connected with the FPGA 64 through the CML interface output to occupy 8 high-speed transceivers BANK for high-speed transmission of sampled data; an SPI signal and a SYNC signal of the AAD08S056G are connected to the Xilinx FPGA, the SPI signal is used for configuring the ADC, and the SYNC signal is used for synchronous sampling among the four ADCs; the sampling clock of the four pieces of AAD08S056G, the reference clock of the FPGA high-speed transceiver and the data processing clock need the same source clock and are connected to a phase-locked medium oscillator (PLDRO); the key to the 4-chip AAD08S056G synchronous sampling is that the SYNC signal of each ADC has a definite phase relationship, has fast transition edges, and has low jitter time. The phase-locked dielectric oscillator (PLDRO) can generate a 13dB sinusoidal clock signal that can be used as a reference clock source for multiple ADCs via a multi-path Power Divider (PD). Meanwhile, the PLDRO can output a homologous 100MHz low-frequency clock, and can be used as a reference clock source of an FPGA receiving end and a source of an ADC synchronous starting signal SYNC.

As shown in fig. 4, in order to perform system management on two FPGAs, four ADC modules and multiple output optical modules as a data receiving front end and a data storage unit, a network management module based on an RK3399 chip is designed for a board card. RK3399 is a domestic high-performance and high-cost-performance control chip, is matched with a 45T FPGA to serve as an interface extension, and is used as a substrate management controller (BMC) in an ATCA protocol to jointly realize the functions of register reading and writing and data transmission of a main function module of a board card.

The power circuit module is composed of two parts: ATCA power supply management module and power supply module. The digital power supply and the analog power supply provide stable and reliable various digital power supplies and analog power supplies for the system, control the power-on sequence of different power supplies, monitor overvoltage and undervoltage and implement protection. two-48V power supplies which are mutually backup are sent to a power supply switching circuit after passing through a protection circuit, and the power supply switching circuit sends a switching command to switch the power supply and close the power supply output according to the states of overvoltage, undervoltage, overcurrent and the like in the power supply management circuit. The energy storage circuit realizes the function that the output power supply does not shake in the power supply switching process. The EMI filter circuit filters EMI interference. The DC/DC bus power supply circuit adopts a BQ60120HEB25NKS device manufactured by Synqar corporation, converts a-48V input power supply into a +12V bus power supply, and has 30A output current and maximum 360W output power. The +12V bus power supply meets the actual 300W power consumption requirement according to the 360W design, and can supply power safely and stably. The power supply power-on control circuit turns off the bus power supply according to the power-on and power-off commands given by the monitoring circuit. The power module part has three parts: the power supply circuit comprises a DC/DC switching power supply circuit, a DC/DC LDO power supply circuit and a power-on sequence control circuit. The DC/DC switching power supply circuit provides various digital power supplies with voltage ranging from-5V to +5V for the digital circuit. The DC/DC LDO power supply circuit provides various analog power supplies with the voltage ranging from-5.2V to +10V for the analog circuit. The whole power supply module provides 73 kinds of power supplies for the system. The power-on time sequence control circuit controls the power-on time sequence of various digital or analog power supplies, meets the power-on requirements of various devices, and simultaneously avoids overlarge impact current generated in the power-on process. When all units of the system work normally at full speed, the input current is less than 20A/12V, and the maximum impact current in the power-on process is less than 6A/12V.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. An integrated receiving system for broadband large dynamic optical network signals, the integrated receiving system comprising: the device comprises a coherent light receiving module, a high-speed ADC module, a clock module, an FPGA module, an optical port module and a power circuit module;

the coherent light receiving module is used for receiving an input optical signal and demodulating the optical signal;

the high-speed ADC module is used for performing analog-to-digital conversion on the analog electric signal obtained after demodulation;

the FPGA module comprises a Virtex Ultrascale + module and is used for controlling the high-speed ADC module to realize analog-to-digital conversion, acquiring digital signals output by the high-speed ADC module and caching the acquired sampling data;

the clock module is used for providing a sampling clock and a starting signal of the high-speed ADC module and a reference clock of the Virtex Ultrascale + module high-speed transceiver;

the optical port module is used for outputting sampling data cached in the FPGA module;

the power circuit module is used for providing power for the coherent light receiving module, the high-speed ADC module, the clock module, the FPGA module and the optical port module, and performing power management and monitoring.

2. The integrated receiving system according to claim 1, wherein the coherent optical receiving module comprises an integrated coherent receiver and an integrated tunable laser component;

the integrated adjustable laser component is connected with the integrated coherent receiver; the integrated coherent receiver is coupled to the high-speed ADC.

3. The integrated receiving system according to claim 1, wherein the high-speed ADC module comprises a multi-slice high-speed analog-to-digital conversion module with a sampling rate of up to 56 GSPS; the high-speed analog-to-digital conversion module is connected with the coherent light receiving module and the FPGA module;

and the high-speed analog-to-digital conversion modules synchronously sample under the action of a starting signal provided by the sampling clock module.

4. The integrated receiving system according to claim 3, wherein the high-speed analog-to-digital conversion module is an AAD08S056G module; the number of the high-speed analog-to-digital conversion modules is 4;

the output end of the AAD08S056G module is connected with the high-speed transceiver of the Virtex Ultrascale + module through a CML interface,

an SPI signal and a SYNC signal of the AAD08S056G module are connected to the Virtex Ultrascale + module, the SPI signal is used for configuring the AAD08S056G module, and the SYNC signal is used for synchronous sampling among four AAD08S056G modules;

the sampling clock of the four AAD08S056G, the reference clock of the high-speed transceiver of the Virtex Ultrascale + module and the data processing clock are the same source clock, and are provided by the clock module.

5. The integrated receiving system according to claim 1, wherein the clock module comprises: the phase-locked loop comprises a phase-locked medium oscillator, a multi-path power divider and a clock chip;

the phase-locked medium oscillator is used for outputting a 13dB sinusoidal clock signal; the multi-path power divider is used for dividing the sinusoidal clock signal into a plurality of paths of clock signals, and the plurality of paths of clock signals are used as reference clock sources of the high-speed ADC module;

the phase-locked medium oscillator is also used for outputting a homologous 100MHz low-frequency clock, and the 100MHz low-frequency clock is used as a reference clock source of the Virtex Ultrascale + module receiving end and a source of a high-speed ADC module synchronous starting signal;

the clock chip is used for providing a reference clock for high-speed signal transmission for the Virtex Ultrascale + module.

6. The integrated receiving system of claim 1, wherein the optical port module comprises a QSFP28 module; the QSFP28 module is connected with the Virtex Ultrascale + module.

7. The integrated receiving system according to claim 1, wherein the FPGA module further comprises: the high-speed cache FPGA module is used for caching the sampling data;

the input port of the high-speed cache FPGA module is connected with the Virtex Ultrascale + module, and the output port of the high-speed cache FPGA module is connected with the optical port module.

8. The integrated receiving system of claim 7, wherein the optical port module comprises a QSFP28 module and a SFP + optical network port;

the QSFP28 module and the SFP + optical network port are both connected with the cache FPGA module.

9. The integrated receiving system according to claim 1, further comprising a network management module,

the network management module comprises: the device comprises a RK3399 chip, a Xilinx XC6SLX45T-2FGG484C chip, an integrated dense analog-to-digital conversion module and a digital-to-analog conversion module;

the RK3399 chip is connected with the FPGA module through an SGMII interface, and the integrated dense analog-to-digital conversion module and the digital-to-analog conversion module are both connected with the coherent light receiving module and the RK3399 chip; the RK3399 chip is connected with the coherent light receiving module.

10. The integrated receiving system of claim 1, wherein the power circuit module comprises an ATCA power management module and a power module;

the power module includes: the DC/DC switching power supply circuit, the DC/DC LDO power supply circuit and the DC/DC bus power supply circuit; the DC/DC switching power supply circuit is used for providing various digital power supplies with voltage ranging from-5V to +5V for the digital circuit; the DC/DC LDO power supply circuit is used for providing various analog power supplies with the voltage ranging from-5.2V to +10V for the analog circuit; the DC/DC bus power supply circuit is used for providing a +12V bus power supply with 30A output current and maximum 360W output power;

the ATCA power supply management module comprises a power-on time sequence control circuit which is used for controlling the power-on time sequence of various digital or analog power supplies.

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