CN112180777A - Multi-channel broadband signal acquisition architecture based on Virtex UltraScale + FPGA - Google Patents
Multi-channel broadband signal acquisition architecture based on Virtex UltraScale + FPGA Download PDFInfo
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- CN112180777A CN112180777A CN202010858318.9A CN202010858318A CN112180777A CN 112180777 A CN112180777 A CN 112180777A CN 202010858318 A CN202010858318 A CN 202010858318A CN 112180777 A CN112180777 A CN 112180777A
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
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Abstract
The invention discloses a multichannel broadband signal acquisition architecture based on Virtex UltraScale + FPGA, which comprises an ADC module, a time sequence synchronization module, a storage module, a Virtex Ultrascale module, an optical transceiver module, an FPGA module, a power supply module and a network switching module, wherein the Virtex Ultrascale module is used for controlling the ADC module to sample, and the time sequence synchronization module is used for providing a local clock of the ADC module, a frame synchronization clock and a reference clock of the FPGA module, so that 8 AD sampling channels are realized, the single-channel sampling speed is up to 3GHz, and the sampling rate of the system can reach 20 Gsps.
Description
Technical Field
The invention belongs to a broadband signal sampling technology, and particularly relates to a multichannel broadband signal acquisition architecture based on Virtex UltraScale + FPGA.
Background
With the continuous development of electronic technology, in the modern electronic reconnaissance electromagnetic environment, the coverage range of signals is continuously expanded, the coverage range of frequency spectrum is about 0.2-100 GHz, the signal density is higher and higher, the pulse density can reach million pulses per second, the signal patterns are more and more, such as frequency agility, waveform agility and the like, and the factors bring great difficulty to the electronic reconnaissance. In the face of the challenge of the modern complex reconnaissance environment to the design of the radar reconnaissance receiver, the electronic reconnaissance receiver must have wider instantaneous bandwidth and larger dynamic range.
The high-speed broadband signal acquisition module is a core unit of the electronic reconnaissance receiver, the high-speed sampling rate and the number of channels of the high-speed broadband signal acquisition module in China are not high at present, and meanwhile, the delay adjustment precision of a sampling clock between the channels is not high, so that the working performance of the electronic reconnaissance receiver is influenced.
Disclosure of Invention
The invention aims to provide a multichannel broadband signal acquisition architecture based on Virtex UltraScale + FPGA.
The technical solution for realizing the purpose of the invention is as follows: the utility model provides a multichannel broadband signal acquisition framework based on Virtex UltraScale + FPGA, includes ADC module, chronogenesis synchronization module, memory module, Virtex Ultrascale module, light transceiver module, FPGA module, power module and network switching module, wherein:
the Virtex Ultrascale module is connected with the ADC module and is used for controlling the ADC module to sample;
the time sequence synchronization module is used for providing a local clock of the ADC module, a frame synchronization clock and a reference clock of the FPGA module;
the storage module is used for storing the sampling data;
the optical transceiver module is used for realizing data communication;
the FPGA module is used for realizing power-on time sequence control and Ethernet control of a power supply;
the network switching module is used for realizing network communication;
the power supply module is used for supplying power.
Preferably, the ADC module adopts 4 AD9208 chips.
Preferably, the Virtex Ultrascale module comprises an XCVU9P-FLGB2104 chip and two pieces of 1G FLASH connected to the XCVU9P-FLGB2104 chip.
Preferably, the timing synchronization module employs HM 7043.
Preferably, the optical transceiver module adopts a GTY x12 optical module.
Preferably, the network switching module adopts an 88E11 chip to realize network switching with an RJ45 interface.
Preferably, the Virtex Ultrascale module controls the ADC module to sample through a JESD204B protocol.
Compared with the prior art, the invention has the following remarkable advantages: the invention realizes 8 AD sampling channels, has the highest single-channel sampling speed of 3GHz, and has the characteristics of simple structure, high sampling speed, high sampling clock synchronization precision and the like.
The present invention is described in further detail below with reference to the attached drawings.
Drawings
FIG. 1 is a block diagram of a multichannel broadband signal acquisition architecture based on Virtex UltraScale + FPGA.
FIG. 2 is a flow chart of Aritx-7 reset and control logic.
FIG. 3 is a functional block diagram of the XCVU9P-FLGB 2104.
Fig. 4 is a functional block diagram of an ADC module.
Detailed Description
A multichannel broadband signal high-speed acquisition architecture based on Virtex Ultrascale + FPGA comprises an ADC module, a time sequence synchronization module, a storage module, a Virtex Ultrascale module, an optical transceiver module, an FPGA module, a power supply module and a network exchange module.
The Virtex Ultrascale module is connected with the ADC module and is used for controlling the ADC module to sample;
the time sequence synchronization module is used for providing a local clock of the ADC module, a frame synchronization clock and a reference clock of the FPGA module;
the storage module is used for storing the sampling data;
the optical transceiver module is used for high-speed inter-board data communication;
the FPGA module is used for realizing power-on time sequence control and Ethernet control of a power supply;
the network switching module is used for sampling the external high-speed network communication of the board;
the power supply module is used for supplying power.
Specifically, the ADC module adopts 4 AD9208 chips, the AD9208 chip is a dual-channel 14-bit sampling, the maximum sampling rate is 3GSPS, and the data transmission is 8 paths of JESD204B protocols; a configurable clock delay register and an internal direct current bias self-calibration function are arranged in the chip. The ADC module supports an 8-channel maximum 14bit @3000Msps analog-to-digital sampling function; supporting the input of a sampling clock with the maximum 3.0 GHz; the input frequency of the analog signal is 50 MHz-6.0 GHz; a sampling clock stepping delay adjustable function; supporting the external DEVCLK and REFCLK inputs to achieve multi-plate synchronization.
Specifically, the timing synchronization module adopts the HM7043 to provide a local clock of the ADC, a frame synchronization clock and a reference clock of the FPGA, and performs 8-way synchronous sampling, clock homology and clock delay on the ADC chip.
Specifically, the memory module comprises two clusters of 256M80 DDR4 and one cluster of 256M8 DDR 3; DDR4 provides a large amount of buffer space for temporary storage of collected and transmitted data; DDR3 is used for XCVU9P to run soft cores, and 4 ADCs are conveniently controlled to be synchronous;
specifically, the Virtex Ultrascale module comprises an XCVU9P-FLGB2104 chip, wherein the XCVU9P is used as an on-board functional core and is used for realizing connection of an SRAM (static random access memory), a GTY (gigabit-capable bus) interface and an optical module interface; the Virtex Ultrascale module comprises two pieces of 1G FLASH connected with an XCVU9P-FLGB2104 chip and used for storing an XCVU9P power-on loading program, and the two pieces of FLASH jointly form an SPIx8 mode, so that the speed of the FPGA power-on loading program is higher; the XCVU9P is externally connected with four AD9208 chips and is used for synchronously sampling eight paths of signals; the XCVU9P-FLGB2104 chip is connected with 24 LVTTL signals, 28 pairs of LVDS signals and 32 pairs of GTY signals and is used for external GPIO control and data transmission; the XCVU9P-FLGB2104 chip is connected with the 12-path optical transceiver module and is used for data transmission.
The Virtex Ultrascale module controls 4 ADC chips to perform high-speed sampling through a JESD204B protocol, sampling clock control among channels is realized by adopting an HMC7043 chip, sampling data can be stored in a DDR4, and high-speed data interaction is realized with an optical module through a network switching module.
The FPGA module adopts Aritx-7 XC7A50T, is connected with all power chips in an SPI communication mode, and realizes effective power supply on a board by controlling the on-off time sequence of the power chips.
The optical transceiver module adopts a GTY x12 optical module, and the network switching module adopts an 88E11 chip and an RJ45 interface to realize network switching.
The invention realizes 8 AD sampling channels, the highest single-channel sampling speed is 3GHz, and the sampling rate of the system can reach 20 Gsps.
Example 1
As shown in fig. 1, the present embodiment provides a multichannel wideband signal acquisition architecture based on Virtex Ultrascale + FPGA, which includes an ADC module, a timing synchronization module, a storage module, a Virtex Ultrascale module, an FPGA module, a power module, a network switching module, an optical module, and the like.
As shown in fig. 2, the FPGA module adopts Aritx-7 XC7a50T, and is used to implement ethernet debug XCVU9P FPGA and board power supply sequence control. The Aritx-7 XC7A50T chip is externally hung with a256M 8 organization form DDR3 SDRAM chip for the ARITX-7 XC7A50T chip to run a MicroBlaze processor soft core. The soft core of the processor runs an LWIP protocol stack to realize TCP/IP communication, and the Socket data packet of upper computer VIVADO software is analyzed and converted into a JTAG time sequence to complete JTAG debugging, downloading, programming and curing of an XCVU9P FPGA chip.
The power-on control and power state indication signals of the power module are connected to the ARITX-7 XC7A50T chip, the power-on sequence of each path of power is controlled by the ARITX-7 XC7A50T chip, and the ARITX-7 XC7A50T chip detects the states of all the power supplies and reports the states. The ARITX-7 XC7A50T chip is externally connected with an EEPROM for storing delay compensation information of ADC configuration temperature change and HM7043 temperature change delay information. The ARITX-7 XC7A50T chip calls the register value delayed by the HM7043 at the temperature every ten minutes according to the current temperature, and the ARITX-7 XC7A50T chip reconfigures the HMC7043 delay register; meanwhile, ADC temperature compensation information stored in the EEPROM is called, the information is reported to the XCVU9P, and the XCVU9P configures the delay compensation of the current temperature of the ADC so that the sampling precision of the ADC is controlled within 1 PS. The ARITX-7 XC7A50T chip is also connected with VPX P0 slot information and an I2C bus, and supports slot number input and I2C bus information response. The ARITX-7 XC7A50T chip is connected with the MLVDS clock input and output of the VPX P0 slot, and can input or output the system reference clock. The ARITX-7 XC7A50T chip is connected with a VPX P1 slot single-ended signal 8bit, and the 8bit unified input and output direction control is realized by using a bidirectional voltage isolation chip.
The on-board management unit circuit has independent power supply, and ensures that the ARITX-7 XC7A50T chip independently supplies power to the on-board high-power device XCVU9P under the normal operation condition to configure functions. The power-up control and status monitor signals for all the remaining power supplies on the board are connected to the ARITX-7 XC7A50T chip. The power-on sequence of the FPGA requires that the ARITX-7 XC7A50T chip controls the power supply state of the power rail and monitors the Powergood signal of the power rail in real time, and the power rail can be monitored through a network and a serial port. The purpose of monitoring the power supply is to provide the ARITX-7 XC7A50T chip internal reset circuit as a control basis. The ARITX-7 XC7A50T chip is responsible for the JTAG and BOOT control of XCVU 9P. The control of these reset signals all depend on the ARITX-7 XC7A50T chip logic. Under the normal condition, the ARITX-7 XC7A50T chip controls the power-on sequence of the power supply according to the requirement of the FPGA chip, and under the condition that all power supply states are normal, the ARITX-7 XC7A50T chip still needs to carry out logic reset on the XCVU9P all the time under the condition that the XCVU9P FPGA is input to the ARITX-7 XC7A50T chip to complete the effective DONE signal.
As shown in fig. 3, BANK0 and BANK65 of XCVU9P configure BANK, M [2:0] bit on BANK0 selects FLASH load mode, the present invention is Master SPI X8 (dual X4) mode, M [2:0] is 001, its BANK operating voltage is 1.8V, two MT25QL01GBBB1EW9-0SIT type FLASH are connected, BANK 64-72 constituting BPI × 8 mode XCVU9P connects 10 MT40a256M16LY-062E type DDR4 for mass data buffer, and BANK voltage is 1.2V. The BANK67 of XCVU9 is connected with a piece of AS4C256M8D3A-12BIN type DDR3 for running a soft core program, and the BANK voltage is 1.5V. BANK468 of XCVU9P connects 24 TTLs and 28 pairs of LVDS signals, with BNAK voltage of 1.8V. The BANK46 and BANK47 of XCVU9P are connected with SPI signals of four AD 9208-type ADCs and are used for configuring the ADCs, and the BNAK voltage is 1.8V. The BANK68 of XCVU9P is connected with RGMII signals of a switch chip and used for data transmission and network programming of FPGA, and the BNAK voltage is 1.8V. The XCVU9P high-speed transceivers BANK 120-127 are connected with 32-path GTY signals. The high-speed transceivers BANK128, BANK233 and BANK231 of the XCVU9P are connected to 12 optical fiber transmission and reception signals. The high-speed transceivers BANK 224-232 of XCVU9P are connected with 4-chip ADCs.
As shown in fig. 4, the ADC module of the present invention adopts 4 AD9208 chips to implement eight-way synchronous sampling, and the JESD204B protocol signal of AD9208 is connected to the FPGA 32 to the high-speed transceiver, occupying four high-speed transceivers BANK, for high-speed transmission of sampled data; an SPI signal and a SYNC signal of the AD9208 are connected to the FPGA, the SPI signal is used for configuring the ADC, and the SYNC signal is used for JESD204B protocol transmission synchronization; local clocks and frame synchronization clocks of 4 AD9208 and reference clocks of the FPGA high-speed transceiver need homologous clocks and are connected to an HMC7043 clock chip; the key points of the 4-chip A9208 synchronous sampling are the JESD204B protocol transmission delay synchronization, the ADC sampling clock delay synchronization and the elimination of the ADC analog front end direct current offset.
Claims (7)
1. The utility model provides a multichannel broadband signal acquisition framework based on Virtex UltraScale + FPGA, its characterized in that includes ADC module, chronogenesis synchronization module, memory module, Virtex Ultrascale module, light transceiver module, FPGA module, power module and network switch module, wherein:
the Virtex Ultrascale module is connected with the ADC module and is used for controlling the ADC module to sample;
the time sequence synchronization module is used for providing a local clock of the ADC module, a frame synchronization clock and a reference clock of the FPGA module;
the storage module is used for storing the sampling data;
the optical transceiver module is used for realizing data communication;
the FPGA module is used for realizing power-on time sequence control and Ethernet control of a power supply;
the network switching module is used for realizing network communication;
the power supply module is used for supplying power.
2. The Virtex UltraScale + FPGA-based multi-channel wideband signal acquisition architecture as claimed in claim 1, wherein the ADC module employs 4 AD9208 chips.
3. The Virtex UltraScale + FPGA-based multi-channel wideband signal acquisition architecture as claimed in claim 1, wherein the Virtex Ultrascale module comprises an XCVU9P-FLGB2104 chip and two pieces of 1G FLASH connected to the XCVU9P-FLGB2104 chip.
4. The Virtex UltraScale + FPGA-based multi-channel wideband signal acquisition architecture as claimed in claim 1, wherein the timing synchronization module employs HM 7043.
5. The Virtex UltraScale + FPGA-based multi-channel wideband signal acquisition architecture as claimed in claim 1, wherein the optical transceiver module employs a GTY x12 optical module.
6. The Virtex UltraScale + FPGA-based multi-channel wideband signal acquisition architecture as claimed in claim 1, wherein said network switching module employs an 88E11 chip to implement network switching with an RJ45 interface.
7. The Virtex UltraScale + FPGA-based multi-channel wideband signal acquisition architecture as claimed in claim 1, wherein the Virtex UltraScale module controls the ADC module to sample via JESD204B protocol.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114745061A (en) * | 2022-03-31 | 2022-07-12 | 中国人民解放军国防科技大学 | Integrated receiving system of broadband large dynamic optical network signal |
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