CN206451166U - A kind of synchronous acquisition circuit based on multi-channel high-speed ADC - Google Patents
A kind of synchronous acquisition circuit based on multi-channel high-speed ADC Download PDFInfo
- Publication number
- CN206451166U CN206451166U CN201720178961.0U CN201720178961U CN206451166U CN 206451166 U CN206451166 U CN 206451166U CN 201720178961 U CN201720178961 U CN 201720178961U CN 206451166 U CN206451166 U CN 206451166U
- Authority
- CN
- China
- Prior art keywords
- ports
- resistance
- chip microcomputer
- electric capacity
- data acquisition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Power Sources (AREA)
Abstract
The utility model proposes a kind of synchronous acquisition circuit based on multi-channel high-speed ADC, including adc data acquisition module, synchronised clock control module and FPGA module；Adc data acquisition module is connected with FPGA module and synchronised clock control module, and the radiofrequency signal of input is transported in FPGA module by JESD204B interfaces；Synchronised clock control module provides clock signal for adc data acquisition module, and provides Sysref signals for adc data acquisition module and FPGA module.Advantage is that this synchronous circuit is due to without radio circuit, simplifying hardware design, solving defect problem of the traditional design in terms of volume, power consumption, size；This circuit is when increasing synchronizing channel, it is only necessary to increase clk signal and sysref output way, it is not necessary to which other extra circuits carry out Computer Aided Design or calibrated channel.Therefore, in theory, synchronizing channel be can be unlimited increase, thus be particularly suitable for Radar Signal Processing.
Description
Technical field
The utility model belongs to field, and in particular to a kind of synchronous acquisition circuit based on multi-channel high-speed ADC.
Background technology
Traditional multi-channel synchronous data acquisition circuit is to use super-heterodyne architecture, and radiofrequency signal is down-converted into a fixation
Intermediate-freuqncy signal, passing through low speed ADC carry out data acquisition.Traditional low speed ADC is generally received using LVDS interface with rear end
Equipment enters row data communication, is so easy for the too many I/O port of rear end receiving device temporary occur, and when PCB trace more
Trouble.Data need synchronization to be acquired, it is necessary that the synchronization of multiple radio frequency down-conversion multi-channel output signals and multi-disc low speed
ADC synchronizes collection.Synchronous acquisition circuit physical culture of the prior art is as shown in Figure 1.
Meanwhile, there is following defect in prior art：
1st, prior art gathers two parts by radio frequency down-conversion and low speed ADC and constituted, and circuit is described herein and only needs to
One high-speed ADC Acquisition Circuit is that can be achieved, by contrast, and prior art suffers from obvious inferior position in volume, power consumption and weight.
2nd, the increase of careless synchronizing channel, prior art implements extremely difficult, or is difficult to.
3rd, the signal bandwidth that prior art can be handled is narrow, need to such as handle the signal of big bandwidth, it is necessary to multiple modular concurrents
Processing.
4th, synchronous progress is poor, if desired for high-precision synchronization, it is necessary to additionally add calibrated channel；
Utility model content
The purpose of this utility model is：For problems of the prior art set forth above, the utility model is carried
For a kind of synchronous acquisition circuit based on multi-channel high-speed ADC.
The technical solution adopted in the utility model is as follows：
A kind of synchronous acquisition circuit based on multi-channel high-speed ADC, including the control of adc data acquisition module, synchronised clock
Module and FPGA module；The adc data acquisition module is connected with FPGA module and synchronised clock control module, by penetrating for input
Frequency signal is transported in FPGA module by JESD204B interfaces；The synchronised clock control module is adc data acquisition module
Clock signal is provided, and Sysref signals (i.e. reference signal) are provided for adc data acquisition module and FPGA module.
Further, in the synchronised clock control module, single-chip microcomputer U501 vdd terminal mouthful and VDD3 ports and electric capacity
C503 one end, electric capacity C504 one end and the connection of electric capacity C505 one end, the electric capacity C503 other ends, the electric capacity C504 other ends and electric capacity
The C505 other ends are grounded；Single-chip microcomputer U501 CLKIN ports are connected with electric capacity C501 one end, single-chip microcomputer U501 CLKIN_N ends
Mouth is connected with electric capacity C502 one end；Single-chip microcomputer U501 PD_N ports are connected with resistance R504 one end and resistance R503 one end, single
Piece machine U502 SCLK ports are connected with resistance R507 one end, and single-chip microcomputer U501 CP_RSET ports are grounded by resistance R505,
Single-chip microcomputer U501 OUT_RSET ports are grounded by resistance R506；Single-chip microcomputer U501 GND ports and PAD ports ground connection；It is single
Piece machine U501 SDIO ports are connected with resistance R508 one end；Single-chip microcomputer U501 SYNC_OUT_N and resistance R509 one end and electricity
Hold the connection of C506 one end, resistance R509 other ends ground connection, the electric capacity C506 other ends and resistance R511 one end and resistance R512 one end
Connection；Single-chip microcomputer U501 SYNC_OUT ports are connected with resistance R510 one end and electric capacity C507 one end, the resistance R510 other ends
Ground connection, the electric capacity C507 other ends are connected with resistance R513 one end and resistance R514 one end；Single-chip microcomputer U501 OUT7_N ports with
Resistance R515 one end and the connection of electric capacity C508 one end, resistance R515 other ends ground connection；Single-chip microcomputer U501 OUT7 ports and resistance
R516 one end and the connection of electric capacity C509 one end, resistance R516 other ends ground connection；Single-chip microcomputer U501 OUT6_N ports and resistance
R517 one end and the connection of electric capacity C510 one end, resistance R517 other ends ground connection；Single-chip microcomputer U501 OUT6 ports and resistance R518
One end and the connection of electric capacity C511 one end, resistance R518 other ends ground connection.
Further, in the adc data acquisition module, single-chip microcomputer U52A SYNCINB- ports and electric capacity C1286 mono-
End connection, single-chip microcomputer U52A SYNCINB+ ports are connected with electric capacity C1287 one end, and the electric capacity C1286 other ends pass through resistance
R393 is connected with the electric capacity C1287 other ends, and single-chip microcomputer U52A VMON ports connect power supply, single-chip microcomputer U52A VCM ports and electricity
The connection of R395 one end is hindered, resistance R395 is connected with electric capacity C912 one end, electric capacity C912 other ends ground connection；Single-chip microcomputer U52A VM_
BYP ports are connected with electric capacity C913 one end, electric capacity C913 other ends ground connection；Single-chip microcomputer U52A VP_BYP ports and electric capacity C916
One end and the connection of resistance R397 one end, electric capacity C916 other ends ground connection, another termination powers of resistance R397；Single-chip microcomputer U52A's
RBIAS_EXT ports are connected with resistance R398 one end, and single-chip microcomputer U52A RBIAS_EXT ports are connected with resistance R399 one end,
The resistance R398 other ends and resistance R399 other ends ground connection；Single-chip microcomputer U52A RSTB ports are connected with resistance R400 one end, electricity
Hinder R400 other ends ground connection；Single-chip microcomputer U52A PWDN ports are connected with resistance R391 one end, resistance R391 other ends ground connection, single
Piece machine U52A I RQ ports are connected with resistance R392 one end, single-chip microcomputer U52A FD ports and resistance R390 one end and resistance
R394 one end is connected, resistance R390 other ends ground connection.
Further, in the synchronised clock control module and adc data acquisition module, the synchronised clock control module
Middle resistance R503 is connected with the CSB ports of single-chip microcomputer U52A in adc data acquisition module, electric in the synchronised clock control module
Resistance R508 is connected with the SDIO ports of single-chip microcomputer U52A in adc data acquisition module, resistance in the synchronised clock control module
R507 is connected with the SCLK ports of single-chip microcomputer U52A in adc data acquisition module, single-chip microcomputer in the synchronised clock control module
U501 RESRT_N ports are connected with the RSTB ports of single-chip microcomputer U52A in adc data acquisition module, the synchronised clock control
Single-chip microcomputer U501 OUT0 ports in module --- OUT7 ports and the SERDOUT0 of single-chip microcomputer U52A in adc data acquisition module
+ port --- SERDOUT7+ ports connect one to one, single-chip microcomputer U501 OUT0_N ends in the synchronised clock control module
Mouth --- OUT7_N ports and SERDOUT0- ports of single-chip microcomputer U52A in adc data acquisition module --- SERDOUT7- ports
Connect one to one, electric capacity C501 and single-chip microcomputer U52A in adc data acquisition module in the synchronised clock control module
CLK- ports are connected, electric capacity C502 and single-chip microcomputer U52A in adc data acquisition module CLK in the synchronised clock control module
+ port is connected, resistance R394 and single-chip microcomputer U52A in adc data acquisition module FD_N ends in the synchronised clock control module
Electric capacity C510 and single-chip microcomputer U52A in adc data acquisition module SYSREF- ends in mouth connection, the synchronised clock control module
Electric capacity C511 and single-chip microcomputer U52A in adc data acquisition module SYSREF+ ends in mouth connection, the synchronised clock control module
Resistance R511 and single-chip microcomputer U52A in adc data acquisition module SYNCINB- in mouth connection, the synchronised clock control module
Port is connected, electric capacity C514 and single-chip microcomputer U52A in adc data acquisition module SYNCINB in the synchronised clock control module
+ port is connected.
In summary, by adopting the above-described technical solution, the beneficial effects of the utility model are：
1. a synchronous circuit due to without radio circuit, simplifying hardware design, solve traditional design volume, power consumption,
Defect problem in terms of size；
2. a circuit is when increasing synchronizing channel, it is only necessary to increases c l k signals and sysref output way, is not required to
Other circuits that will be extra carry out Computer Aided Design or calibrated channel.Therefore, in theory, synchronizing channel be can be unlimited increasing
Plus, thus it is particularly suitable for Radar Signal Processing.
3. because circuit uses high-speed ADC, current high-speed ADC sample rate highest has 5GSPS, and instant bandwidth can be arrived
2.5G, relatively conventional synchronous circuit bandwidth only has tens M situation, there is qualitative leap.
Brief description of the drawings
Fig. 1 is synchronous acquisition circuit of the prior art；
Fig. 2 is synchronous circuit theory diagram of the present utility model；
Fig. 3 is synchronised clock control module circuit diagram；
Fig. 4 is high-speed ADC data acquisition module circuit diagram.
Embodiment
All features disclosed in this specification, can be with any in addition to mutually exclusive feature and/or step
Mode is combined.
The utility model is elaborated with reference to Fig. 2, Fig. 3, Fig. 4.
The utility model high speed ADC, which is used, is based on JESD204B interfaces, is below the interface brief introduction：
JESD204B is a kind of JEDEC standard, for single main frame (such as FPGA or ASIC) and one or more data
High speed serialization link between converter.Newest specification is provided per passage or per differential pair highest 12.5Gbps speed.Future
Version 12.5Gbps and higher speed may be provided.Passage is reduced to using 8B/10B codings, thus the effective bandwidth of passage
The 80% of theoretical value.Clock is embedded in a stream, therefore without extra clock signal.Multiple passages can be combined together
To improve handling capacity, data link layer protocol ensures data integrity.In FPGA/ASIC, to realize data frame transfer,
The resource that JESD204 needs is far more than simple LVDS or CMOS.It significantly reduces wiring requirement, but requires using more
Expensive FPGA, PCB layout is also more complicated.
With the continuous lifting of IC Processing Ability of Manufacturing, ADC/DAC sample rate also more and more higher, from tens M of beginning,
To hundreds of M, in several G till now.The continuous lifting of careless sample rate, carrying out Interface design using traditional LVDS buses can not expire
Sufficient chip design needs, therefore high-speed ADC/DAC of JESD204B interfaces turns into a kind of trend.
The design mainly realizes that multiple Channel Synchronous coherents are adopted using a kind of high-speed ADC chip based on JESD204B interfaces
The hardware design of collection.Compared with traditional scheme, without radio down-converting circuitry, synchronous circuit design is more succinct flexible, can expand
Malleability is strong.Synchronous circuit theory diagram is as indicated with 2.
, wherein it is desired to ensure that the clock cabling between multi-disc ADC is isometric, and every ADC clock cabling can be correct
Gather sysref signals.The difficult point of Synchronization Design, is the generation of clock circuit and synchronous control signal.
Circuit operation principle is：Clock circuit produces clock and provides clock to two panels ADC first, then synchronous control signal
After circuit sends sysref synchronizing signals to two panels ADC, two panels high-speed ADC is received after signal simultaneously, is started simultaneously at and is adopted
Collect data.Data after collection are assisted by being encoded inside ADC and being transferred to rear end receiving device (FPGA) by JESD204B
View ensures that data are synchronous to receiving device, is so achieved that the synchronous acquisition of data.
Clock and sysref signal generating circuits are as shown in Figure 3.
High-speed ADC data acquisition module circuit diagram is as shown in Figure 4.
Claims (4)
1. a kind of synchronous acquisition circuit based on multi-channel high-speed ADC, it is characterised in that including adc data acquisition module, synchronization
Clock control module and FPGA module；The adc data acquisition module is connected with FPGA module and synchronised clock control module, will
The radiofrequency signal of input is transported in FPGA module by JESD204B interfaces；The synchronised clock control module is adc data
Acquisition module provides clock signal, and provides Sysref signals for adc data acquisition module and FPGA module.
2. a kind of synchronous acquisition circuit based on multi-channel high-speed ADC according to claim 1, it is characterised in that described
In synchronised clock control module, single-chip microcomputer U501 vdd terminal mouthful and VDD3 ports and electric capacity C503 one end, electric capacity C504 one end and
Electric capacity C505 one end is connected, the electric capacity C503 other ends, the electric capacity C504 other ends and electric capacity C505 other ends ground connection；Single-chip microcomputer U501
CLKIN ports be connected with electric capacity C501 one end, single-chip microcomputer U501 CLKIN_N ports are connected with electric capacity C502 one end；Monolithic
Machine U501 PD_N ports are connected with resistance R504 one end and resistance R503 one end, single-chip microcomputer U502 SCLK ports and resistance
R507 one end is connected, and single-chip microcomputer U501 CP_RSET ports are grounded by resistance R505, single-chip microcomputer U501 OUT_RSET ports
It is grounded by resistance R506；Single-chip microcomputer U501 GND ports and PAD ports ground connection；Single-chip microcomputer U501 SDIO ports and resistance
R508 one end is connected；Single-chip microcomputer U501 SYNC_OUT_N is connected with resistance R509 one end and electric capacity C506 one end, resistance R509
The other end is grounded, and the electric capacity C506 other ends are connected with resistance R511 one end and resistance R512 one end；Single-chip microcomputer U501 SYNC_
OUT terminal mouthful is connected with resistance R510 one end and electric capacity C507 one end, resistance R510 other ends ground connection, the electric capacity C507 other ends and electricity
Hinder R513 one end and the connection of resistance R514 one end；Single-chip microcomputer U501 OUT7_N ports and resistance R515 one end and electric capacity C508 mono-
End connection, resistance R515 other ends ground connection；Single-chip microcomputer U501 OUT7 ports connect with resistance R516 one end and electric capacity C509 one end
Connect, resistance R516 other ends ground connection；Single-chip microcomputer U501 OUT6_N ports are connected with resistance R517 one end and electric capacity C510 one end,
The resistance R517 other ends are grounded；Single-chip microcomputer U501 OUT6 ports are connected with resistance R518 one end and electric capacity C511 one end, resistance
The R518 other ends are grounded.
3. a kind of synchronous acquisition circuit based on multi-channel high-speed ADC according to claim 1, it is characterised in that described
In adc data acquisition module, single-chip microcomputer U52A SYNCINB- ports are connected with electric capacity C1286 one end, single-chip microcomputer U52A's
SYNCINB+ ports are connected with electric capacity C1287 one end, and the electric capacity C1286 other ends pass through resistance R393 and the electric capacity C1287 other ends
Connection, single-chip microcomputer U52A VMON ports connect power supply, and single-chip microcomputer U52A VCM ports are connected with resistance R395 one end, resistance
R395 is connected with electric capacity C912 one end, electric capacity C912 other ends ground connection；Single-chip microcomputer U52A VM_BYP ports and electric capacity C913 mono-
End connection, electric capacity C913 other ends ground connection；Single-chip microcomputer U52A VP_BYP ports and electric capacity C916 one end and resistance R397 one end
Connection, electric capacity C916 other ends ground connection, another termination powers of resistance R397；Single-chip microcomputer U52A RBIAS_EXT ports and resistance
R398 one end is connected, and single-chip microcomputer U52A RBIAS_EXT ports are connected with resistance R399 one end, the resistance R398 other ends and resistance
The R399 other ends are grounded；Single-chip microcomputer U52A RSTB ports are connected with resistance R400 one end, resistance R400 other ends ground connection；Monolithic
Machine U52A PWDN ports are connected with resistance R391 one end, resistance R391 other ends ground connection, single-chip microcomputer U52A IRQ ports and electricity
The connection of R392 one end is hindered, single-chip microcomputer U52A FD ports are connected with resistance R390 one end and resistance R394 one end, and resistance R390 is another
One end is grounded.
4. a kind of synchronous acquisition circuit based on multi-channel high-speed ADC according to claim 1, it is characterised in that described
In synchronised clock control module and adc data acquisition module, resistance R503 is adopted with adc data in the synchronised clock control module
Collect resistance R508 in the CSB ports connection of single-chip microcomputer U52A in module, the synchronised clock control module and gather mould with adc data
Single-chip microcomputer U52A SDIO ports are connected in block, resistance R507 and adc data acquisition module in the synchronised clock control module
Single-chip microcomputer U501 RESRT_N ports and ADC in middle single-chip microcomputer U52A SCLK ports connection, the synchronised clock control module
Single-chip microcomputer U52A RSTB ports are connected in data acquisition module, single-chip microcomputer U501 OUT0 in the synchronised clock control module
Port --- OUT7 ports and the SERDOUT0+ ports of single-chip microcomputer U52A in adc data acquisition module --- SERDOUT7+ ports
Connect one to one, single-chip microcomputer U501 OUT0_N ports --- OUT7_N ports and ADC in the synchronised clock control module
Single-chip microcomputer U52A SERDOUT0- ports --- SERDOUT7- ports connect one to one in data acquisition module, the synchronization
Electric capacity C501 is connected with the CLK- ports of single-chip microcomputer U52A in adc data acquisition module in clock control module, when described synchronous
Electric capacity C502 is connected with the CLK+ ports of single-chip microcomputer U52A in adc data acquisition module in clock control module, the synchronised clock
Resistance R394 is connected with the FD_N ports of single-chip microcomputer U52A in adc data acquisition module in control module, the synchronised clock control
Electric capacity C510 is connected with the SYSREF- ports of single-chip microcomputer U52A in adc data acquisition module in molding block, the synchronised clock control
Electric capacity C511 is connected with the SYSREF+ ports of single-chip microcomputer U52A in adc data acquisition module in molding block, the synchronised clock control
Resistance R511 is connected with the SYNCINB- ports of single-chip microcomputer U52A in adc data acquisition module in molding block, the synchronised clock
Electric capacity C514 is connected with the SYNCINB+ ports of single-chip microcomputer U52A in adc data acquisition module in control module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720178961.0U CN206451166U (en) | 2017-02-27 | 2017-02-27 | A kind of synchronous acquisition circuit based on multi-channel high-speed ADC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720178961.0U CN206451166U (en) | 2017-02-27 | 2017-02-27 | A kind of synchronous acquisition circuit based on multi-channel high-speed ADC |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206451166U true CN206451166U (en) | 2017-08-29 |
Family
ID=59666067
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720178961.0U Active CN206451166U (en) | 2017-02-27 | 2017-02-27 | A kind of synchronous acquisition circuit based on multi-channel high-speed ADC |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206451166U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108134607A (en) * | 2017-12-20 | 2018-06-08 | 北京华航无线电测量研究所 | High-speed AD synchronous acquisition circuit and synchronous method between plate based on JESD204B |
| CN111555764A (en) * | 2020-05-15 | 2020-08-18 | 山东大学 | Radio frequency direct-sampling broadband digital receiver system, method and radio observation system |
| CN111865461A (en) * | 2020-05-25 | 2020-10-30 | 北京无线电测量研究所 | Broadband multichannel digital TR circuit |
| CN112180777A (en) * | 2020-08-24 | 2021-01-05 | 扬州船用电子仪器研究所(中国船舶重工集团公司第七二三研究所) | Multi-channel broadband signal acquisition architecture based on Virtex UltraScale + FPGA |
-
2017
- 2017-02-27 CN CN201720178961.0U patent/CN206451166U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108134607A (en) * | 2017-12-20 | 2018-06-08 | 北京华航无线电测量研究所 | High-speed AD synchronous acquisition circuit and synchronous method between plate based on JESD204B |
| CN108134607B (en) * | 2017-12-20 | 2021-07-02 | 北京华航无线电测量研究所 | High-speed AD synchronous acquisition circuit and method between boards based on JESD204B |
| CN111555764A (en) * | 2020-05-15 | 2020-08-18 | 山东大学 | Radio frequency direct-sampling broadband digital receiver system, method and radio observation system |
| CN111865461A (en) * | 2020-05-25 | 2020-10-30 | 北京无线电测量研究所 | Broadband multichannel digital TR circuit |
| CN111865461B (en) * | 2020-05-25 | 2022-09-23 | 北京无线电测量研究所 | Broadband multichannel digital TR circuit |
| CN112180777A (en) * | 2020-08-24 | 2021-01-05 | 扬州船用电子仪器研究所(中国船舶重工集团公司第七二三研究所) | Multi-channel broadband signal acquisition architecture based on Virtex UltraScale + FPGA |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN206451166U (en) | A kind of synchronous acquisition circuit based on multi-channel high-speed ADC | |
| CN106374927A (en) | Multi-channel high-speed AD system based on FPGA and PowerPC | |
| CN106126473A (en) | A kind of data based on standard AMC platform process plate system | |
| CN204166088U (en) | Local discharge signal harvester | |
| CN205901714U (en) | S frequency channel receiving and dispatching integration treater | |
| CN207586906U (en) | A kind of high speed acquisition multi-channel synchronous system | |
| US20140244889A1 (en) | Pci-e reference clock passive splitter and method thereof | |
| CN210222733U (en) | High-speed digital intermediate frequency acquisition board | |
| CN206431607U (en) | A kind of LCD drive circuit systems | |
| CN206421377U (en) | A kind of multifunctional integrated test card | |
| Zamarreno-Ramos et al. | A ${0.35}~\mu {\rm m} $ Sub-ns Wake-up Time ON-OFF Switchable LVDS Driver-Receiver Chip I/O Pad Pair for Rate-Dependent Power Saving in AER Bit-Serial Links | |
| CN203133718U (en) | Blade server backboard | |
| CN204480239U (en) | A kind of USB turns serial port control circuit | |
| CN207150756U (en) | A kind of MIPI camera signals long haul transmission system | |
| CN205829883U (en) | A kind of multisource video acquisition processing system based on FPGA | |
| CN206039509U (en) | MIPI interface signals level shifting circuit based on homemade FPGA | |
| CN202094873U (en) | Interface structure for serial communication data | |
| CN104008076A (en) | Bus data signal transmitting method and device capable of supporting DVFS | |
| CN104252438B (en) | Digit translation communication interface and method based on the serial line interfaces of RS 422 | |
| CN103560988B (en) | A kind of data link realizes circuit | |
| CN104079309A (en) | Communication device and communication method of K wave band vehicle-mounted receiver | |
| CN207234789U (en) | A kind of Multihost board structures applied in multipath server | |
| CN201159878Y (en) | PCIE card slot adapter | |
| CN206272649U (en) | A kind of miniature digital BBP based on the design of EP4SGX230KF40I4 chips | |
| CN202976319U (en) | Central processing unit (CPU) card and embedded secure access module (ESAM) communication multiplex circuit of three-phase fee control intelligent ammeter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |