CN202094873U - Interface structure for serial communication data - Google Patents
Interface structure for serial communication data Download PDFInfo
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- CN202094873U CN202094873U CN2010205384819U CN201020538481U CN202094873U CN 202094873 U CN202094873 U CN 202094873U CN 2010205384819 U CN2010205384819 U CN 2010205384819U CN 201020538481 U CN201020538481 U CN 201020538481U CN 202094873 U CN202094873 U CN 202094873U
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Abstract
A high-speed interface structure for serial communication data with low power consumption abandons arrangement of multipath sampling and arbitration circuits and pre-samples content data according to original clock frequency signals CLK extracted from input data and by using the technology of combining asynchronization of single-path sampling and multi-clock automatic synchronization. After the per-sampled data and a system clock are synchronized, a CLK1 is fed back and regulated to a single-path sampling module, the content data are sampled precisely so that the results and a target clock CLK2 are synchronic, combination of clock domain asynchronization and synchronization is realized and efficiency is improved. Under the condition that an application specific integrated circuit ASIC is similar in area, the power consumption of a physical layer (PHY) can be decreased by higher than 70%, which surpasses the reached level of an existing international realization framework. Interference of high-speed signals to other circuits inside an ASIC chip is reduced, the requirement for layout and wiring of inside modules of the chip is lowered, energy is saved and production cost is reduced.
Description
Technical field
The utility model relates to a kind of integrated circuit (IC) design to be realized, particularly a kind of interface structure of serial communication data of high-speed low-power-consumption.
Background technology
Develop rapidly along with modern digital communication, the interconnection technique of speed more than 5Gbit/s just obtaining application more and more widely, as very short distance optical interconnection (VSR), SATA high-speed transfer standard, Express PCI2.0 and USB3.0 agreement etc. between interconnected between communication system High speed rear panel, communication system backboard, local area network (LAN), communication equipment.These mutual contact modes often need the integrated circuit support of high speed, low-power consumption, cheapness, to reach higher performance.
Above-mentioned high-speed digital communication system generally adopts serial mode transmission data, but special clock passage is not provided, and must extract clock signal from data-signal, and it is separated with content-data.In optical fiber telecommunications system, SATA high speed transmission system, Express PCI 2.0 and USB 3.0 systems, has similar situation.
Require the response time quick because high-speed data receives, in existing high-speed data reception framework as shown in Figure 1, use the data-signal that does not have corresponding frequency spectrum component and non-return-to-zero coding (NRZI) on the message transmission rate frequency usually as the input data.But in this kind framework, the shake of recovered clock is bigger, and system will obtain stable data in view of the above must pass through the multichannel over-sampling, and the logic determines of carrying out of arbitration circuit is handled.
Particularly, produce the required clock signal of system of each module in the reception framework by phase-locked loop (PLL); Produce the multichannel over-sampling clock of its phase place such as time-delay such as grade again by delay phase-locked loop (DLL), and export the multichannel over-sampling circuit to.
The multichannel over-sampling circuit mainly solves clock and the jitter problem of importing data.Sampling is passed by in general use four road or eight, makes its receiver correctly to carry out data extract from the input data.Usually, pass by sampling clock at each, receiver proposes one group of data from the input data, and is transported in the independent clock zone; All multichannel datas that extracts, deliver to the FIFO memory wait respectively and further handle again.
Arbitration circuit is judged that one of them is the correct data of corresponding system clock, and this synchrodata is exported to the outside by data-interface according to the multichannel data output that the multichannel over-sampling circuit is produced.
Above-mentioned existing high-speed data receives in the framework, the system configuration complexity; When adopting high-frequency clock to handle whole over-sampling circuit, the over-sampling way of use is many more, and the energy that circuit consumed is just many more; Application-specific integrated circuit (ASIC) (ASIC) realizes that shared chip area is big more, and cost is high more.This high speed of communicating by letter with modern digital, low-power consumption, cheap requirement do not conform to.
Universal USB 2.0 physical layers (PHY) of for example using framework like this to realize, when high speed operation, can consume the electric current of about 60mA, little for general application problem, but to being a huge thermal source as integrated image inductor CIS, it will have a strong impact on the picture quality that image inductor is captured.
The utility model content
The purpose of this utility model provides a kind of interface structure of serial communication data, can be synchronous fully with receiving data and system clock, under the close situation of the realization area of application-specific integrated circuit ASIC, reduce the power consumption of high-speed data recovery system, and reduce the difficulty that the ASIC rear end relates to timing closure.
In order to achieve the above object, the technical solution of the utility model provides a kind of interface structure of serial communication data, comprises the single channel sampling module, respectively the clock and data recovery module that is connected with described single channel sampling module, the automatic synchronous processing module of clock for a long time;
Described clock and data recovery module receives the input data, wherein content-data and clock frequency signal CLK is separated, and export described single channel sampling module respectively to;
Described single channel sampling module carries out pre-sampling processing according to clock frequency signal CLK to content-data, and exports pre-sampled data for a long time that the automatic synchronous processing module of clock carries out Synchronous Processing to;
Described single channel sampling module is also adjusted clock CLK1 according to a road of the automatic synchronous processing module feedback of described clock for a long time, and described content-data is accurately sampled.
The interface structure of described serial communication data also comprises the phase-locked loop that is connected respectively with the input clock of described input data and outside;
Described phase-locked loop is realized the frequency multiplication of described input clock by locking phase, obtains and system clock described input data sync, that have system's highest frequency;
Described system clock exports described clock and data recovery module, single channel sampling module and the automatic processing module of clock for a long time respectively to.
Described clock and data recovery module is according to described system clock, separates described input data, obtains wherein content-data and clock frequency signal CLK;
Described clock frequency signal CLK has the identical system's highest frequency of system clock with described phase-locked loop output.
The interface structure of described serial communication data also comprises the data interface module that is connected with the automatic synchronous processing module of described clock for a long time;
The automatic synchronous processing module of described clock for a long time carries out Synchronous Processing according to described pre-sampled data and system clock, obtains feeding back to the described adjustment clock CLK1 of single channel sampling module, also obtains one tunnel target clock CLK2 and exports described data interface module to.
The low speed fractional frequency signal that described adjustment clock CLK1 that the automatic synchronous processing module of described clock is for a long time exported respectively and target clock CLK2 are described system clock.
Described single channel sampling module also is connected with described data interface module; Described single channel sampling module obtains and the synchronous accurate sampled data of described target clock CLK2, and exports described data interface module to according to adjusting clock CLK1.
Described accurate sampled data has the settling time and the retention time in a corresponding system maximum clock cycle at least.
Described system is the cycle of described system clock in the maximum clock cycle, the inverse of promptly described system highest frequency.
Described data interface module is sampled to the accurate sampled data of described single channel sampling module output once more according to target clock CLK2, obtains to the outside dateout of carrying of described receiving interface framework.
Compared with prior art, the interface structure of serial communication data described in the utility model, abandoned the setting of multichannel over-sampling and arbitration circuit, its advantage is: the utility model uses the asynchronous technique of single channel sampling, the technology that combines with the automatic locking phase of clock for a long time, according to clock and data recovery module (CDR) output, by original clock frequency signal CLK that the input extracting data goes out, content-data is sampled in advance; By the automatic synchronous processing module of clock for a long time pre-sampled data and system clock are carried out synchronously, and feedback adjusting clock CLK1 is to the single channel sampling module, further content-data is accurately sampled, obtain complete synchronous accurate sampled data with target clock CLK2, realize asynchronous with synchronous the combining of clock zone, improved efficient.
The utility model is owing to used the asynchronous and synchronous technology that combines of above-mentioned clock zone, realize under the similar situation of area at application-specific integrated circuit ASIC, the power consumption that physical layer (PHY) realizes lowers greater than 70%, surpassed the level that existing in the world realization framework is reached, reduce the interference of high speed signal again dramatically to other circuit of asic chip inside, reduce the layout (FloorPlan) of chip internal module and the requirement of wiring (Route), save energy consumption, also reduced production cost.
Description of drawings
Fig. 1 is the schematic diagram that existing general high-speed data receives framework.
Fig. 2 is the schematic diagram of the interface structure of the utility model serial communication data.
Embodiment
The embodiment of the interface structure of the utility model serial communication data is described below in conjunction with accompanying drawing 2.
At first, the input clock that receives from the outside produces the system clock with system's highest frequency by phase-locked loop (PLL) 10.This phase-locked loop (PLL) 10 is phase feedback automatic control modules, has the function of clock synchronization and phase locking, and it realizes the input clock frequency multiplication by locking phase, obtains and import the described system clock of data sync.System clock synchronously exports clock and data recovery module (CDR) 20 in the utility model, single channel sampling module 30 and the automatic processing module of clock for a long time respectively to.
Above-mentioned input data also are connected with the clock and data recovery module (CDR) 20 of open loop, (CDR) 20 is according to system clock for this clock and data recovery module, content-data and clock frequency signal CLK in the input data are separated, and export single channel sampling module 30 respectively to.This isolated clock frequency signal CLK has the identical system's highest frequency of system clock with phase-locked loop (PLL) 10 outputs, but the phase place of clock frequency signal CLK changes with the input data variation that is input to clock and data recovery module (CDR) 20.According to this clock frequency signal CLK, 30 pairs of described content-datas of single channel sampling module are sampled in advance, and export pre-sampled data and arrive the automatic synchronous processing module 40 of clock for a long time.
According to system clock, the pre-sampled data that the automatic synchronous processing module 40 of described clock for a long time will receive is carried out Synchronous Processing, and feeds back one the tunnel and adjust clock CLK1 to single channel sampling module 30, also exports one tunnel target clock CLK2 simultaneously to data interface module 50.The clock CLK1 of this two-way output and CLK2 are for a long time, and the automatic synchronous processing module 40 of clock does not have positive connection with respect to the low speed fractional frequency signal of described system clock but adjust between clock CLK1 and the target clock CLK2.
Described single channel sampling module 30 is accurately sampled to the content-data of clock and data recovery module (CDR) 20 outputs once more, and is also exported the result to data interface module 50 according to adjusting clock CLK1.
Because the automatic synchronous processing module 40 of clock can carry out automatically to each clock of importing its inside synchronously for a long time, wherein, the data in each high-frequency clock territory can be synchronized with low-speed clock automatically; In the low-speed clock territory, make high-speed data have the settling time (setup time) and the retention time (hold time) in a corresponding high-frequency clock cycle at least.
According to described in the utility model, the high-frequency clock territory comprises the clock frequency signal CLK of system clock and clock and data recovery module (CDR) 20 outputs, and low-speed clock comprises adjustment clock CLK1 and target clock CLK2.High-speed data comprises the described content-data of clock and data recovery module (CDR) 20 outputs; And pre-sampled data and accurately sampled data differ and be decided to be high-speed data.
Therefore, through pre-sampling, Synchronous Processing, feedback with after accurately sampling, data interface module 50 final accurate sampled datas that receive and target clock CLK2 are fully synchronous, when this accurate sampled data is high-speed data, wherein comprise the settling time and the retention time in a corresponding system maximum clock cycle at least.Because clock frequency signal CLK can constantly change according to the input data, described system promptly is meant the cycle of described system clock the maximum clock cycle, is specially the inverse of system's highest frequency, is a fixed value.
Data interface module 50 is sampled once more to the accurate sampled data of described single channel sampling module 30 outputs under the effect of target clock CLK2, obtains final dateout.
For example, interface structure with the above-mentioned serial communication data of the utility model, be applied under the UTMI agreement of USB2.0, during as the receiving interface of physical layer (PHY): the current sinking of UTMI is 15mA under 0.13um CMOS technology, and the area of its application-specific integrated circuit ASIC is 0.42 square millimeter.
And if adopt high-speed data general in the background technology to receive framework, the consumed current of UTMI is 60mA under 0.13um CMOS technology, and the ASIC area is 0.36 square millimeter.
As seen, under the close situation of the realization area of application-specific integrated circuit ASIC, the utility model can reduce the power consumption 75% of high-speed data recovery system.
In sum, abandoned the setting of multichannel over-sampling and arbitration circuit in the prior art, the interface structure of serial communication data described in the utility model, use the asynchronous technique of single channel sampling, the technology that combines with the automatic locking phase of clock for a long time, according to clock and data recovery module (CDR) 20 output, by original clock frequency signal CLK that the input extracting data goes out, content-data is sampled in advance; By 40 pairs of pre-sampled datas of the automatic synchronous processing module of clock and system clock carry out synchronously for a long time, and feedback adjusting clock CLK1 is to single channel sampling module 30, further content-data is accurately sampled, obtain complete synchronous accurate sampled data with target clock CLK2, realize asynchronous with synchronous the combining of clock zone, improved efficient.
The utility model is owing to used the asynchronous and synchronous technology that combines of above-mentioned clock zone, realize under the similar situation of area at application-specific integrated circuit ASIC, the power consumption that physical layer (PHY) realizes lowers greater than 70%, surpassed the level that existing in the world realization framework is reached, reduce the interference of high speed signal again dramatically to other circuit of asic chip inside, reduce the layout (FloorPlan) of chip internal module and the requirement of wiring (Route), save energy consumption, also reduced production cost.
Although content of the present utility model has been done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to restriction of the present utility model.After those skilled in the art have read foregoing, for multiple modification of the present utility model with to substitute all will be conspicuous.Therefore, protection range of the present utility model should be limited to the appended claims.
Claims (5)
1. the interface structure of serial communication data is characterized in that, comprises single channel sampling module (30), respectively the clock and data recovery module (20) that is connected with described single channel sampling module (30), the automatic synchronous processing module of clock (40) for a long time;
Described clock and data recovery module (20) receives the input data, wherein content-data and clock frequency signal CLK is separated, and export described single channel sampling module (30) respectively to;
Described single channel sampling module (30) carries out pre-sampling processing according to clock frequency signal CLK to content-data, and exports pre-sampled data for a long time that the automatic synchronous processing module of clock (40) carries out Synchronous Processing to;
Described single channel sampling module (30) also receives a road of the automatic synchronous processing module of described clock for a long time (40) feedback output and adjusts clock CLK1, described content-data is carried out accurate sampling processing, and obtain accurate sampled data.
2. the interface structure of serial communication data according to claim 1 is characterized in that, also comprises the phase-locked loop (10) that is connected with outside input clock, and it carries out phase locking handles, and exports the frequency multiplication of described input clock;
Described phase-locked loop (10) also is connected with described input data, and system clock output and described input data sync, that have system's highest frequency;
Described system clock exports described clock and data recovery module (20), single channel sampling module (30) and the automatic processing module of clock for a long time respectively to.
3. as the interface structure of serial communication data as described in the claim 2, it is characterized in that, also comprise the data interface module (50) that is connected with the automatic synchronous processing module of described clock for a long time (40);
The automatic synchronous processing module of described clock for a long time (40) carries out Synchronous Processing according to described pre-sampled data and system clock, obtain feeding back to the described adjustment clock CLK1 of low speed fractional frequency signal of the described system clock of conduct of single channel sampling module (30), also obtain exporting described data interface module (50) to as the target clock CLK2 of another road low speed fractional frequency signal of described system clock.
4. as the interface structure of serial communication data as described in the claim 3, it is characterized in that described single channel sampling module (30) also is connected with described data interface module (50); Described single channel sampling module (30) is according to adjusting clock CLK1, obtain the accurate sampled data with the settling time and the retention time in described target clock CLK2 cycle synchronous, that comprise at least one corresponding described system clock, and export described data interface module (50) to.
5. as the interface structure of serial communication data as described in the claim 4, it is characterized in that, described data interface module (50) is according to target clock CLK2, accurate sampled data to described single channel sampling module (30) output is sampled once more, obtains to the outside dateout of carrying of described receiving interface framework.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205384819U CN202094873U (en) | 2010-09-21 | 2010-09-21 | Interface structure for serial communication data |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010205384819U CN202094873U (en) | 2010-09-21 | 2010-09-21 | Interface structure for serial communication data |
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| CN202094873U true CN202094873U (en) | 2011-12-28 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104253620A (en) * | 2014-09-17 | 2014-12-31 | 清华大学 | Novel transmitter for high-speed serial port |
| CN108449086A (en) * | 2018-02-27 | 2018-08-24 | 灿芯创智微电子技术（北京）有限公司 | A kind of multi-channel high-speed universal serial bus transmitting terminal parallel port synchronous method, circuit and chip |
-
2010
- 2010-09-21 CN CN2010205384819U patent/CN202094873U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104253620A (en) * | 2014-09-17 | 2014-12-31 | 清华大学 | Novel transmitter for high-speed serial port |
| CN104253620B (en) * | 2014-09-17 | 2016-03-30 | 清华大学 | A kind of novel HSSI High-Speed Serial Interface transmitter |
| CN108449086A (en) * | 2018-02-27 | 2018-08-24 | 灿芯创智微电子技术（北京）有限公司 | A kind of multi-channel high-speed universal serial bus transmitting terminal parallel port synchronous method, circuit and chip |
| CN108449086B (en) * | 2018-02-27 | 2021-11-16 | 灿芯创智微电子技术（北京）有限公司 | Method and circuit for synchronizing parallel ports of multi-channel high-speed serial bus sending end |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20111228 Termination date: 20140921 |
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| EXPY | Termination of patent right or utility model |