CN204362064U - Data sink, data receiving system and data transmission system - Google Patents
Data sink, data receiving system and data transmission system Download PDFInfo
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- CN204362064U CN204362064U CN201520023308.8U CN201520023308U CN204362064U CN 204362064 U CN204362064 U CN 204362064U CN 201520023308 U CN201520023308 U CN 201520023308U CN 204362064 U CN204362064 U CN 204362064U
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Abstract
The utility model provides a kind of data sink, data receiving system and data transmission system.Described data sink comprises: sampling clock produces circuit, and it produces multiple sampled clock signals with identical frequency and predetermined phase difference according to recovering reference clock signal; Serial data sample circuit, it utilizes described multiple sampled clock signal sampled data signal transmission to obtain the reception data of a series of serial; Clock selection circuit, it selects a suitable sampled clock signal as serioparallel exchange clock signal according to clock signal of system from described multiple sampled clock signal; Serial-parallel conversion circuit, the reception data of the serial from described serial data sample circuit are converted to parallel reception data according to described serioparallel exchange clock signal by it.Due to select from described multiple sampled clock signal according to clock signal of system the most suitable one as serioparallel exchange clock signal, the synchronism between data that each data sink receives can be improved.
Description
[technical field]
The utility model relates to field of data transmission, particularly a kind of data sink, data receiving system and data transmission system.
[background technology]
Along with the development of electron trade technology, particularly in the development of coffret, IEEE1284 is replaced by USB (Universal Serial Bus) interface, PATA (Parallel Advanced Technology Attachment) is replaced by SATA (Serial Advanced Technology Attachment), PCI (Peripheral Component Interconnect) replace by PCI-Express, none speed all demonstrating Traditional parallel interface has reached a bottleneck, the substitute is speed serial line interface faster, so SerDes (SERDES is the abbreviation of SERializer (serializer)/DESerializer (the deserializer)) technology being originally used for optical fiber communication becomes the main flow for HSSI High-Speed Serial Interface.Serial line interface mainly applies differential signal transmission technology, has low in energy consumption, by force anti-interference, fireballing feature, and the maximum transmission rate of serial line interface can reach more than 10Gbps in theory.
Fig. 1 shows existing a kind of SerDes data transmission system, and it comprises data source 100, clock generator 200, first data sink 310, second data sink 320, the 3rd data sink 330.Each data sink can be called as a data receiving channel, and therefore this data transmission system also can be called as multi-channel Transmission System, multiple channel reception to data between need phase mutually synchronization.
Described clock generator 200 produces reference clock signal ref_clk, and this reference clock signal ref_clk is supplied to data source 100.Phase-locked loop pll in described data source 100 produces described tranmitting data register signal according to this reference clock signal, and send after data to be transmitted being modulated based on tranmitting data register signal, the output signal transmission RXP/N sent is provided to each data sink, wherein signal RXP/N_1 is provided to the first data sink, signal RXP/N_2 is provided to the second data sink, and signal RXP/N_3 is provided to the 3rd data sink.This reference clock signal is also provided to each data sink by as recovery reference clock signal Rec_ref_clk, wherein Rec_ref_clk_1 is supplied to data sink 310, Rec_ref_clk_2 is supplied to data sink 320, Rec_ref_clk_3 and is supplied to data sink 330.This reference clock signal ref_clk is provided to each data sink by as clock signal of system sys_clk after certain delay of delayer.
Each data sink comprises data receipt unit SerDes RX and packet synchronisation circuit.Described data receipt unit SerDes RX produces multiple sampled clock signal based on the recovery reference clock signal Rec_ref_clk received, the data transfer signal utilizing described multiple sampled clock signal to sample to be sent by data source 100 obtains the reception data of a series of serial, and the reception data of described serial are converted to parallel reception data.Described packet synchronisation circuit carries out packet synchronisation based on the reception data that described clock signal of system is parallel.
Current SerDes multi-channel data synchronously realizes by data buffer usually.Its usually utilizes unnecessary synchronizing information in transmission data to align the transfer of data of each passage.This method of synchronization increases the time delay of transfer of data, and adds the complexity of chip or system, also reduces the effective speed of transfer of data to a certain extent.In addition, the change over clock of the serioparallel exchange of traditional SerDes data sink is fixing, can not effectively by intervening the delay of transfer of data.Because the change of the clock of phase-locked loop pll and the clock of recovery is random, so the data time difference of every two passages cannot be guaranteed.
As shown in Figure 2, the sequential chart of the serial data that obtains of the data receipt unit of its each data sink illustrated in Fig. 1 and recovered clock signal Rec_clk.As shown in Figure 2, the data RX_data_1 that the data receipt unit of the first data sink obtains is 0123,0123,, and the data RX_data_2 that the data receipt unit of the second data sink obtains is 012,3012,3012,3012 ..., and the data RX_data_3 that the data receipt unit of the 3rd data sink obtains is 01,2301,2301,2301 ...Difference 1 between the data RX_data_2 that the data receipt unit of the data RX_data_1 that the data receipt unit of the first data sink obtains and the second data sink obtains, difference 1 between the data RX_data_3 that the data receipt unit of the data RX_data_2 that the data receipt unit of the second data sink obtains and the 3rd data sink obtains, difference 2 between the data RX_data_3 that the data receipt unit of the data RX_data_1 that the data receipt unit of the first data sink obtains and the 3rd data sink obtains.
Therefore, be necessary to provide a kind of technical scheme of improvement to overcome the problems referred to above.
[the utility model content]
One of the purpose of this utility model is to provide a kind of data sink, and it can improve the data syn-chronization received in its data received and other passage.
Two of the purpose of this utility model is to provide a kind of data receiving system, and it has multiple parallel data receiving channel, and can improve the synchronism between data that each data receiving channel receives.
Three of the purpose of this utility model is to provide a kind of data transmission system, and it has multiple parallel data receiving channel, and can improve the synchronism between data that each data receiving channel receives.
In order to solve the problem, according to an aspect of the present utility model, the utility model provides a kind of data sink, it comprises: sampling clock produces circuit, it produces multiple sampled clock signal according to the recovery reference clock signal received, and has identical frequency and predetermined phase difference between each sampled clock signal; Serial data sample circuit, its data transfer signal utilizing described multiple sampled clock signal to sample to be sent by data source obtains the reception data of a series of serial; Clock selection circuit, it selects a suitable sampled clock signal as serioparallel exchange clock signal according to the clock signal of system that receives from described multiple sampled clock signal; Serial-parallel conversion circuit, the reception data of the serial from described serial data sample circuit are converted to parallel reception data according to described serioparallel exchange clock signal by it.
Further, described clock selection circuit comprises: select logical circuit, described multiple sampled clock signal and the clock signal of system received contrast by it, find the immediate sampled clock signal in the hopping edge of its hopping edge and described clock signal of system, and export the gating signal of the immediate sampled clock signal in hopping edge of this hopping edge of gating and described clock signal of system; Clock gate, it receives multiple sampled clock signal, and according to select logical circuit export gating signal gating and corresponding sampled clock signal as serioparallel exchange clock signal.
Further, described multiple sampled clock signal comprise multiple justified sampled clock signal and with described multiple justified margin sampled clock signal, the phase difference of each justified sampled clock signal and adjacent justified margin sampled clock signal is that predetermined phase is poor, the phase difference of each justified margin sampled clock signal and adjacent justified margin sampled clock signal is that predetermined phase is poor, described selection logical circuit is by described multiple justified sampled clock signal, described multiple justified margin sampled clock signal and the clock signal of system received contrast, find the immediate justified sampled clock signal in the hopping edge of its hopping edge and described clock signal of system, and the gating signal of the immediate justified sampled clock signal in the hopping edge exporting this hopping edge of gating and described clock signal of system, described clock gate receives multiple justified sampled clock signal, and according to justified sampled clock signal corresponding to gating signal gating selecting logical circuit to export as serioparallel exchange clock signal.
Further, in selection logical circuit, utilize each sampled clock signal to carry out sampling to described clock signal of system and obtain multiple system clock synchronization signal, two that find phase difference to undergo mutation adjacent system clock synchronization signals, two sampled clock signals that two that determine that phase difference undergos mutation adjacent system clock synchronization signals are corresponding, the hopping edge of the justified sampled clock signal in two sampled clock signals determined and the hopping edge of described clock signal of system closest.
Further, described hopping edge is rising edge.
Further, described selection logical circuit also receives reset trigger signal, when reset trigger signal becomes effective at every turn, the immediate sampled clock signal in hopping edge that described selection logical circuit searches once its hopping edge and described clock signal of system again, and export corresponding gating signal.
Further, described selection logical circuit also exports reset synchronization signal to described serial-parallel conversion circuit, synchronous with described clock signal of system to ensure the parallel reception data that described serial-parallel conversion circuit exports.
Further, data sink also comprises: packet synchronisation circuit, and it receives the parallel reception data from described serial-parallel conversion circuit, and carries out packet synchronisation based on described clock signal of system to parallel reception data.
According to another aspect of the present utility model, the utility model provides a kind of data receiving system, it comprises: multiple data sink, and each data sink receives the data transfer signal sent from same data source, receives and recovers reference clock signal and clock signal of system.Each data sink comprises: sampling clock produces circuit, and it produces multiple sampled clock signal according to the recovery reference clock signal received, and has identical frequency and predetermined phase difference between each sampled clock signal; Serial data sample circuit, its data transfer signal utilizing described multiple sampled clock signal to sample to be sent by data source obtains the reception data of a series of serial; Clock selection circuit, it selects a suitable sampled clock signal as serioparallel exchange clock signal according to the clock signal of system that receives from described multiple sampled clock signal; Serial-parallel conversion circuit, the reception data of the serial from described serial data sample circuit are converted to parallel reception data according to described serioparallel exchange clock signal by it.
According to another aspect of the present utility model, the utility model provides a kind of data transmission system, and it comprises: data source, obtains data transfer signal and send this data transfer signal based on tranmitting data register signal after data to be transmitted being modulated; The data receiving system above mentioned, each data sink receives the data transfer signal sent from described data source.
Further, described data transmission system also comprises: clock generator, it produces reference clock signal, this reference clock signal is provided to data source, described data source produces described tranmitting data register signal according to this reference clock signal, this reference clock signal is also provided to each data sink by as recovery reference clock signal, and this reference clock signal is provided to each data sink by as clock signal of system after certain delay.
Compared with prior art, in the utility model, according to the clock signal of system received select from described multiple sampled clock signal the most suitable one as serioparallel exchange clock signal, instead of in the fixing or random described multiple sampled clock signal of employing one is as serioparallel exchange clock signal, the synchronism between data that each data sink receives can be improved like this.
[accompanying drawing explanation]
In order to be illustrated more clearly in the technical scheme of the utility model embodiment, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only embodiments more of the present utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.Wherein:
Fig. 1 shows existing a kind of SerDes data transmission system;
The sequential chart of the serial data that each data receipt unit of each data sink that Fig. 2 has gone out in Fig. 1 obtains and recovered clock signal Rec_clk;
Fig. 3 is the data transmission system structural representation in one embodiment in the utility model;
Fig. 4 is the data receipt unit structural representation in one embodiment in Fig. 3;
Fig. 5 is the fundamental diagram of the serial data sample circuit in Fig. 4;
Fig. 6 is the fundamental diagram of the selection logical circuit in Fig. 4.
[embodiment]
For enabling above-mentioned purpose of the present utility model, feature and advantage become apparent more, are described in further detail the utility model below in conjunction with the drawings and specific embodiments.
Fig. 3 is data transmission system 30 structural representation in one embodiment in the utility model.Described data transmission system 30 comprises data source 400, clock generator 500, first data sink 610, second data sink 620, the 3rd data sink 630.In this example, show three data sinks, in fact can be two, a four or more data sink, be introduced for three data sinks below.Each data sink can be called as a data receiving channel, and therefore this data transmission system also can be called as multi-channel data receiving system, multiple channel reception to data between need phase mutually synchronization.
Described clock generator 500 produces reference clock signal ref_clk, and this reference clock signal ref_clk is supplied to data source 400.This reference clock signal ref_clk is also provided to each data sink by as recovery reference clock signal Rec_ref_clk, wherein Rec_ref_clk_1 is supplied to data sink 610, Rec_ref_clk_2 is supplied to data sink 620, Rec_ref_clk_3 and is supplied to data sink 630.This reference clock signal ref_clk is provided to each data sink 610,620 and 630 after certain delay of delayer as clock signal of system sys_clk.In other embodiments, reference clock signal ref_clk also can be provided in other manners, recover reference clock signal Rec_ref_clk and clock signal of system sys_clk.
Phase-locked loop pll in described data source 400 produces described tranmitting data register signal according to this reference clock signal ref_clk, and based on tranmitting data register signal, data to be transmitted is carried out modulating rear formation data transfer signal and being sent by this data transfer signal, the data transfer signal RXP/N sent is provided to each data sink, wherein signal RXP/N_1 is provided to the first data sink 610, signal RXP/N_2 is provided to the second data sink 620, and signal RXP/N_3 is provided to the 3rd data sink 630.
Each data sink comprises data receipt unit SerDes RX and packet synchronisation circuit.Described data receipt unit SerDes RX produces multiple sampled clock signal based on the recovery reference clock signal Rec_ref_clk received, the data transfer signal utilizing described multiple sampled clock signal to sample to be sent by data source 400 obtains the reception data of a series of serial, from described multiple sampled clock signal, select a suitable sampled clock signal as serioparallel exchange clock signal based on the clock signal of system sys_clk received, based on described serioparallel exchange clock signal, the reception data of described serial are converted to parallel reception data.Because the serioparallel exchange clock signal in each data order unit can carry out adaptive adjustment according to the difference of the delay of the clock signal of system sys_clk of different data sinks, the synchronism of the parallel reception data obtained can be improved like this.
Described packet synchronisation circuit carries out packet synchronisation based on the reception data that described clock signal of system is parallel.In one embodiment, when the packet synchronisation circuit in first data sink 610 exports a packet, ensure that the packet synchronisation circuit in second data sink 620 and the 3rd data sink 630 is exporting same packet.Synchronous based on described clock signal of system sys_clk, the same packet of output that each packet synchronisation circuit can be synchronous.Each packet can N bit data, and such as N can be 20.In one embodiment, described packet synchronisation circuit is one group of d type flip flop, the input D of each d type flip flop is connected with a data bit in parallel reception data, and its clock end CLK meets described clock signal of system sys_clk, and its output Q exports the parallel data after packet synchronisation.
Fig. 4 is the data receipt unit structural representation in one embodiment in Fig. 3.Described data receipt unit comprises sampling clock and produces circuit (not shown), serial data sample circuit 602, clock selection circuit 603 and serial-parallel conversion circuit 605.
Described sampling clock produces circuit and produces multiple sampled clock signal according to the recovery reference clock signal Rec_ref_clk received.Such as CK0-CK7 totally 8 sampled clock signals, have identical frequency and predetermined phase difference between each sampled clock signal, such as phase difference is 45 degree.The data transfer signal that described serial data sample circuit 602 utilizes described multiple sampled clock signal to sample to be sent by data source obtains the reception data of a series of serial.Described clock selection circuit 603 selects a suitable sampled clock signal as serioparallel exchange clock signal C K_sel according to the clock signal of system sys_clk received from described multiple sampled clock signal.The reception data of the serial from described serial data sample circuit 602 are converted to parallel reception data according to described serioparallel exchange clock signal C K_sel by described serial-parallel conversion circuit 605.
As shown in Figure 4, described clock selection circuit 603 comprises clock gate 606 and selects logical circuit 607.Logical circuit 607 is selected described multiple sampled clock signal CK0-CK7 and the clock signal of system sys_clk received to be contrasted, find the immediate sampled clock signal in the hopping edge of its hopping edge and described clock signal of system, and export the gating signal of the immediate sampled clock signal in hopping edge of this hopping edge of gating and described clock signal of system sys_clk.Described clock gate 606 receives multiple sampled clock signal, and according to select logical circuit 607 export gating signal gating and corresponding sampled clock signal as serioparallel exchange clock signal C K_sel.
In one embodiment, described multiple sampled clock signal (such as CK0-CK7) comprise multiple justified sampled clock signal (such as CK0, CK2, CK4, CK6) and with described multiple justified margin sampled clock signal (such as CK1, CK3, CK5, CK7).The phase difference of each justified sampled clock signal and adjacent justified margin sampled clock signal is that predetermined phase is poor, and the phase difference of each justified margin sampled clock signal and adjacent justified margin sampled clock signal is that predetermined phase is poor.Described multiple justified sampled clock signal, described multiple justified margin sampled clock signal and the clock signal of system sys_clk that receives contrast by described selection logical circuit 607, find the immediate justified sampled clock signal in the hopping edge of its hopping edge and described clock signal of system, and the gating signal of the immediate justified sampled clock signal in the hopping edge exporting this hopping edge of gating and described clock signal of system.Described clock gate 606 receives multiple justified sampled clock signal, and according to justified sampled clock signal corresponding to gating signal gating selecting logical circuit to export as serioparallel exchange clock signal.
In one embodiment, the tranmitting data register signal in described data source 400 is 2.4GHz, and reference clock signal ref_clk, clock signal of system sys_clk and recovery reference clock signal Rec_ref_clk are 120MHz.Described sampled clock signal is 600MHz, total CK0-CK7 eight sampled clock signals.It is understood that in other embodiments, the frequency of described sampled clock signal, described clock signal of system sys_clk and described recovery reference clock signal Rec_ref_clk all can be changed.
Fig. 5 is the fundamental diagram of the serial data sample circuit in Fig. 4.After dynamically locking, clock CK0, CK2, CK4, CK6 align in the middle of the data that receive, it is also referred to as justified sampled clock signal, and clock CK1, CK3, CK5, CK7 align the data edge received, and it is also referred to as justified margin sampled clock signal.The phase difference of 45 degree is differed between two often adjacent sampled clock signals.Like this, utilize in clock CK0, CK2, CK4, CK6 each can both sample and obtain a data, they can obtain the data of 4 Bits Serial altogether.After 5 clock cycle, 20 Bits Serial data can be obtained.
Fig. 6 is the fundamental diagram of the selection logical circuit 607 in Fig. 4.Sampled clock signal CK0-CK7 carries out sampling to described clock signal of system sys_clk and obtains system clock synchronization signal sys_clk_sync<0>, sys_clk_sync<1>, sys_clk_sync<2>, sys_clk_sync<3>,, sys_clk_sync<7>.Can find according to Fig. 6, larger sudden change is had from the phase difference between system clock synchronization signal sys_clk_sync<2> and system clock synchronization signal sys_clk_sync<3>, that is, the rising edge of clock signal of system sys_clk is between sampled clock signal CK2 and CK3.That is, be justified sampled clock signal CK2 with the immediate justified sampled clock signal of rising edge of its rising edge and described clock signal of system.Next, described selection logical circuit 607 can send the gating signal of gating justified sampled clock signal CK2.Described clock gate 606 using justified sampled clock signal CK2 described in gating as serioparallel exchange clock signal C K_sel.
Because the clock gate 606 in each data sink selects the immediate justified sampled clock signal of the rising edge of its rising edge and clock signal of system sys_clk as serioparallel exchange clock signal C K_sel, make the serial-parallel conversion circuit 605 of each data sink can export synchronous parallel data like this.Thus the transmission data interlock that can control any two data sinks to a data bit deviation within.
As shown in Figure 4, described selection logical circuit 607 also receives reset trigger signal rsn, when reset trigger signal rsn becomes effective at every turn, described selection logical circuit 607 searches once the immediate sampled clock signal in hopping edge of its hopping edge and described clock signal of system sys_clk again, and exports corresponding gating signal.When reset trigger signal rsn remains effective, this gating signal of output that described selection logical circuit 607 continues, the same sampled clock signal of output making described clock gate 606 lasting is as serioparallel exchange clock.Described selection logical circuit 607 also exports reset synchronization signal retn_sysn to described serial-parallel conversion circuit 605, to ensure the parallel reception data sys_clk synchronous with described clock signal of system that described serial-parallel conversion circuit 605 exports.
In the utility model, " connection ", be connected, word that " companys ", the expression such as " connecing " are electrical connected, if no special instructions, then represent direct or indirect electric connection, be connected such as through after a resistance, a logical circuit or a functional circuit, etc.
It is pointed out that the scope be familiar with person skilled in art and any change that embodiment of the present utility model is done all do not departed to claims of the present utility model.Correspondingly, the scope of claim of the present utility model is also not limited only to previous embodiment.
Claims (10)
1. a data sink, is characterized in that, it comprises:
Sampling clock produces circuit, and it produces multiple sampled clock signal according to the recovery reference clock signal received, and has identical frequency and predetermined phase difference between each sampled clock signal;
Serial data sample circuit, its data transfer signal utilizing described multiple sampled clock signal to sample to be sent by data source obtains the reception data of a series of serial;
Clock selection circuit, it selects a suitable sampled clock signal as serioparallel exchange clock signal according to the clock signal of system that receives from described multiple sampled clock signal;
Serial-parallel conversion circuit, the reception data of the serial from described serial data sample circuit are converted to parallel reception data according to described serioparallel exchange clock signal by it.
2. data sink according to claim 1, is characterized in that, described clock selection circuit comprises:
Select logical circuit, described multiple sampled clock signal and the clock signal of system received contrast by it, find the immediate sampled clock signal in the hopping edge of its hopping edge and described clock signal of system, and export the gating signal of the immediate sampled clock signal in hopping edge of this hopping edge of gating and described clock signal of system;
Clock gate, it receives multiple sampled clock signal, and according to select logical circuit export gating signal gating and corresponding sampled clock signal as serioparallel exchange clock signal.
3. data sink according to claim 2, is characterized in that, described multiple sampled clock signal comprise multiple justified sampled clock signal and with described multiple justified margin sampled clock signal,
The phase difference of each justified sampled clock signal and adjacent justified margin sampled clock signal is that predetermined phase is poor, and the phase difference of each justified margin sampled clock signal and adjacent justified margin sampled clock signal is that predetermined phase is poor,
Described multiple justified sampled clock signal, described multiple justified margin sampled clock signal and the clock signal of system that receives contrast by described selection logical circuit, find the immediate justified sampled clock signal in the hopping edge of its hopping edge and described clock signal of system, and the gating signal of the immediate justified sampled clock signal in the hopping edge exporting this hopping edge of gating and described clock signal of system;
Described clock gate receives multiple justified sampled clock signal, and according to justified sampled clock signal corresponding to gating signal gating selecting logical circuit to export as serioparallel exchange clock signal.
4. data sink according to claim 3, it is characterized in that, in selection logical circuit, utilize each sampled clock signal to carry out sampling to described clock signal of system and obtain multiple system clock synchronization signal, two that find phase difference to undergo mutation adjacent system clock synchronization signals, two sampled clock signals that two that determine that phase difference undergos mutation adjacent system clock synchronization signals are corresponding, the hopping edge of the justified sampled clock signal in two sampled clock signals determined and the hopping edge of described clock signal of system closest.
5. data sink according to claim 3, is characterized in that, described hopping edge is rising edge.
6. data sink according to claim 2, it is characterized in that, described selection logical circuit also receives reset trigger signal, when reset trigger signal becomes effective at every turn, the immediate sampled clock signal in hopping edge that described selection logical circuit searches once its hopping edge and described clock signal of system again, and export corresponding gating signal.
7. data sink according to claim 6, it is characterized in that, described selection logical circuit also exports reset synchronization signal to described serial-parallel conversion circuit, synchronous with described clock signal of system to ensure the parallel reception data that described serial-parallel conversion circuit exports.
8. data sink according to claim 6, is characterized in that, it also comprises:
Packet synchronisation circuit, it receives the parallel reception data from described serial-parallel conversion circuit, and carries out packet synchronisation based on described clock signal of system to parallel reception data.
9. a data receiving system, is characterized in that, it comprises:
Multiple as arbitrary in claim 1-8 as described in data sink, each data sink receives the data transfer signal sent from same data source, receives and recovers reference clock signal and clock signal of system.
10. a data transmission system, it comprises:
Data source, obtains data transfer signal after data to be transmitted being modulated and send this data transfer signal based on tranmitting data register signal;
Data receiving system as claimed in claim 9, each data sink receives the data transfer signal sent from described data source,
Clock generator, it produces reference clock signal, this reference clock signal is provided to data source, described data source produces described tranmitting data register signal according to this reference clock signal, this reference clock signal is also provided to each data sink by as recovery reference clock signal, and this reference clock signal is provided to each data sink by as clock signal of system after certain delay.
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| CN201520023308.8U CN204362064U (en) | 2015-01-14 | 2015-01-14 | Data sink, data receiving system and data transmission system |
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| CN201520023308.8U CN204362064U (en) | 2015-01-14 | 2015-01-14 | Data sink, data receiving system and data transmission system |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104579570A (en) * | 2015-01-14 | 2015-04-29 | 灿芯半导体(上海)有限公司 | Data receiver, data receiving system and data transmission system |
| CN109947681A (en) * | 2019-03-20 | 2019-06-28 | 天津芯海创科技有限公司 | Stringization/deserializer and high speed interface protocol exchange chip |
| CN113364468A (en) * | 2021-06-24 | 2021-09-07 | 成都纳能微电子有限公司 | Serial-to-parallel conversion alignment circuit and method |
-
2015
- 2015-01-14 CN CN201520023308.8U patent/CN204362064U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104579570A (en) * | 2015-01-14 | 2015-04-29 | 灿芯半导体(上海)有限公司 | Data receiver, data receiving system and data transmission system |
| CN109947681A (en) * | 2019-03-20 | 2019-06-28 | 天津芯海创科技有限公司 | Stringization/deserializer and high speed interface protocol exchange chip |
| CN113364468A (en) * | 2021-06-24 | 2021-09-07 | 成都纳能微电子有限公司 | Serial-to-parallel conversion alignment circuit and method |
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