CN109947681A - Stringization/deserializer and high speed interface protocol exchange chip - Google Patents
Stringization/deserializer and high speed interface protocol exchange chip Download PDFInfo
- Publication number
- CN109947681A CN109947681A CN201910212722.6A CN201910212722A CN109947681A CN 109947681 A CN109947681 A CN 109947681A CN 201910212722 A CN201910212722 A CN 201910212722A CN 109947681 A CN109947681 A CN 109947681A
- Authority
- CN
- China
- Prior art keywords
- circuit
- stringization
- configuration
- deserializer
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Communication Control (AREA)
Abstract
The present invention provides a kind of stringization/deserializer and high speed interface protocol exchange chips；Stringization/deserializer includes configuration management circuit and the string/deserializing circuit for setting quantity；Stringization/deserializing circuit includes receiver, transmitter and clock management circuits；Configuration management circuit receives the configuration-direct that software definition control circuit is sent；According to configuration-direct, each stringization/deserializing circuit is configured；Clock management circuits export the corresponding clock signal of configuration-direct to receiver and transmitter；After receiver converts parallel data for the serial data that external physical link is sent according to the corresponding high speed interface protocol of configuration-direct, parallel data is sent to physical code circuit；After transmitter converts serial data for the parallel data that physical code circuit is sent according to the corresponding high speed interface protocol of configuration-direct, serial data is sent to external physical link.The present invention improves string/deserializer to the applicability of a variety of high speed interface protocols, improves efficiency.
Description
Technical field
The present invention relates to high speed interface protocol technical fields, assist more particularly, to a kind of stringization/deserializer and high-speed interface
Discuss exchange chip.
Background technique
HSSI High-Speed Serial Interface protocol circuits most at present, usual data processing granularity are divided into three hierarchical structures in the industry,
That is transmission transaction layer, data link layer and physical transfer sublayer, and SerDes (Serializer/Deserializer stringization/
Deserializer) circuit be high speed serialization protocol interface core component；SerDes circuit is responsible for the number of high speed protocol serial line interface
Word signal carries out physical transfer after being converted to High Speed Analog differential signal.It is directed to different type protocol architecture, is respectively required
The function of physical layer specification is different from performance, sets so each protocol interface has all carried out otherness to the SerDes component of itself
Meter.The SerDes of existing high speed serialization protocol interface is designed, mainly according to the function and performance of own protocol physical specification
The design that demand carries out, and application can not be matched directly to other protocol interfaces.So will cause in design different agreement interface
When, it needs to be designed SerDes adjustment, working efficiency is lower.
Summary of the invention
In view of this, the purpose of the present invention is to provide a kind of stringization/deserializer and high speed interface protocol exchange chip, with
Stringization/deserializer is improved to the applicability of a variety of high speed interface protocols, is improved efficiency.
In a first aspect, string/the deserializer is set to high quick access the embodiment of the invention provides a kind of stringization/deserializer
In mouth agreement exchange chip；Stringization/deserializer respectively with physical code circuit, software definition control circuit and external physical link
Connection；Stringization/deserializer includes configuration management circuit and the string/deserializing circuit for setting quantity；Configuration management circuit respectively with
Stringization/deserializing circuit connection；Stringization/deserializing circuit includes receiver, transmitter and clock management circuits；Clock management circuits point
It is not connect with receiver and transmitter；Configuration management circuit is used to receive the configuration-direct of software definition control circuit transmission；Root
According to configuration-direct, each stringization/deserializing circuit is configured；Clock management circuits are used to match to receiver and transmitter output
Set the corresponding clock signal of instruction；Receiver is for sending out external physical link according to the corresponding high speed interface protocol of configuration-direct
The serial data sent is converted into parallel data, and parallel data is sent to physical code circuit；Transmitter according to configuration for referring to
It enables corresponding high speed interface protocol convert serial data for the parallel data that physical code circuit is sent, serial data is sent
To external physical link.
With reference to first aspect, the embodiment of the invention provides the first possible embodiments of first aspect, wherein on
Stating configuration-direct includes multiple configuration subcommands；Configuration management circuit carries out the corresponding serial/deserializing circuit of configuration subcommand
Setting；Configuring subcommand includes clock frequency, parallel bit wide and channel selecting.
With reference to first aspect, the embodiment of the invention provides second of possible embodiments of first aspect, wherein on
Stating high speed interface protocol includes FC-AE-ASM agreement, 3.0 agreement of RapidIO, 10GBASE-KR agreement and 1000BASE-SX association
One of view is a variety of.
The possible embodiment of second with reference to first aspect, the embodiment of the invention provides the third of first aspect
Possible embodiment, wherein above-mentioned receiver include the sequentially connected more gradient amplitudes of oscillation adjust circuit, receiver equalization circuitry,
Clock data recovery circuit, serial-parallel conversion circuit, PRBS detection circuit and the first data bit width conversion circuit；Configuration management circuit
It is connect with the first data bit width conversion circuit；Configuration management circuit output controls signal to the first data bit width conversion circuit
Parallel bit wide is configured.
The third possible embodiment with reference to first aspect, the embodiment of the invention provides the 4th kind of first aspect
Possible embodiment, wherein above-mentioned string/deserializing circuit further includes that the first reception differential port port and second receive difference
Port；First receives differential port port and the second reception differential port and more gradient amplitudes of oscillation adjusting circuit connection；More gradient pendulum
Width adjusts circuit and receives the string that differential port reception external physical link is sent by the first reception differential port port and second
Row data.
The possible embodiment of second with reference to first aspect, the embodiment of the invention provides the 5th kind of first aspect
Possible embodiment, wherein above-mentioned transmitter include sequentially connected second data bit width conversion circuit, first selector,
Asynchronous buffer circuit, second selector, parallel-to-serial converter, preemphasis circuit and driver；Transmitter further includes PRBS Sequence
Source circuit；PRBS Sequence source circuit is connected with the input terminal of first selector；First selector and second selector are alternative
Selector；Two input terminals of first selector are connect with PRBS Sequence source circuit and the second data bit width conversion circuit respectively；
The output end and asynchronous buffer circuit connection of first selector；Two input terminals of second selector respectively with parallel-to-serial converter
And asynchronous buffer circuit；The output end of second selector is connect with parallel-to-serial converter；Configuration management circuit is selected with first respectively
Select the selection end of device, the selection end of second selector and the connection of the second data bit width conversion circuit；Configuration management circuit output control
Signal processed is to control the output signal of the output end of first selector and second selector；Configuration management circuit output controls signal
It is configured with the parallel bit wide to the second data bit width conversion circuit.
The 5th kind of possible embodiment with reference to first aspect, the embodiment of the invention provides the 6th kind of first aspect
Possible embodiment, wherein above-mentioned string/deserializing circuit further includes that the first transmission differential port port and second send difference
Port；First transmission differential port port and the second transmission differential port are connect with preemphasis circuit；Preemphasis circuit passes through the
One, which sends differential port port and the second transmission differential port, is sent to external physical link for parallel data.
With reference to first aspect, the embodiment of the invention provides the 7th kind of possible embodiments of first aspect, wherein also
Including reset circuit；Reset circuit is connect with configuration management circuit and stringization/deserializing circuit respectively；Reset circuit is used for when reception
When to reset signal, hard reset is carried out to configuration management circuit and stringization/deserializing circuit.
With reference to first aspect, the embodiment of the invention provides the 8th kind of possible embodiments of first aspect, wherein on
Stating string/deserializing circuit further includes configuration interface；Configure interface and configuration management circuit connection；Configuration management circuit, which passes through, to be configured
Interface and software definition control circuit carry out signal transmission.
Second aspect, the embodiment of the present invention also provide a kind of high speed interface protocol exchange chip, including sequentially connected soft
Part defines the 8th kind of possible described in any item strings of embodiment of control circuit, such as above-mentioned first aspect to first aspect
Change/deserializer, physical code circuit, data link circuit and transmission transaction circuit.
The embodiment of the present invention bring it is following the utility model has the advantages that
The embodiment of the invention provides a kind of stringization/deserializer and high speed interface protocol exchange chips；Stringization/deserializer packet
It includes configuration management circuit and sets string/deserializing circuit of quantity；Stringization/deserializing circuit includes receiver, transmitter and clock
Manage circuit；Configuration management circuit receives the configuration-direct that software definition control circuit is sent；According to configuration-direct, to each string
Change/deserializing circuit is configured；Clock management circuits export the corresponding clock signal of configuration-direct to receiver and transmitter；It connects
It receives device and parallel data is converted for the serial data that external physical link is sent according to the corresponding high speed interface protocol of configuration-direct
Afterwards, parallel data is sent to physical code circuit；Transmitter compiles physics according to the corresponding high speed interface protocol of configuration-direct
After the parallel data that code circuit is sent is converted into serial data, serial data is sent to external physical link.Which improves
Applicability of the string/deserializer to a variety of high speed interface protocols, improves efficiency.
Other features and advantages of the present invention will illustrate in the following description, alternatively, Partial Feature and advantage can be with
Deduce from specification or unambiguously determine, or by implementing above-mentioned technology of the invention it can be learnt that.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, better embodiment is cited below particularly, and match
Appended attached drawing is closed, is described in detail below.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is the structural schematic diagram of HSSI High-Speed Serial Interface protocol circuit provided in an embodiment of the present invention；
Fig. 2 is a kind of structural schematic diagram of stringization/deserializer provided in an embodiment of the present invention；
Fig. 3 is each function mould in a kind of multichannel SerDes structure based on multi-protocols framework provided in an embodiment of the present invention
Block number evidence and control planning schematic diagram；
Fig. 4 is that the multichannel SerDes structure of multi-protocols framework provided in an embodiment of the present invention is in the data under 4X mode
Flow graph；
Fig. 5 is that the multichannel SerDes structure of multi-protocols framework provided in an embodiment of the present invention is under 2X+2X mode
Data flow figure；
Fig. 6 is that the multichannel SerDes structure of multi-protocols framework provided in an embodiment of the present invention is under 2X+1X+1X mode
Data flow figure；
Fig. 7 is that the multichannel SerDes structure of multi-protocols framework provided in an embodiment of the present invention is under 1X+1X+2X mode
Data flow figure；
Fig. 8 is that the multichannel SerDes structure of multi-protocols framework provided in an embodiment of the present invention is in 1X+1X+1X+1X mould
Data flow figure under formula；
Fig. 9 is a kind of structural schematic diagram of high speed interface protocol exchange chip provided in an embodiment of the present invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with attached drawing to the present invention
Technical solution be clearly and completely described, it is clear that described embodiments are some of the embodiments of the present invention, rather than
Whole embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making creative work premise
Under every other embodiment obtained, shall fall within the protection scope of the present invention.
As data processing platform (DPP) is to the promotion increasingly of data transfer bandwidth demand and all types of high speed serialization agreements
Development needs a kind of clog-free, low time delay that can be realized between any two kinds of agreements, the highly reliable, kind that flexibly exchanges at present
The exchange chip of heterogeneous protocol interconnection.And the high speed protocol serial line interface of this chip, it is desirable to carry out isomery design, meet a variety of
The functional performance demand of agreement.High-speed serial link system gradually replaces parallel link system, becomes high speed data link
Prevailing transmission mode.Transmission mode of the serial line interface due to using differential signal, so having compared to parallel link farther
Transmission range, more large transmission bandwidth and the advantages that better signal quality.SerDes circuit is high speed serialization protocol interface
Core component, the performance quality of high speed protocol interface, the overwhelming majority depends on SerDes performance.
HSSI High-Speed Serial Interface protocol circuits most at present, usual data processing granularity are divided into three hierarchical structures in the industry,
That is transmission transaction layer, data link layer and physical transfer sublayer, SerDes circuit are located at the physical transfer of high speed protocol interface
Sublayer, as shown in Figure 1；SerDes circuit is responsible for the digital signal of high speed protocol serial line interface being converted to High Speed Analog difference
Physical transfer is carried out after signal.It is directed to different type protocol architecture, the function and performance for respectively requiring physical layer specification are not
Together, so each protocol interface has all carried out otherness design to the SerDes component of itself.It can be compatible with there is presently no a
The serial line interface of multiple agreements, thus design a kind of multichannel SerDes structure that can satisfy various protocols demand be support it is more
The premise of agreement high speed serialization agreement.
The SerDes of existing high speed serialization protocol interface is designed, mainly according to the function of own protocol physical specification with
The design that performance requirement carries out, and application can not be matched directly to other protocol interfaces.So will cause in design different agreement
When interface, need to be designed SerDes adjustment, and software definition can not be supported based on the multichannel of multi-protocols
SerDes functional requirement.
By the functional performance demand of the multiple agreements of integration design is normalized, so that framework one kind is based in the present invention
The multichannel SerDes structure of multi-protocols framework, the multi-protocols compatible high-speed for serving the exchange chip of heterogeneous protocol interconnection are serial
In interface.
Based on this, the embodiment of the invention provides a kind of stringization/deserializer and high speed interface protocol exchange chip, Ke Yiying
For field of data transmission.
For convenient for understanding the present embodiment, first to a kind of string/deserializer disclosed in the embodiment of the present invention into
Row is discussed in detail.
The embodiment of the invention provides a kind of stringization/deserializers；String/the deserializer is set to high speed interface protocol exchange
In chip；Stringization/deserializer respectively with physical code circuit, software definition control circuit and external physical link connection；Stringization/
Deserializer includes configuration management circuit and the string/deserializing circuit for setting quantity；Stringization/deserializing circuit includes receiver, sends
Device and clock management circuits；Clock management circuits are connect with receiver and transmitter respectively.
To set quantity as 4, stringization/deserializer structural schematic diagram is as shown in Fig. 2, stringization/deserializer includes matching
Set management circuit 10 and the first stringization/deserializing circuit 20a, the second stringization/deserializing circuit 20b, third string/deserializing circuit 20c
And the 4th stringization/deserializing circuit 20d；Configuration management circuit 10 respectively with the first stringization/deserializing circuit 20a, the second stringization/unstring
Circuit 20b, third string/deserializing circuit 20c and the 4th stringization/deserializing circuit 20d connection；First stringization/deserializing circuit 20a packet
Include the first receiver 201a, the first transmitter 202a and the first clock management circuits 203a；Second stringization/deserializing circuit 20b packet
Include second receiver 201b, the second transmitter 202b and second clock management circuit 203b；Third string/deserializing circuit 20c packet
Include third receiver 201c, third transmitter 202c and third clock management circuits 203c；4th stringization/deserializing circuit 20d packet
Include the 4th receiver 201d, the 4th transmitter 202d and the 4th clock management circuits 203d.
Configuration management circuit is used to receive the configuration-direct of software definition control circuit transmission；According to configuration-direct, to each
A stringization/deserializing circuit is configured；Wherein, above-mentioned configuration-direct includes multiple configuration subcommands；Configuration management circuit is to matching
Corresponding serial/the deserializing circuit of subcommand is set to be configured；Configuring subcommand includes clock frequency, parallel bit wide and channel selecting
Deng respectively to clock management circuits, the configurable module in receiver and transmitter is configured；Each clock management circuits are used
In to belonging to a string of change/deserializing circuit receivers and the corresponding clock signal of transmitter output configuration-direct；Pass through clock synchronization
Clock management circuit is configured, and different string/deserializing circuits can be made to synchronize work or asynchronous working；To receiver
Configurable module is carried out with postponing, which can handle and corresponding high speed interface protocol data；Receiver is used for basis
The serial data that external physical link is sent is converted parallel data by the corresponding high speed interface protocol of configuration-direct, by simultaneously line number
According to being sent to physical code circuit；The configurable module of transmitter is carried out with postponing, the transmitter can handle with it is corresponding
High speed interface protocol data；What transmitter was used to be sent physical code circuit according to the corresponding high speed interface protocol of configuration-direct
Parallel data is converted into serial data, and serial data is sent to external physical link.
Above-mentioned receiver may include impedance calibration circuit, balanced device (CTLE-Continuous Time Linear
Equalizer continuous time linear equalization and DFE-Decision Feedback Equalization decision feedback equalization), when
The string that clock data recovery circuit and logic (clock data recovery circuit abbreviation CDR), phase difference value device, parallel bit wide can configure is simultaneously
Conversion circuit, PRBS (Pseudo Random Binary Sequence, pseudo-random binary sequence) detection, built-in receive are led to
Road loopback etc.；It is mainly used for completing according to entering data to adjustment clock, to realize to the samplings of data and by serial data
It is converted into parallel data.
Above-mentioned transmitter may include parallel-to-serial converter, output driver, preemphasis control circuit, edge control electricity
The parallel-to-serial converter etc. that road, impedance calibration circuit, PRBS generation, built-in transmission path loopback and parallel bit wide can configure；It is main
It is used to complete data by parallel-to-serial conversion and driving.
The embodiment of the invention provides a kind of stringization/deserializers；Stringization/deserializer includes configuration management circuit and setting number
String/deserializing circuit of amount；Stringization/deserializing circuit includes receiver, transmitter and clock management circuits；Configuration management circuit connects
Receive the configuration-direct that software definition control circuit is sent；According to configuration-direct, each stringization/deserializing circuit is configured；When
Clock manages circuit to receiver and the corresponding clock signal of transmitter output configuration-direct；Receiver is corresponding according to configuration-direct
After the serial data that external physical link is sent is converted parallel data by high speed interface protocol, parallel data is sent to physics
Coding circuit；Transmitter is converted according to the parallel data that the corresponding high speed interface protocol of configuration-direct sends physical code circuit
After serial data, serial data is sent to external physical link.Which improves string/deserializer to a variety of high quick access
The applicability of mouth agreement, improves efficiency.
The multichannel SerDes structure that the embodiment of the invention provides a kind of based on multi-protocols framework (alternatively referred to as stringization/
Deserializer), it realizes on the basis of SerDes structure string/deserializer shown in Fig. 2；The SerDes structure can be adapted for
High speed interface protocol is FC-AE-ASM agreement, 3.0 agreement of RapidIO, in 10GBASE-KR agreement and 1000BASE-SX agreement
One or more data string or unstring.
The multichannel SerDes circuit for the support various protocols that the present invention designs, has been compatible with FC-AE-ASM agreement,
3.0 agreement of RapidIO, the physical specification requirement of four kinds of serial interface protocols of 10GBASE-KR agreement 1000BASE-SX, is propped up simultaneously
The channel binding of different agreement mode is held, and flank speed is up to 10.3125Gbps.
The main design thought of SerDes circuit of the invention are as follows: analyze each protocol physical layers specification first, arrange each
Interface protocol function and performance requirement；After completion demand arranges, design is normalized to identical close function, as SerDes
Shared logic of the circuit under different agreement operating mode；The differentiation function that finally different agreement is required, can according to software
The mentality of designing of definition, be designed as it is configurable can isomery processing circuit.
Multi-protocols high speed serialization SerDes major function is by data by being converted into high-speed serial signals parallel and being sent to
On channel, while the serial data of high speed can be received from channel and be converted into parallel signal and used for upper layer, entire mistake
Journey is completed under the synchronous effect of clock.SerDes circuit of the invention designs a submodule according to a functional requirement
Mode be designed, each function module data and control planning are as shown in figure 3, the big portion of demand of each agreement to SerDes function
Divide and be consistent, so the identical part of functional requirement is designed as generic logic.
SerDes circuit is designed for one group according to 4Lane (channel), referred to herein as a Bank (group), each Bank
Mainly consist of three parts: 4 transmitting-receiving main channels, clock processing module, configuration management and reseting module (also referred to as reset electricity
Road)；Wherein, transmitting-receiving main channel configures a clock processing module, and the two, which combines, is equivalent to above-mentioned string/unstring
Circuit, a transmitting-receiving main channel include a receiver and a transmitter；Reset circuit respectively with configuration management circuit and string
Change/deserializing circuit connection；Clock processing module is differential driving module, mainly includes phase-locked loop circuit QPLL in Bank, channel
Interior phase-locked loop circuit CPLL, clock selection circuit, frequency dividing circuit etc.；Configuration management mainly includes configuration bus management module, is posted
Storage management module is responsible for realizing that software is matched to data Path selection, clock frequency, data bit width and submodule operating mode
Set control；Reset circuit is for when it receives the reset signal it, carrying out configuration management circuit and stringization/deserializing circuit firmly multiple
Position.
In addition, above-mentioned Clock management module can also directly input phase-locked loop circuit CPLL in channel using reference clock
Scheme realizes above functions, can be used as alternative scheme of the invention and realizes.
Specifically, stringization/deserializing circuit structure also is understood that from Fig. 3；In the Lane 0 that Fig. 3 is shown, connect
Receiving device includes that sequentially connected more gradient amplitudes of oscillation adjust circuit, receiver equalization circuitry, clock data recovery circuit, serioparallel exchange electricity
Road, PRBS detection circuit and the first data bit width conversion circuit；One eye figure observation module can also be set and receiving balanced electricity
Data cases between road and clock data recovery circuit module are observed；Configuration management circuit and the first data bit width are converted
Circuit connection；Configuration management circuit output control signal is configured with the parallel bit wide to the first data bit width conversion circuit.
Transmitter include sequentially connected second data bit width conversion circuit, first selector, asynchronous buffer circuit, second selector,
Parallel-to-serial converter, preemphasis circuit and driver；Transmitter further includes PRBS Sequence source circuit；PRBS Sequence source circuit and the
The input terminal of one selector is connected；First selector and second selector are alternative selector；Two of first selector are defeated
Enter end to connect with PRBS Sequence source circuit and the second data bit width conversion circuit respectively；The output end of first selector delays with asynchronous
Deposit circuit connection；Two input terminals of second selector respectively with parallel-to-serial converter and asynchronous buffer circuit；Second selector
Output end connect with parallel-to-serial converter；Configuration management circuit respectively with the selection end of first selector, second selector
Select end and the connection of the second data bit width conversion circuit；Configuration management circuit output controls signal to control first selector and the
The output signal of the output end of two selectors；Configuration management circuit output controls signal to the second data bit width conversion circuit
Parallel bit wide is configured.
In addition, further including configuration interface in a Lane；Configure interface and configuration management circuit connection；Configuration management circuit
Signal transmission is carried out by configuring interface and software definition control circuit.
It further include the first reception differential port port and the second reception differential port in one Lane, i.e. it is poor to receive in Fig. 3
Divide P and receives difference N；First receives differential port port and the second reception differential port and more gradient amplitudes of oscillation adjusting circuit company
It connects；More gradient amplitudes of oscillation adjust circuit and receive differential port port and the second reception differential port reception external physical chain by first
The serial data that road is sent.
It further include the first transmission differential port port and the second transmission differential port in one Lane, i.e. it is poor to send in Fig. 3
Divide P and sends difference N；First transmission differential port port and the second transmission differential port are connect with preemphasis circuit；Preemphasis
Parallel data is sent to external physical link by the first transmission differential port port and the second transmission differential port by circuit.
SerDes circuit provided by the invention can support the demand of different application form, logical including hybrid protocol
Road, different channel width accesses, different rates access.
1. being directed to different channel width accesses
Refer in the same Bank of SerDes with width access, can be according to different application agreement, software definition is at different
Channel width.That is 4 Lane inside SerDes support the channel multiplexing under 1X/2X/4X mode, support a variety of moulds of dynamic configuration
Formula: the redundant mode under 4X, 2X+2X, 2X (1X)+1X+1X, 1X+1X+2X (1X), 1X+1X+1X+1X and corresponding modes.I.e. 1
4 channels for including in SerDes can be dynamically configured to following Three models, while support the redundancy mould under above-mentioned 3 kinds of modes
Formula configuration:
(1) 4 channels operation in 4x mode, while can redundant configuration at 2X (Lane2~Lane3 redundancy), 1X (Lane1
~Lane3 redundancy), as shown in figure 4, four channels handle input data or output data simultaneously, with the same physical code electricity
Road carries out data transmission.
(2) 2 channels operations in 1st 2x mode, while can redundant configuration at 1X (Lane1 redundancy), another 2 channel works
Make in 2x mode, while can redundant configuration at 1X (Lane3 redundancy), as shown in Figure 5.
(3) 2 channels operations in 2x mode, while can redundant configuration at 1X (Lane1 redundancy), Lane2 works in 1X mould
Formula, Lane3 work in 1X mode, as shown in Figure 6.
(4) Lane0 work works in 2X mode, simultaneously in 1X mode, Lane1 work in 1X mode, Lane2~Lane3
Can redundant configuration be 1X (Lane3 redundancy), as shown in Figure 7.
(5) Lane0, Lane1, Lane2, Lane3 work in 1x mode, as shown in Figure 8 respectively.
Wherein, PCS is physical code circuit；TX0_P, TX0_N are respectively the output letter for sending difference P and sending difference N
Number；RX0_P, RX0_N are respectively the input signal for receiving difference P and receiving difference N.
2. being directed to hybrid protocol access
Hybrid protocol access refers to the application characteristic that various communications protocols can be supported to coexist in the same Bank of SerDes.Consider
To the particularity of RapidIO agreement and the demand of simplified control device timing topology, each access of SerDes under hybrid protocol can be such as
Distribution shown in table 1, wherein Eth (Ethernet) agreement includes 10GBASE-KR and 1000BASE-SX agreement, and FC generation refers to FC-AE-
In ASM agreement, RapidIO generation, refer to 3.0 agreement of RapidIO.
Table 1
3. being directed to different rates access
Different rates access refers to that the different channels of SerDes IP can work in different rates.Need exist for explanation
It is that different rates access is limited to two conditions: the communication protocol of current channel, the Lane n X width mode of binding.
The SerDes IP of multi-protocols need to support the PHY layer specification of different agreement, and therefore, corresponding channel need to support difference
Multiple frequency points under agreement.It is specific as shown in table 2.Therefore multi-protocols high speed SerDes need to carry out rate under each protocol specification
Configuration.
Table 2
Further, since SerDes can work in different working modes, wherein the n channel to work under Lane n X mode
Must operate at same rate, and require the n Channel Synchronous, particularly, it is contemplated that upper controller timing topology it is simple
Change, Lane0~Lane1 and Lane2~Lane3 under 2X+2X mode must operate at same rate group, it may be assumed that rate group one:
1.25/2.5/5Gbps, rate group two: 3.125/6.25Gbps, rate group three: 10.3125Gbps.
Below end will be sent and received by taking the channel RapidIO3.0 agreement x4/10.3125G rate operating mode as an example
Multi-protocols multichannel SerDes circuit workflow is as shown in Figure 2.
1, under the channel RapidIO3.0 agreement x4/10.3125Gbps rate mode, multichannel SerDes circuit transmission path
Workflow:
A) chip is by carrying out hard reset to entire SerDes circuit and submodule relevant to SerDes.
B) user meets current protocol function and performance requirement by configuration management module, configuration: configuration originating data is logical
Road selects (two MUX in Fig. 5), is selected as functional mode data path；Configurable clock generator management module exports 10.3125Gbps
Rate corresponds to clock frequency；The data bit width conversion module of four Lane transmitting terminals is configured, operating mode is x4 mode.
C) user completes configuration, starts log-on data and sends, data are sent in physical link by SerDes circuit.
2, under the channel RapidIO3.0 agreement x4/10.3125Gbps rate mode, multichannel SerDes circuit receiving path
Workflow:
A) chip is by carrying out hard reset to entire SerDes circuit and submodule relevant to SerDes.
B) user meets current protocol function and performance requirement by configuration management module, configuration: configuration originating data is logical
Road selects (three MUX in Fig. 2), is selected as functional mode data path；Configurable clock generator management module exports 10.3125Gbps
Rate corresponds to clock frequency；The data bit width conversion module of four Lane transmitting terminals is configured, operating mode is x4 mode.
C) user completes configuration, starts log-on data and receives, the reception data from physical link are entered by SerDes
Into subsequent chip circuit.
The multichannel SerDes circuit based on multi-protocols framework that the present invention designs, has the advantage that
1, FC-AE-ASM agreement is supported, 3.0 agreement of RapidIO, four kinds of 10GBASE-KR agreement 1000BASE-SX serial
The requirement of interface protocol physical specification, realizes programmable operating mode switching, and SerDes circuit is suitable to different agreement application scenarios
It is greatly increased with property.
2, list SerDes circuit hybrid protocol of the invention works at the same time, and is connect using the high speed serialization of SerDes circuit of the present invention
Mouth is more flexible using form.The multi-protocol data interactive system designed using the present invention can greatly reduce system hardware rule
Mould and volume weight power dissipation overhead.
3, in circuit of the present invention on multiple critical data paths, built-in testing winding access is devised, circuit is increased
Measurability.
The embodiment of the present invention also provides a kind of high speed interface protocol exchange chip, and structural schematic diagram is as shown in Figure 9；The core
Piece includes sequentially connected software definition control circuit 80, above-mentioned string/deserializer 81, physical code circuit 82, data-link
Road circuit 83 and transmission transaction circuit 84.
High speed interface protocol exchange chip provided in an embodiment of the present invention, with a kind of stringization/solution provided by the above embodiment
String device technical characteristic having the same reaches identical technical effect so also can solve identical technical problem.
The computer program of a kind of stringization/deserializer and high speed interface protocol exchange chip provided by the embodiment of the present invention
Product, the computer readable storage medium including storing program code, the instruction that said program code includes can be used for executing
Previous methods method as described in the examples, specific implementation can be found in embodiment of the method, and details are not described herein.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description
And/or the specific work process of device, it can refer to corresponding processes in the foregoing method embodiment, details are not described herein.
In addition, in the description of the embodiment of the present invention unless specifically defined or limited otherwise, term " installation ", " phase
Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can
To be mechanical connection, it is also possible to be electrically connected；It can be directly connected, can also can be indirectly connected through an intermediary
Connection inside two elements.For the ordinary skill in the art, above-mentioned term can be understood at this with concrete condition
Concrete meaning in invention.
It, can be with if the function is realized in the form of SFU software functional unit and when sold or used as an independent product
It is stored in a computer readable storage medium.Based on this understanding, technical solution of the present invention is substantially in other words
The part of the part that contributes to existing technology or the technical solution can be embodied in the form of software products, the meter
Calculation machine software product is stored in a storage medium, including some instructions are used so that a computer equipment (can be a
People's computer, server or network equipment etc.) it performs all or part of the steps of the method described in the various embodiments of the present invention.
And storage medium above-mentioned includes: that USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), arbitrary access are deposited
The various media that can store program code such as reservoir (RAM, Random Access Memory), magnetic or disk.
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" be based on the orientation or positional relationship shown in the drawings, merely to
Convenient for description the present invention and simplify description, rather than the device or element of indication or suggestion meaning must have a particular orientation,
It is constructed and operated in a specific orientation, therefore is not considered as limiting the invention.In addition, term " first ", " second ",
" third " is used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance.
Finally, it should be noted that embodiment described above, only a specific embodiment of the invention, to illustrate the present invention
Technical solution, rather than its limitations, scope of protection of the present invention is not limited thereto, although with reference to the foregoing embodiments to this hair
It is bright to be described in detail, those skilled in the art should understand that: anyone skilled in the art
In the technical scope disclosed by the present invention, it can still modify to technical solution documented by previous embodiment or can be light
It is readily conceivable that variation or equivalent replacement of some of the technical features；And these modifications, variation or replacement, do not make
The essence of corresponding technical solution is detached from the spirit and scope of technical solution of the embodiment of the present invention, should all cover in protection of the invention
Within the scope of.Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. a kind of stringization/deserializer, which is characterized in that the stringization/deserializer is set in high speed interface protocol exchange chip；
The stringization/deserializer respectively with physical code circuit, software definition control circuit and external physical link connection；The string
Change/deserializer includes configuration management circuit and the string/deserializing circuit for setting quantity；The configuration management circuit respectively with it is described
Stringization/deserializing circuit connection；The stringization/deserializing circuit includes receiver, transmitter and clock management circuits；The clock pipe
Reason circuit is connect with the receiver and the transmitter respectively；
The configuration management circuit is used to receive the configuration-direct that the software definition control circuit is sent；Referred to according to the configuration
It enables, each stringization/deserializing circuit is configured；
The clock management circuits are used to export the corresponding clock letter of the configuration-direct to the receiver and the transmitter
Number；
What the receiver was used to be sent the external physical link according to the corresponding high speed interface protocol of the configuration-direct
Serial data is converted into parallel data, and the parallel data is sent to the physical code circuit；
What the transmitter was used to be sent the physical code circuit according to the corresponding high speed interface protocol of the configuration-direct
Parallel data is converted into serial data, and the serial data is sent to the external physical link.
2. stringization according to claim 1/deserializer, which is characterized in that the configuration-direct includes multiple configuration lives
It enables；The configuration management circuit is configured the corresponding stringization/deserializing circuit of the configuration subcommand；The configuration subcommand
Including clock frequency, parallel bit wide and channel selecting.
3. stringization according to claim 1/deserializer, which is characterized in that the high speed interface protocol includes FC-AE-ASM
Agreement, RapidIO3.0 agreement, one of 10GBASE-KR agreement and 1000BASE-SX agreement or a variety of.
4. stringization according to claim 3/deserializer, which is characterized in that the receiver includes sequentially connected mostly terraced
It spends the amplitude of oscillation and adjusts circuit, receiver equalization circuitry, clock data recovery circuit, serial-parallel conversion circuit, PRBS detection circuit and first
Data bit width conversion circuit；
The configuration management circuit is connect with the first data bit width conversion circuit；The configuration management circuit output control letter
It number is configured with the parallel bit wide to the first data bit width conversion circuit.
5. stringization according to claim 4/deserializer, which is characterized in that the stringization/deserializing circuit further includes first connecing
Astigmat divides ports port and the second reception differential port；Described first receives differential port port and the second reception differential ends
Mouth adjusts circuit connections with more gradient amplitudes of oscillation；More gradient amplitudes of oscillation adjust circuit and receive differential port by described first
Port and the second reception differential port receive the serial data that the external physical link is sent.
6. stringization according to claim 3/deserializer, which is characterized in that the transmitter includes sequentially connected second
Data bit width conversion circuit, first selector, asynchronous buffer circuit, second selector, parallel-to-serial converter, preemphasis circuit and
Driver；The transmitter further includes PRBS Sequence source circuit；The PRBS Sequence source circuit is defeated with the first selector
Enter end to be connected；
The first selector and the second selector are alternative selector；Two input terminals of the first selector point
It is not connect with the PRBS Sequence source circuit and the second data bit width conversion circuit；The output end of the first selector with
The asynchronous buffer circuit connection；Two input terminals of the second selector respectively with the parallel-to-serial converter and described different
Walk buffer circuit；The output end of the second selector is connect with the parallel-to-serial converter；
The configuration management circuit respectively with the selection end of the first selector, the selection end of the second selector and described
The connection of second data bit width conversion circuit；The configuration management circuit output control signal is to control the first selector and institute
State the output signal of the output end of second selector；The configuration management circuit output control signal is to second data bit
The parallel bit wide of wide conversion circuit is configured.
7. stringization according to claim 6/deserializer, which is characterized in that the stringization/deserializing circuit further includes the first hair
Send differential port port and the second transmission differential port；Described first sends differential port port and the second transmission differential ends
Mouth is connect with the preemphasis circuit；The preemphasis circuit sends differential port port and second hair by described first
Send differential port that parallel data is sent to the external physical link.
8. stringization according to claim 1/deserializer, which is characterized in that further include reset circuit；The reset circuit point
It is not connect with the configuration management circuit and the stringization/deserializing circuit；
The reset circuit is used for when it receives the reset signal it, to the configuration management circuit and the stringization/deserializing circuit
Carry out hard reset.
9. stringization according to claim 1/deserializer, which is characterized in that the stringization/deserializing circuit further includes that configuration connects
Mouthful；The configuration interface and the configuration management circuit connection；The configuration management circuit by the configuration interface with it is described
Software definition control circuit carries out signal transmission.
10. a kind of high speed interface protocol exchange chip, which is characterized in that including sequentially connected software definition control circuit, such as
The described in any item stringizations of claim 1-9/deserializer, physical code circuit, data link circuit and transmission transaction circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910212722.6A CN109947681B (en) | 2019-03-20 | 2019-03-20 | Serializer/deserializer and high-speed interface protocol exchange chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910212722.6A CN109947681B (en) | 2019-03-20 | 2019-03-20 | Serializer/deserializer and high-speed interface protocol exchange chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109947681A true CN109947681A (en) | 2019-06-28 |
| CN109947681B CN109947681B (en) | 2020-12-01 |
Family
ID=67011141
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910212722.6A Active CN109947681B (en) | 2019-03-20 | 2019-03-20 | Serializer/deserializer and high-speed interface protocol exchange chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109947681B (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110493310A (en) * | 2019-07-17 | 2019-11-22 | 中国人民解放军战略支援部队信息工程大学 | A kind of protocol controller and method of software definition |
| CN112685355A (en) * | 2021-01-11 | 2021-04-20 | 龙迅半导体（合肥）股份有限公司 | String adding device |
| CN113572486A (en) * | 2021-06-29 | 2021-10-29 | 中国人民解放军战略支援部队信息工程大学 | Transmitter with low-speed SerDes interface, receiver with low-speed SerDes interface and circuit design method of transmitter |
| CN114143513A (en) * | 2021-12-29 | 2022-03-04 | 重庆紫光华山智安科技有限公司 | Multi-dimensional feature acquisition device and image acquisition method |
| CN114336197A (en) * | 2022-01-20 | 2022-04-12 | 深圳宏芯宇电子股份有限公司 | Interface conversion device, test board and card reader |
| CN114731294A (en) * | 2020-01-21 | 2022-07-08 | 华为技术有限公司 | Exchange network chip and exchange equipment |
| CN114968875A (en) * | 2022-05-31 | 2022-08-30 | 重庆长安汽车股份有限公司 | Self-adaptive system supporting vehicle-mounted serial deserializing link and automatic driving automobile |
| WO2022193328A1 (en) * | 2021-03-19 | 2022-09-22 | 华为技术有限公司 | Serializing/deserializing circuit, serial data receiving method, and chip |
| CN115882870A (en) * | 2023-02-01 | 2023-03-31 | 井芯微电子技术(天津)有限公司 | High-speed serializer and deserializer integration method and electronic equipment |
| WO2023125722A1 (en) * | 2021-12-31 | 2023-07-06 | 华为技术有限公司 | High-speed serial interface and data transmission method |
| CN117539818A (en) * | 2024-01-10 | 2024-02-09 | 富瀚微电子(成都)有限公司 | Interface based on PHY model, chip integrating interface and chip simulation system |
| CN117749263A (en) * | 2024-02-08 | 2024-03-22 | 合肥国家实验室 | Receiving device based on space laser communication and space laser communication system |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6901126B1 (en) * | 2000-06-30 | 2005-05-31 | Texas Instruments Incorporated | Time division multiplex data recovery system using close loop phase and delay locked loop |
| CN101394678A (en) * | 2008-11-07 | 2009-03-25 | 烽火通信科技股份有限公司 | Serialization/de-serialization interface module generally used in GEPON/GPON |
| CN102257849A (en) * | 2011-06-08 | 2011-11-23 | 华为技术有限公司 | Method, system and apparatus for dynamically adjusting link |
| CN102323877A (en) * | 2011-08-31 | 2012-01-18 | 广东威创视讯科技股份有限公司 | SERDES-based video processing system |
| CN204362064U (en) * | 2015-01-14 | 2015-05-27 | 灿芯半导体(上海)有限公司 | Data sink, data receiving system and data transmission system |
| CN105119715A (en) * | 2015-07-03 | 2015-12-02 | 合肥工业大学 | FPGA intra-IO sheet interconnecting digital circuit based on re-encryption algorithm |
| CN105680871A (en) * | 2016-04-07 | 2016-06-15 | 武汉芯泰科技有限公司 | Parallel-serial/ serial-parallel conversion device for data serial transmission |
| CN106230826A (en) * | 2016-08-02 | 2016-12-14 | 哈尔滨工业大学 | Application system interface protocol automatic analyzer |
| CN108039961A (en) * | 2017-12-01 | 2018-05-15 | 周阳 | A kind of apparatus and method for automatically configuring high speed serialization transceiver parameters |
| CN108737024A (en) * | 2017-04-13 | 2018-11-02 | 默升科技集团有限公司 | Low-power SERDES frameworks and agreement |
| CN109495519A (en) * | 2019-01-09 | 2019-03-19 | 天津芯海创科技有限公司 | Physical code circuit and high speed interface protocol exchange chip |
-
2019
- 2019-03-20 CN CN201910212722.6A patent/CN109947681B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6901126B1 (en) * | 2000-06-30 | 2005-05-31 | Texas Instruments Incorporated | Time division multiplex data recovery system using close loop phase and delay locked loop |
| CN101394678A (en) * | 2008-11-07 | 2009-03-25 | 烽火通信科技股份有限公司 | Serialization/de-serialization interface module generally used in GEPON/GPON |
| CN102257849A (en) * | 2011-06-08 | 2011-11-23 | 华为技术有限公司 | Method, system and apparatus for dynamically adjusting link |
| CN102323877A (en) * | 2011-08-31 | 2012-01-18 | 广东威创视讯科技股份有限公司 | SERDES-based video processing system |
| CN204362064U (en) * | 2015-01-14 | 2015-05-27 | 灿芯半导体(上海)有限公司 | Data sink, data receiving system and data transmission system |
| CN105119715A (en) * | 2015-07-03 | 2015-12-02 | 合肥工业大学 | FPGA intra-IO sheet interconnecting digital circuit based on re-encryption algorithm |
| CN105680871A (en) * | 2016-04-07 | 2016-06-15 | 武汉芯泰科技有限公司 | Parallel-serial/ serial-parallel conversion device for data serial transmission |
| CN106230826A (en) * | 2016-08-02 | 2016-12-14 | 哈尔滨工业大学 | Application system interface protocol automatic analyzer |
| CN108737024A (en) * | 2017-04-13 | 2018-11-02 | 默升科技集团有限公司 | Low-power SERDES frameworks and agreement |
| CN108039961A (en) * | 2017-12-01 | 2018-05-15 | 周阳 | A kind of apparatus and method for automatically configuring high speed serialization transceiver parameters |
| CN109495519A (en) * | 2019-01-09 | 2019-03-19 | 天津芯海创科技有限公司 | Physical code circuit and high speed interface protocol exchange chip |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110493310B (en) * | 2019-07-17 | 2021-09-10 | 中国人民解放军战略支援部队信息工程大学 | Software defined protocol controller and method |
| CN110493310A (en) * | 2019-07-17 | 2019-11-22 | 中国人民解放军战略支援部队信息工程大学 | A kind of protocol controller and method of software definition |
| CN114731294B (en) * | 2020-01-21 | 2023-07-07 | 华为技术有限公司 | Exchange network chip and exchange equipment |
| CN114731294A (en) * | 2020-01-21 | 2022-07-08 | 华为技术有限公司 | Exchange network chip and exchange equipment |
| CN112685355A (en) * | 2021-01-11 | 2021-04-20 | 龙迅半导体（合肥）股份有限公司 | String adding device |
| CN112685355B (en) * | 2021-01-11 | 2022-03-18 | 龙迅半导体（合肥）股份有限公司 | String adding device |
| WO2022193328A1 (en) * | 2021-03-19 | 2022-09-22 | 华为技术有限公司 | Serializing/deserializing circuit, serial data receiving method, and chip |
| CN113572486A (en) * | 2021-06-29 | 2021-10-29 | 中国人民解放军战略支援部队信息工程大学 | Transmitter with low-speed SerDes interface, receiver with low-speed SerDes interface and circuit design method of transmitter |
| CN114143513A (en) * | 2021-12-29 | 2022-03-04 | 重庆紫光华山智安科技有限公司 | Multi-dimensional feature acquisition device and image acquisition method |
| WO2023125722A1 (en) * | 2021-12-31 | 2023-07-06 | 华为技术有限公司 | High-speed serial interface and data transmission method |
| CN114336197A (en) * | 2022-01-20 | 2022-04-12 | 深圳宏芯宇电子股份有限公司 | Interface conversion device, test board and card reader |
| CN114336197B (en) * | 2022-01-20 | 2024-03-08 | 深圳宏芯宇电子股份有限公司 | Interface conversion device, test board and card reader |
| CN114968875A (en) * | 2022-05-31 | 2022-08-30 | 重庆长安汽车股份有限公司 | Self-adaptive system supporting vehicle-mounted serial deserializing link and automatic driving automobile |
| CN114968875B (en) * | 2022-05-31 | 2023-08-25 | 重庆长安汽车股份有限公司 | Self-adaptive system supporting vehicle-mounted serial deserializing link and automatic driving automobile |
| CN115882870A (en) * | 2023-02-01 | 2023-03-31 | 井芯微电子技术(天津)有限公司 | High-speed serializer and deserializer integration method and electronic equipment |
| CN117539818A (en) * | 2024-01-10 | 2024-02-09 | 富瀚微电子(成都)有限公司 | Interface based on PHY model, chip integrating interface and chip simulation system |
| CN117539818B (en) * | 2024-01-10 | 2024-04-02 | 富瀚微电子(成都)有限公司 | Interface based on PHY model, chip integrating interface and chip simulation system |
| CN117749263A (en) * | 2024-02-08 | 2024-03-22 | 合肥国家实验室 | Receiving device based on space laser communication and space laser communication system |
| CN117749263B (en) * | 2024-02-08 | 2024-04-26 | 合肥国家实验室 | Receiving device based on space laser communication and space laser communication system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109947681B (en) | 2020-12-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109947681A (en) | Stringization/deserializer and high speed interface protocol exchange chip | |
| CN112260689B (en) | Sampling calibration method for self-adaptive delay compensation serial ADC sampling system | |
| CN101394678B (en) | Serialization/de-serialization interface module generally used in GEPON/GPON | |
| CN102057635B (en) | PLD architecture optimized for 10G Ethernet physical layer solution | |
| CN101252537B (en) | Switching network communicating system, method and master control board | |
| CN101951313B (en) | FPGA-based SFI4.1 device | |
| CN100527697C (en) | Means and a method for switching data packets or frames | |
| US20090135890A1 (en) | Physical layer device having an analog SERDES pass through mode | |
| CN108011694B (en) | A kind of efficient data exchange method based on FC | |
| US8732375B1 (en) | Multi-protocol configurable transceiver with independent channel-based PCS in an integrated circuit | |
| US9425824B2 (en) | Configurable multi-mode media independent interface | |
| CN108683536B (en) | Configurable dual-mode converged communication method of asynchronous network on chip and interface thereof | |
| CN102347904A (en) | Router equipment, main card thereof and method for adapting main card to interface card | |
| CN106250335B (en) | For providing the technology of data rate change | |
| JP6077097B2 (en) | Multiple serial media independent interface | |
| CN201910048U (en) | LVDS (Low Voltage Differential Signaling) node module | |
| CN101547054B (en) | Data receiving device of parallel optical inter-connected system based on programmable device and method thereof | |
| EP2498446B1 (en) | Method and apparatus compatible with 10ge lan port and wan port | |
| WO2018196833A1 (en) | Message sending method and message receiving method and apparatus | |
| CN208924235U (en) | Processor and network security device | |
| CN202103684U (en) | Digital circuit for realizing frame synchronization of STM-64 | |
| CN201499173U (en) | Data receiving device with low error rate and high flexibility | |
| CN102594454A (en) | Universal interface method for 10 GEPON (Gigabit Passive Optical Network) or XG-PON (XG-Passive Optical Network) OLT (Optical Line Terminal) or ONU (Optical Network Unit) SERDES (Serializer-Deserializer) | |
| CN219227609U (en) | JESD204B data transmission system based on optical fiber medium | |
| CN115269487B (en) | Inter-chip data high-speed transmission method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |