CN110493310B - Software defined protocol controller and method - Google Patents
Software defined protocol controller and method Download PDFInfo
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Abstract
The invention provides a software-defined protocol controller and a method. The protocol controller includes: the link layer transmitting side functional unit is used for carrying out packet caching and management on a data packet input by the user input interface, generating a control symbol and transmitting the data packet and the control symbol combination to the PCS input parallel bus; the link receiving side functional unit is used for separating data input into a control symbol and a data packet on the parallel bus by the PCS and outputting the data packet to the user output interface according to protocol specification; and the link layer state register is used for storing the state information of the link layer of the protocol controller. The method comprises the following steps: receiving a data packet input by a user input interface, carrying out packet caching and management, and selecting a data packet to be sent preferentially; generating a control symbol; sending the data packet and the control symbol to a PCS input parallel bus; separating the data into control symbols and data packets; and outputting the received data packet to a user output interface. The invention increases the flexibility of the communication interface.
Description
Technical Field
The invention relates to the technical field of high-speed serial communication, in particular to a device and a method of a software-defined protocol controller.
Background
At present, a high-speed serial interface is a main data communication mode between chips and between board cards and equipment due to fewer interface pins, high transmission rate, strong anti-interference performance and simple wiring and connection, and for example, a serial communication mode is adopted for data transmission in data centers, high-performance computing, radar processing systems, video monitoring systems and other infrastructures. However, under different application scenarios and requirements, the interface protocols for communication may be different, and commonly used interfaces include an Ethernet interface, a Fiber Channel interface, a RapidIO interface, a PCIe interface, and the like. In order to meet different requirements, more and more high-performance processing chips integrate multiple high-speed serial interface hard cores (IP cores), such as NXP T2080 DSP chips, and integrate multiple protocol controllers including Ethernet, PCIe, RapidIO and the like and SerDes with multiple frequency points, so that the applicability of the chips is improved, and meanwhile, the area and the power consumption of the chips are greatly increased. The traditional communication interface adopts an Application Specific Integrated Circuit (ASIC) implementation mode, and the protocol type is unchangeable, which greatly limits the use range of the whole Chip.
The traditional high-speed serial interface adopts rigid protocol analysis logic and can only support the interconnection communication of one or a class of protocols. The high-speed serial communication protocol generally consists of a plurality of layers of protocols, for example, an osi (open System interconnection) reference model is divided into seven layers, namely a physical layer (PMA + PCS module), a link layer (MAC), a network layer, a transport layer, a session layer, a presentation layer and an application layer, wherein the physical layer and the link layer form a protocol controller, mainly implement reliable transmission of protocol (data) packets, the functions of the protocol controller are generally implemented by using customized circuits, and other layers can currently implement software control. As shown in fig. 6, the conventional protocol controller structure: including the physical layer and the link layer, their main functions and implementations are as follows:
1) PMA + PCS module: the device is responsible for the functions of serial-parallel conversion, coding and decoding, bit width conversion, clock recovery, synchronization and the like of transmission words, and different protocols are mainly embodied in that the transmission rate, coding and decoding rules, bandwidth and the like have differences. Since the encoding rules of different protocols are relatively fixed and the PLL technology and clock recovery (SDR) technology supporting wideband point-to-multipoint protocols are relatively mature, the configurable ASIC circuit design is generally adopted for this part of functions. Wherein, PCS: the full name of Physical Coding Sublayer refers to a Physical Coding Sublayer; PMA: the full name of Physical Medium Attachment refers to the Physical media sublayer.
2) And the MAC module: the MAC is mainly responsible for link establishment and maintenance, protocol packet transceiving, parsing, error control, flow control, and the like, and is a functional module closely related to a protocol, different protocols have dedicated IP cores, and currently, there is no general solution.
The existing high-speed serial communication protocol is a transmission protocol based on packet switching, and link maintenance and reliable transmission of data packets are realized by adopting control symbols, so that the contents of the data packets and the control symbols are transmitted on a high-speed serial bus. In order to increase the speed and reduce the power consumption, the function of the link layer inside the protocol controller generally adopts ASIC design, and can only support the link establishment and the message transceiving function of one or a class of protocols, so the application range is also limited, and there are mainly 3 defects: (1) the protocol of the message processed by the port protocol controller is fixed and can not be changed according to the requirement; (2) in order to adapt to different application scenes, the conventional chip needs to integrate controllers with various protocols, so that the area and the cost of the chip are increased; (3) the self-defining protocol cannot be performed according to the requirement.
Disclosure of Invention
The invention provides a software-defined protocol controller and a method thereof, aiming at solving the problems that in the prior art, because a message protocol processed by a port protocol controller is fixed, the message protocol can not be changed according to requirements, the prior chip needs to integrate controllers with various protocols in order to adapt to different application scenes, the chip area and the cost are increased, the protocol can not be customized according to requirements, and the like.
In a first aspect, the present invention provides a software-defined protocol controller, the protocol controller comprising: a link layer transmitting side function unit, a link layer receiving side function unit and a link layer state register; wherein:
the link layer transmitting side functional unit is used for carrying out packet caching and management on data packets input by the user input interface, selecting the data packets to be transmitted preferentially according to priority, generating control symbols related to link maintenance and data packet receiving and transmitting, and transmitting the data packets and the control symbols to the PCS input parallel bus in a combined mode according to protocol regulations;
the link receiving side functional unit is used for receiving data input into the parallel bus by the PCS, separating the data input into control symbols and data packets on the parallel bus by the PCS, analyzing the control symbols and outputting the received data packets to the user output interface according to protocol specification;
and the link layer state register is used for storing the state information of the link layer of the protocol controller.
Further, the link layer transmitting side function unit includes: the device comprises a sending packet cache management module, a data packet sending module, a control symbol generating module and a control symbol and data packet merging module; wherein:
the sending packet cache management module is used for storing, classifying and scheduling data input by the user input interface; selecting a data packet to be sent preferentially according to a QoS rule specified by a protocol, and outputting the data packet to be sent preferentially to a data packet sending module;
the data packet sending module is used for receiving the data packet output by the sending packet cache management module, and calculating and inserting CRC in the data packet sending process;
the control symbol generating module is used for generating a control symbol according to the state information stored in the link layer state register;
and the control symbol and data merging module is used for selecting the data of the data packet sending module and the control symbol generating module according to the protocol specification to be combined and outputting the combined data to the PCS input parallel bus.
Further, the data packet sending module includes: a CRC insertion sub-module and a CRC calculation sub-module; wherein:
a CRC calculation sub-module for calculating CRC for the sent data packet by packet;
and a CRC insertion sub-module for inserting the CRC into the transmitted data packet according to the protocol.
Further, the control symbol generation module includes: the device comprises a first TCAM submodule, a control symbol memory, a first microcode instruction memory and a first microcode instruction execution submodule; wherein:
the first TCAM submodule is used for storing the value of a link layer state register of the protocol controller;
a control symbol memory for all control symbols specified by the protocol;
a first microcode instruction memory for storing logic operation instructions;
the first microcode instruction execution submodule is used for modifying the control symbol output by the control symbol memory according to the value of the current link layer state register and the logic operation instruction output by the first microcode instruction memory to obtain a final control symbol;
and searching a table according to the value output by the first TCAM submodule to obtain a unique address, and searching the table according to the unique address to obtain the control symbol and the logic operation instruction for generating the final control symbol.
Further, the link layer receiving side function unit includes: the device comprises a control symbol and data separation module, a control symbol analysis module, a data packet receiving module and a received packet cache management module; wherein:
and the control symbol and data separation module is used for judging the data type of the current PCS input parallel bus: if the data input into the parallel bus by the PCS is the control symbol at present, the data input into the parallel bus by the PCS is input into a control symbol analysis module; if the data input into the parallel bus by the PCS is a data packet at present, transmitting the data input into the parallel bus by the PCS to a data packet receiving module;
the control symbol analyzing module is used for analyzing the control symbols and extracting and processing commands and information in the control symbols;
the data packet receiving module is used for aligning and verifying the received data and sending the verified data and related verification information to the receiving packet cache management module;
and the receiving packet cache management module is used for storing, classifying and scheduling the data sent by the data packet receiving module, selecting the data packet sent preferentially according to the QoS rule and outputting the data packet sent preferentially to the user output interface.
Further, the data packet receiving module comprises: a data packet recombination submodule and a CRC (cyclic redundancy check) check submodule; wherein:
the data packet reorganization submodule is used for carrying out reorganization operation on the received data, the reorganization operation comprises aligning the received data according to the packet start information and the packet end information output by the control symbol analysis module, and inputting the aligned parallel data into the CRC (cyclic redundancy check) module;
and the CRC check submodule is used for checking the received data and writing the check result into the link layer state register.
Further, the controller parsing module comprises: the second TCAM sub-module, the second microcode instruction memory and the second microcode instruction execution sub-module; wherein:
the second TCAM submodule is used for storing all control symbols specified by the protocol;
a second microcode instruction memory for storing logic operation instructions;
the second microcode instruction execution submodule is used for operating the input control symbol and the value of the current link layer state register according to the logic operation instruction output by the second microcode instruction memory and storing the operation result to the link layer state register;
and the second TCAM submodule obtains a unique address according to the input control symbol and obtains the logic operation instruction for operation according to the unique address.
Further, the status information includes: at least one of receive control symbol information, transmit/receive control symbol count, transmit/receive packet count, and transmit/receive buffer idle information.
In a second aspect, the present invention provides a method for controlling a software-defined protocol controller, including:
step 1: receiving a data packet input by a user input interface, performing packet caching and management on the data packet, and selecting the data packet to be sent preferentially;
step 2: generating a control symbol related to link maintenance and data packet transceiving according to the state information of the link layer;
and step 3: sending the data packet and the control symbol to a PCS input parallel bus;
and 4, step 4: receiving data input by a PCS (personal communications System) on a parallel bus;
and 5: separating data input into parallel bus by PCS into control symbol and data packet;
step 6: analyzing the control symbol;
and 7: and recombining the received data packets and performing CRC (cyclic redundancy check) according to the analysis result of the control symbol, and outputting the correct data packets which pass the CRC to a user output interface in sequence according to the protocol specification and the priority of the data packets.
In a third aspect, the present invention provides an electronic device comprising:
the processor and the memory are communicated with each other through a bus; the memory stores program instructions executable by the processor, the processor invoking the program instructions to perform a method comprising: receiving a data packet input by a user input interface, performing packet caching and management on the data packet, and selecting the data packet to be sent preferentially; generating a control symbol related to link maintenance and data packet transceiving according to the state information of the link layer; sending the data packet and the control symbol to a PCS input parallel bus; receiving data input by a PCS (personal communications System) on a parallel bus; separating data input into parallel bus by PCS into control symbol and data packet; analyzing the control symbol; and recombining the received data packets and performing CRC (cyclic redundancy check) according to the analysis result of the control symbol, and outputting the correct data packets which pass the CRC to a user output interface in sequence according to the protocol specification and the priority of the data packets.
In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method of: receiving a data packet input by a user input interface, performing packet caching and management on the data packet, and selecting the data packet to be sent preferentially; generating a control symbol related to link maintenance and data packet transceiving according to the state information of the link layer; sending the data packet and the control symbol to a PCS input parallel bus; receiving data input by a PCS (personal communications System) on a parallel bus; separating data input into parallel bus by PCS into control symbol and data packet; analyzing the control symbol; and recombining the received data packets and performing CRC (cyclic redundancy check) according to the analysis result of the control symbol, and outputting the correct data packets which pass the CRC to a user output interface in sequence according to the protocol specification and the priority of the data packets.
The invention has the beneficial effects that:
the protocol controller and the method defined by the software can customize the hardware of the protocol controller by adopting a software programming mode according to the protocol requirement, greatly increase the practicability and the universality of an interface, and compared with the existing scheme of a fixed protocol controller, the protocol controller has the following advantages: (1) the protocol type of the controller can be changed according to requirements; (2) adding or deleting control symbols, data packet formats and the like according to the user requirements to realize customized protocol communication; (3) greatly improved flexibility and practicality in a variety of protocol applications.
Drawings
Fig. 1 is a schematic structural diagram of a software-defined protocol controller according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a control symbol generation module and a control symbol parsing module according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a data packet sending module and a data packet receiving module according to an embodiment of the present invention;
fig. 4 is a flowchart illustrating a control method of a software-defined protocol controller according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a conventional protocol controller provided in the prior art.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
By analyzing the functions of the link layers of different protocols, the link layer mainly completes link maintenance and packet transceiving, wherein the link maintenance is generally realized by several control symbols or control sequences with relatively fixed formats, such as a packet start control symbol, an end control symbol, a state control symbol, a link request control symbol, a link response control symbol, a packet acknowledgement control symbol, and the like of the RapidIO protocol. The link layer realizes the maintenance of the link and the receiving and sending of the packets by receiving and sending corresponding control symbols; the receiving and sending function of the packet is mainly that the receiving end judges the start and the end of the data packet according to the start control symbol and the end control symbol of the packet, the input parallel data is aligned, recombined and checked, and according to the check result, the receiving process of the packet triggers the sending side to send the corresponding control symbol to inform the opposite end interface whether the data packet is received correctly or has errors; and at a sending end, sequentially sending the data packets in the sending packet buffer according to the bit width of the data path in the link, adding a packet start control symbol to a data packet head in the process of sending the data packets, and adding an end control symbol to a packet tail, wherein the control symbol and the data packets share a parallel data transceiving path between a link layer and a PCS layer. By analyzing the functions of the link layer, the invention provides a new protocol controller architecture based on software definition.
The software defined protocol controller provided by the embodiment of the invention comprises: a link layer transmitting side function unit, a link layer receiving side function unit and a link layer state register; wherein:
the link layer transmitting side functional unit is used for carrying out packet caching and management on data packets input by the user input interface, selecting the data packets to be transmitted preferentially according to priority, generating control symbols related to link maintenance and data packet receiving and transmitting, and transmitting the data packets and the control symbols to the PCS input parallel bus in a combined mode according to protocol regulations;
the link receiving side functional unit is used for receiving data input into the parallel bus by the PCS, separating the data input into control symbols and data packets on the parallel bus by the PCS, analyzing the control symbols and outputting the received data packets to the user output interface according to protocol specification;
and the link layer state register is used for storing the state information of the link layer of the protocol controller.
Specifically, the protocol controller provided in the embodiment of the present invention has a workflow as follows: firstly, a link layer transmitting side functional unit receives a data packet input by a user input interface, performs packet caching and management on the data packet, and selects a data packet to be transmitted preferentially; then, the link layer transmitting side functional unit generates a control symbol related to link maintenance and data packet receiving and transmitting according to the state information of the link layer, and transmits the data packet needing to be transmitted preferentially and the generated control symbol to a PCS input parallel bus; then, the link receiving side functional unit receives data input by the PCS into the parallel bus, separates the data input by the PCS into control symbols and data packets, and recombines the separated data packets to form complete data packets to be stored in a cache; and finally, the link receiving side functional unit analyzes the control symbol and outputs the received data packet to the user output interface according to the protocol specification according to the analysis result of the control symbol.
Wherein, PCS: the full name of Physical Coding Sublayer refers to a Physical Coding Sublayer;
as shown in fig. 1, an embodiment of the present invention provides a software-defined protocol controller, including: a link layer transmitting side functional unit 11, a link layer receiving side functional unit 12, and a link layer status register 13. Wherein:
the link layer transmitting side functional unit 11 includes: a sending packet buffer management module 111, a data packet sending module 112, a control symbol generating module 113 and a control symbol and data merging module 114; the transmission packet buffer management module 111 is used for storing, classifying and scheduling data input by the user input interface; selecting a data packet to be sent preferentially according to a QoS rule specified by a protocol, and outputting the data packet to be sent preferentially to the data packet sending module 112; the packet sending module 112 is configured to receive a packet output by the packet sending buffer management module 111, and calculate and insert CRC in the packet sending process; the control symbol generating module 113 is configured to generate a control symbol according to the state information stored in the link layer state register 13; the control symbol and data merging module 114 is configured to select data of the data packet sending module 112 and the control symbol generating module 113 according to a protocol specification, combine the data, and output the combined data to the PCS input parallel bus.
The link layer receiving side functional unit 12 includes: a control symbol and data separation module 121, a control symbol analysis module 122, a data packet receiving module 123 and a received packet cache management module 124; the control symbol and data separation module 121 is used to determine the data type of the current PCS input parallel bus: if the data of the current PCS input parallel bus is a control symbol, the data of the PCS input parallel bus is input to the control symbol analyzing module 122; if the data on the current PCS input parallel bus is a data packet, the data on the PCS input parallel bus is transmitted to the data packet receiving module 123; the control symbol parsing module 122 is configured to parse the control symbol, extract and process the command and information in the control symbol; the data packet receiving module 123 is configured to align and check the received data, and send the checked data and relevant check information to the receiving packet cache management module 124; the received packet buffer management module 124 is configured to store, classify, and schedule data sent by the data packet receiving module 123, select a data packet to be sent preferentially according to the QoS rule, and output the data packet to be sent preferentially to the user output interface.
Specifically, the working flow of the protocol controller provided by the embodiment of the present invention at the sending side is as follows: firstly, the sending packet buffer management module 111 receives data input by a user through a user input interface, and stores, classifies and schedules the input data; and selects the data packet to be sent preferentially according to the QoS rule, and outputs the data packet to the data packet sending module 112; then, the data packet sending module 112 receives the data packet output by the sending packet buffer management module 111, sends the received data packet to the control symbol and data combining module 114, and calculates and inserts CRC in the data packet sending process; then, the control symbol generating module 113 generates a control symbol according to the status information stored in the link layer status register 13, and sends the control symbol to the control symbol and data combining module 114; finally, the control symbol and data combination module 114 receives the data packet output by the data packet transmission module 112 and the control symbol output by the control symbol generation module 113, and outputs the received data of the two modules to the PCS input parallel bus.
The working process of the protocol controller at the receiving side of the embodiment of the invention is as follows: first, the control symbol and data separation module 121 receives data input by the PCS on the parallel bus, and determines the type of data input by the PCS on the parallel bus: if the data of the current PCS input parallel bus is a control symbol, the data of the PCS input parallel bus is input to the control symbol analyzing module 122; if the data on the current PCS input parallel bus is a data packet, the data on the PCS input parallel bus is transmitted to the data packet receiving module 123; then, the control symbol analyzing module 122 receives the control symbol output by the control symbol and data separating module 121, analyzes the control symbol, and extracts and processes the command and information in the control symbol; next, the data packet receiving module 123 receives the data packet output by the control symbol and data separating module 121, aligns and verifies the received parallel data, and sends the verified parallel data and the related verification information to the receiving packet cache management module 124; finally, the received packet buffer management module 124 receives the data output by the data packet receiving module 123, selects the data packet to be preferentially sent according to the QoS rule, and outputs the data packet to be preferentially sent to the user output interface.
The following example explains that the controller parsing module 122 extracts and processes commands and information in the controller: for example, the start of packet control symbol, the control symbol parsing module 122 needs to inform the data packet receiving module 123 that the data following the start of packet control symbol is the beginning of the data packet. If the control symbol is the link state request control symbol, the transmitting side needs to be triggered to transmit the state control symbol according to the current state. If the packet is the ack control symbol, the credit register needs to be updated or the sending packet buffer management module needs to be informed to release the corresponding storage space according to the definition of different protocols.
The link layer status register 13 stores status information including: at least one of receive control symbol information, transmit/receive control symbol count, transmit/receive packet count, and transmit/receive buffer idle information.
Wherein, QoS: the full Quality of Service refers to the Quality of Service.
In addition, the transmission packet buffer management module 111 needs to implement flow control in cooperation with the controller analysis module 122 on the receiving side.
On the basis of the above embodiments, as shown in fig. 2, an embodiment of the present invention provides a controller generating module 113 and a controller parsing module 122. Wherein:
the control symbol generation module 113 includes: a first TCAM sub-module 1131, a control symbol memory 1132, a first microcode instruction memory 1133, and a first microcode instruction execution sub-module 1134; the first TCAM submodule 1131 is configured to store a value of the protocol controller link layer status register 13; a control symbol memory 1132 for all control symbols specified by the protocol; the first microcode instruction memory 1133 is used for storing a logic operation instruction; the first microcode instruction execution submodule 1134 is configured to modify the control symbol output by the control symbol memory 1132 according to the value of the current link layer status register 13 and the logic operation instruction output by the first microcode instruction memory 1133 to obtain a final control symbol; a unique address is obtained according to a table lookup of values output by the first TCAM submodule 1131, and the control symbol and the logical operation instruction for generating the final control symbol are obtained according to the unique address table lookup.
The controller parsing module 122 includes: a second TCAM submodule 1221, a second microcode instruction memory 1222, and a second microcode instruction execution submodule 1223; the second TCAM sub-module 1221 is configured to store all control symbols specified by the protocol; the second microcode instruction memory 1222 is used to store logic operation instructions; the second microcode instruction execution submodule 1223 is configured to perform an operation on the input control symbol and the value of the current link layer status register 13 according to the logic operation instruction output by the second microcode instruction storage 1222, and store the operation result in the link layer status register 13; the second TCAM sub-module 1131 obtains a unique address according to the input control symbol, and obtains the logical operation instruction for performing operation according to the unique address.
Specifically, in the control symbol generation module 113, the first TCAM submodule 1131 stores the content of the status register related to the link layer of the protocol controller, and first, according to the value of the status register, the first TCAM submodule 1131 may output a unique address through table lookup, where the address simultaneously indexes the first microcode instruction memory 1133 and the control symbol memory 1132, and the control symbol memory 1132 stores all the control symbols of the protocol; then, the control symbol memory 1132 may output an initial control symbol to the first microcode instruction execution sub-module 1134 according to the address through table lookup, and the first microcode instruction memory 1133 may output a microcode instruction for logic operation to the first microcode instruction execution sub-module 1134 according to the address through table lookup; finally, the first microcode instruction execution sub-module 1134 modifies the initial control symbol according to the value of the current link layer status register 13 and the microcode instruction, outputs the final control symbol, and updates the value of the relevant status register at the same time.
In the control symbol parsing module 122, the second TCAM submodule 1221 stores all the control symbols of the protocol, and first, the second TCAM submodule 1221 obtains a unique address through table lookup according to the input control symbols, and the address indexes the second microcode instruction memory 1222; then, the second microcode instruction memory 1222 can output the corresponding microcode instruction to the second microcode execution sub-module according to the address through table lookup; finally, the second microcode instruction execution submodule 1223 performs corresponding operation on the value of the current link layer status register 13 and the input control symbol according to the microcode instruction, and writes the operation result into the corresponding link layer status register 13.
The microcode instruction mainly comprises an instruction which can carry out logic operations such as addition, subtraction, AND, OR, XOR, shift, setting, clearing and the like on any bit section of input data of the microcode instruction execution submodule.
TCAM: all called Ternary Content addressable memory, is a type of tri-state Content addressable memory.
It should be noted that the difference between link layers of different protocols is mainly reflected in the difference between the control symbols and the packet formats, but the control symbols and the packet formats of each protocol are relatively fixed.
As can be seen from the above, in the embodiment of the present invention, the TCAM + programmable microcode instruction is used to implement the parsing of the control symbol at the receiving end and the generation of the control symbol at the sending end, and the control symbol at the link layer can be programmed and customized according to the requirement of the protocol to implement the software defined protocol controller.
On the basis of the above embodiments, as shown in fig. 3, an embodiment of the present invention provides a packet sending module 112 and a packet receiving module 123 that can be configured as needed. Wherein:
the packet sending module 112 includes: a CRC calculation sub-module 1121 and a CRC insertion sub-module 1122; the CRC calculation sub-module 1121 is configured to calculate a CRC for each packet of the received data; CRC insertion sub-module 1122 is used to insert the CRC in the transmitted packet as specified by the protocol.
The packet receiving module 123 includes: a data packet recombination submodule 1231 and a CRC check submodule 1232; the data packet reassembly sub-module 1231 is configured to perform reassembly operations on the received data, where the reassembly operations include aligning the received data according to the packet start information and the packet end information output by the control symbol parsing module 122, and inputting the aligned parallel data to the CRC check module; the CRC check submodule 1232 is configured to check the received data, and write a check result into the link layer status register 13.
Specifically, the data packet sending module 112 mainly completes CRC calculation, counting and sending of the data packet; the data packet receiving module 123 mainly completes the reassembly, counting and checking of parallel data.
On the transmitting side: firstly, the CRC calculation submodule 1121 performs CRC calculation on input parallel data by packet; CRC insertion sub-module 1122 then adds the calculated CRC to the packet or end according to protocol specifications to complete encapsulation of the link layer packet.
On the receiving side: firstly, the data packet reassembly sub-module 1231 reassembles the input parallel data according to the input parallel data and the corresponding control symbol information, the reassembly operation includes aligning the input parallel data (which may have bubbles in the middle) according to the packet start information and the packet end information given by the control symbol parsing module 122, and the aligned parallel data is input to the CRC check sub-module 1232; then, the CRC check submodule 1232 receives the data output by the packet reassembly submodule 1231, checks the data, and writes the check result into the corresponding link layer status register 13.
It should be noted that, both the packet receiving module 123 and the packet sending module 112 will count the length of the packet, so as to ensure that the total length of the received and sent packets is not greater than the maximum packet length required by the protocol.
As can be seen from the above, the embodiment of the present invention can customize the length of the data packet and the CRC calculation rule according to the requirement of the protocol, so as to implement the software defined protocol controller.
As shown in fig. 4, an embodiment of the present invention provides a method for controlling a software-defined protocol controller, where the method includes:
s101: the protocol controller receives a data packet input by a user input interface, performs packet caching and management on the data packet, and selects a data packet to be sent preferentially;
s102: the protocol controller generates a control symbol related to link maintenance and data packet receiving and transmitting according to the state information of the link layer;
s103: the protocol controller sends the data packet and the control symbol to a PCS input parallel bus;
s104: the protocol controller receives data input by the PCS on the parallel bus;
s105: the protocol controller separates data input by the PCS into control symbols and data packets;
s106: the protocol controller analyzes the control symbol;
s107: the protocol controller carries out recombination and CRC check on the received data packets according to the analysis result of the control symbol, and outputs correct data packets passing through the CRC check to the user output interface in sequence according to the protocol specification and the priority of the data packets.
Fig. 5 is a block diagram of an electronic device according to an embodiment of the present invention. As shown in fig. 5, the electronic apparatus includes: a memory 502 and a processor 501, wherein the processor 501 and the memory 502 are communicated with each other through a bus 503; the memory 502 stores program instructions executable by the processor, which the processor 501 calls to perform a method, for example, comprising: receiving a data packet input by a user input interface, performing packet caching and management on the data packet, and selecting the data packet to be sent preferentially; generating a control symbol related to link maintenance and data packet transceiving according to the state information of the link layer; sending the data packet and the control symbol to a PCS input parallel bus; receiving data input by a PCS (personal communications System) on a parallel bus; separating data input into parallel bus by PCS into control symbol and data packet; analyzing the control symbol; and recombining the received data packets and performing CRC (cyclic redundancy check) according to the analysis result of the control symbol, and outputting the correct data packets which pass the CRC to a user output interface in sequence according to the protocol specification and the priority of the data packets.
Embodiments of the present invention also provide a computer program product, the computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions, which when executed by a computer, enable the computer to perform the methods provided by the above-mentioned method embodiments, for example, including: receiving a data packet input by a user input interface, performing packet caching and management on the data packet, and selecting the data packet to be sent preferentially; generating a control symbol related to link maintenance and data packet transceiving according to the state information of the link layer; sending the data packet and the control symbol to a PCS input parallel bus; receiving data input by a PCS (personal communications System) on a parallel bus; separating data input into parallel bus by PCS into control symbol and data packet; analyzing the control symbol; and recombining the received data packets and performing CRC (cyclic redundancy check) according to the analysis result of the control symbol, and outputting the correct data packets which pass the CRC to a user output interface in sequence according to the protocol specification and the priority of the data packets.
An embodiment of the present invention further provides a computer-readable storage medium, where the computer-readable storage medium stores computer instructions, and the computer instructions enable the computer to execute the method provided by each of the above method embodiments, for example, including: receiving a data packet input by a user input interface, performing packet caching and management on the data packet, and selecting the data packet to be sent preferentially; generating a control symbol related to link maintenance and data packet transceiving according to the state information of the link layer; sending the data packet and the control symbol to a PCS input parallel bus; receiving data input by a PCS (personal communications System) on a parallel bus; separating data input into parallel bus by PCS into control symbol and data packet; analyzing the control symbol; and recombining the received data packets and performing CRC (cyclic redundancy check) according to the analysis result of the control symbol, and outputting the correct data packets which pass the CRC to a user output interface in sequence according to the protocol specification and the priority of the data packets.
The heterogeneous protocol terminals are interconnected and intercommunicated, and a Field Programmable Gate Array (FPGA) scheme can be used, but the FPGA is a fine-grained programmable device, has high resource consumption and large area, and is not suitable for being integrated on a traditional processor chip. Compared with the scheme based on the FPGA, the protocol controller framework supports software definition, the protocol type supported by the protocol controller can be changed through software programming, the implementation mode is flexible, and the modification is simple.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A software defined protocol controller, comprising: a link layer transmitting side function unit, a link layer receiving side function unit and a link layer state register; wherein:
the link layer transmitting side functional unit is used for carrying out packet caching and management on data packets input by the user input interface, selecting the data packets to be transmitted preferentially according to priority, generating control symbols related to link maintenance and data packet receiving and transmitting, and transmitting the data packets and the control symbols to the PCS input parallel bus in a combined mode according to protocol regulations;
the link receiving side functional unit is used for receiving data input into the parallel bus by the PCS, separating the data input into control symbols and data packets on the parallel bus by the PCS, analyzing the control symbols and outputting the received data packets to the user output interface according to protocol specification;
and the link layer state register is used for storing the state information of the link layer of the protocol controller.
2. The protocol controller according to claim 1, wherein the link layer transmit side functional unit comprises: the device comprises a sending packet cache management module, a data packet sending module, a control symbol generating module and a control symbol and data packet merging module; wherein:
the sending packet cache management module is used for storing, classifying and scheduling data input by the user input interface; selecting a data packet to be sent preferentially according to a QoS rule specified by a protocol, and outputting the data packet to be sent preferentially to a data packet sending module;
the data packet sending module is used for receiving the data packet output by the sending packet cache management module, and calculating and inserting CRC in the data packet sending process;
the control symbol generating module is used for generating a control symbol according to the state information stored in the link layer state register;
and the control symbol and data merging module is used for selecting the data of the data packet sending module and the control symbol generating module according to the protocol specification to be combined and outputting the combined data to the PCS input parallel bus.
3. The protocol controller according to claim 2, wherein the packet transmission module comprises: a CRC calculation sub-module and a CRC insertion sub-module; wherein:
a CRC calculation sub-module for calculating CRC for the received data packet by packet;
a CRC insertion sub-module for inserting the CRC in a transmitted data packet according to a protocol specification.
4. The protocol controller of claim 2, wherein the control symbol generation module comprises: the device comprises a first TCAM submodule, a control symbol memory, a first microcode instruction memory and a first microcode instruction execution submodule; wherein:
the first TCAM submodule is used for storing the value of a link layer state register of the protocol controller;
a control symbol memory for storing all control symbols prescribed by the protocol;
a first microcode instruction memory for storing logic operation instructions;
the first microcode instruction execution submodule is used for modifying the control symbol output by the control symbol memory according to the value of the current link layer state register and the logic operation instruction output by the first microcode instruction memory to obtain a final control symbol;
and searching a table according to the value output by the first TCAM submodule to obtain a unique address, and searching the table according to the unique address to obtain the control symbol and the logic operation instruction for generating the final control symbol.
5. The protocol controller according to any of claims 1 to 4, wherein the link layer receive side functional unit comprises: the device comprises a control symbol and data separation module, a control symbol analysis module, a data packet receiving module and a received packet cache management module; wherein:
and the control symbol and data separation module is used for judging the data type of the current PCS input parallel bus: if the data input into the parallel bus by the PCS is the control symbol at present, the data input into the parallel bus by the PCS is input into a control symbol analysis module; if the data input into the parallel bus by the PCS is a data packet at present, transmitting the data input into the parallel bus by the PCS to a data packet receiving module;
the control symbol analyzing module is used for analyzing the control symbols and extracting and processing commands and information in the control symbols;
the data packet receiving module is used for aligning and verifying the received data and sending the verified data and related verification information to the receiving packet cache management module;
and the receiving packet cache management module is used for storing, classifying and scheduling the data sent by the data packet receiving module, selecting the data packet sent preferentially according to the QoS rule and outputting the data packet sent preferentially to the user output interface.
6. The protocol controller according to claim 5, wherein the packet receiving module comprises: a data packet recombination submodule and a CRC (cyclic redundancy check) check submodule; wherein:
the data packet reorganization submodule is used for carrying out reorganization operation on the received data, the reorganization operation comprises aligning the received data according to the packet start information and the packet end information output by the control symbol analysis module, and inputting the aligned parallel data into the CRC (cyclic redundancy check) module;
and the CRC check submodule is used for checking the received data and writing the check result into the link layer state register.
7. The protocol controller of claim 5, wherein the controller parsing module comprises: the second TCAM sub-module, the second microcode instruction memory and the second microcode instruction execution sub-module; wherein:
the second TCAM submodule is used for storing all control symbols specified by the protocol;
a second microcode instruction memory for storing logic operation instructions;
the second microcode instruction execution submodule is used for operating the input control symbol and the value of the current link layer state register according to the logic operation instruction output by the second microcode instruction memory and storing the operation result to the link layer state register;
and the second TCAM submodule obtains a unique address according to the input control symbol and obtains the logic operation instruction for operation according to the unique address.
8. The protocol controller of claim 1, wherein the status information comprises: at least one of receive control symbol information, transmit/receive control symbol count, transmit/receive packet count, and transmit/receive buffer idle information.
9. A method for controlling a software defined protocol controller, comprising:
step 1: receiving a data packet input by a user input interface, performing packet caching and management on the data packet, and selecting the data packet to be sent preferentially;
step 2: generating a control symbol related to link maintenance and data packet transceiving according to the state information of the link layer;
and step 3: sending the data packet and the control symbol to a PCS input parallel bus;
and 4, step 4: receiving data input by a PCS (personal communications System) on a parallel bus;
and 5: separating data input into parallel bus by PCS into control symbol and data packet;
step 6: analyzing the control symbol;
and 7: and recombining the received data packets and performing CRC (cyclic redundancy check) according to the analysis result of the control symbol, and outputting the correct data packets which pass the CRC to a user output interface in sequence according to the protocol specification and the priority of the data packets.
10. An electronic device, comprising:
the processor and the memory are communicated with each other through a bus; the memory stores program instructions executable by the processor, the processor invoking the program instructions to perform the method of claim 9.
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| CN114546495B (en) * | 2021-09-03 | 2022-12-20 | 北京睿芯众核科技有限公司 | Method and system for checking address attribute of RISC-V architecture processor |
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