CN109947681B - Serializer/deserializer and high-speed interface protocol exchange chip - Google Patents
Serializer/deserializer and high-speed interface protocol exchange chip Download PDFInfo
- Publication number
- CN109947681B CN109947681B CN201910212722.6A CN201910212722A CN109947681B CN 109947681 B CN109947681 B CN 109947681B CN 201910212722 A CN201910212722 A CN 201910212722A CN 109947681 B CN109947681 B CN 109947681B
- Authority
- CN
- China
- Prior art keywords
- circuit
- serializer
- deserializer
- configuration
- protocol
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Communication Control (AREA)
Abstract
The invention provides a serializer/deserializer and a high-speed interface protocol exchange chip; the serializer/deserializer comprises a configuration management circuit and a set number of serializing/deserializing circuits; the serialization/deserialization circuit comprises a receiver, a transmitter and a clock management circuit; the configuration management circuit receives a configuration instruction sent by the software definition control circuit; setting each serialization/deserialization circuit according to the configuration instruction; the clock management circuit outputs a clock signal corresponding to the configuration instruction to the receiver and the transmitter; the receiver converts serial data sent by an external physical link into parallel data according to a high-speed interface protocol corresponding to the configuration instruction, and then sends the parallel data to the physical coding circuit; and the transmitter converts the parallel data sent by the physical coding circuit into serial data according to a high-speed interface protocol corresponding to the configuration instruction and then sends the serial data to an external physical link. The invention improves the applicability of the serializer/deserializer to various high-speed interface protocols and improves the efficiency.
Description
Technical Field
The present invention relates to the technical field of high-speed interface protocols, and in particular, to a serializer/deserializer and a high-speed interface protocol exchange chip.
Background
Most high-speed serial interface protocol circuits currently in the industry generally have data processing granularity divided into three hierarchies, namely a transmission transaction layer, a data link layer and a physical transmission sub-layer, and a SerDes (Serializer/Deserializer) circuit is a core component of a high-speed serial protocol interface; the SerDes circuit is responsible for converting the digital signals of the high-speed protocol serial interface into high-speed analog differential signals and then carrying out physical transmission. For different types of protocol structures, the functions and performances of the required physical layer specifications are different, so that each protocol interface carries out differential design on the SerDes component of the protocol interface. The SerDes design of the existing high-speed serial protocol interface is mainly designed according to the function and performance requirements of the physical specification of the protocol, and other protocol interfaces cannot be directly matched and applied. Therefore, when designing different protocol interfaces, SerDes needs to be designed and adjusted, and the working efficiency is low.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a serializer/deserializer and a high-speed interface protocol switching chip, so as to improve the applicability of the serializer/deserializer to various high-speed interface protocols and improve the efficiency.
In a first aspect, an embodiment of the present invention provides a serializer/deserializer, where the serializer/deserializer is disposed in a high-speed interface protocol exchange chip; the serializer/deserializer is respectively connected with the physical coding circuit, the software defined control circuit and the external physical link; the serializer/deserializer comprises a configuration management circuit and a set number of serializing/deserializing circuits; the configuration management circuit is respectively connected with the serialization/deserialization circuit; the serialization/deserialization circuit comprises a receiver, a transmitter and a clock management circuit; the clock management circuit is respectively connected with the receiver and the transmitter; the configuration management circuit is used for receiving a configuration instruction sent by the software-defined control circuit; setting each serialization/deserialization circuit according to the configuration instruction; the clock management circuit is used for outputting a clock signal corresponding to the configuration instruction to the receiver and the transmitter; the receiver is used for converting serial data sent by an external physical link into parallel data according to a high-speed interface protocol corresponding to the configuration instruction and sending the parallel data to the physical coding circuit; and the transmitter is used for converting the parallel data sent by the physical coding circuit into serial data according to a high-speed interface protocol corresponding to the configuration instruction and sending the serial data to an external physical link.
With reference to the first aspect, an embodiment of the present invention provides a first possible implementation manner of the first aspect, where the configuration instruction includes a plurality of configuration subcommands; the configuration management circuit sets a serial/deserializing circuit corresponding to the configuration sub-command; the configuration subcommands include clock frequency, parallel bit width, and channel selection.
With reference to the first aspect, an embodiment of the present invention provides a second possible implementation manner of the first aspect, where the high-speed interface protocol includes one or more of an FC-AE-ASM protocol, a RapidIO3.0 protocol, a 10GBASE-KR protocol, and a 1000BASE-X protocol.
With reference to the second possible implementation manner of the first aspect, an embodiment of the present invention provides a third possible implementation manner of the first aspect, where the receiver includes a multi-gradient swing adjusting circuit, a receiving equalizing circuit, a clock data recovery circuit, a serial-to-parallel conversion circuit, a PRBS detecting circuit, and a first data bit width conversion circuit, which are connected in sequence; the configuration management circuit is connected with the first data bit width conversion circuit; the configuration management circuit outputs a control signal to set the parallel bit width of the first data bit width conversion circuit.
With reference to the third possible implementation manner of the first aspect, an embodiment of the present invention provides a fourth possible implementation manner of the first aspect, wherein the serializing/deserializing circuit further includes a first receiving differential port and a second receiving differential port; the first receiving differential port and the second receiving differential port are connected with the multi-gradient swing amplitude adjusting circuit; the multi-gradient swing adjusting circuit receives serial data sent by an external physical link through a first receiving differential port and a second receiving differential port.
With reference to the second possible implementation manner of the first aspect, an embodiment of the present invention provides a fifth possible implementation manner of the first aspect, where the transmitter includes a second data bit width conversion circuit, a first selector, an asynchronous cache circuit, a second selector, a parallel-to-serial conversion circuit, a pre-emphasis circuit, and a driver, which are connected in sequence; the transmitter further includes a PRBS sequence source circuit; the PRBS sequence source circuit is connected with the input end of the first selector; the first selector and the second selector are either one-out-of-two selectors; two input ends of the first selector are respectively connected with the PRBS sequence source circuit and the second data bit width conversion circuit; the output end of the first selector is connected with the asynchronous cache circuit; two input ends of the second selector are respectively connected with the parallel-serial conversion circuit and the asynchronous cache circuit; the output end of the second selector is connected with the parallel-serial conversion circuit; the configuration management circuit is respectively connected with the selection end of the first selector, the selection end of the second selector and the second data bit width conversion circuit; the configuration management circuit outputs a control signal to control output signals of output ends of the first selector and the second selector; the configuration management circuit outputs a control signal to set the parallel bit width of the second data bit width conversion circuit.
With reference to the fifth possible implementation manner of the first aspect, an embodiment of the present invention provides a sixth possible implementation manner of the first aspect, wherein the serializing/deserializing circuit further includes a first sending differential port and a second sending differential port; the first sending differential port and the second sending differential port are connected with the pre-emphasis circuit; the pre-emphasis circuit sends the parallel data to the external physical link through the first sending differential port and the second sending differential port.
With reference to the first aspect, an embodiment of the present invention provides a seventh possible implementation manner of the first aspect, where the apparatus further includes a reset circuit; the reset circuit is respectively connected with the configuration management circuit and the serialization/deserialization circuit; the reset circuit is used for carrying out hard reset on the configuration management circuit and the serialization/deserialization circuit when receiving a reset signal.
With reference to the first aspect, an embodiment of the present invention provides an eighth possible implementation manner of the first aspect, where the serializing/deserializing circuit further includes a configuration interface; the configuration interface is connected with the configuration management circuit; the configuration management circuit is in signal transmission with the software defined control circuit through the configuration interface.
In a second aspect, an embodiment of the present invention further provides a high-speed interface protocol exchange chip, which includes a software-defined control circuit, a serializer/deserializer, a physical coding circuit, a data link circuit, and a transmission transaction circuit, which are sequentially connected to each other.
The embodiment of the invention has the following beneficial effects:
the embodiment of the invention provides a serializer/deserializer and a high-speed interface protocol exchange chip; the serializer/deserializer comprises a configuration management circuit and a set number of serializing/deserializing circuits; the serialization/deserialization circuit comprises a receiver, a transmitter and a clock management circuit; the configuration management circuit receives a configuration instruction sent by the software definition control circuit; setting each serialization/deserialization circuit according to the configuration instruction; the clock management circuit outputs a clock signal corresponding to the configuration instruction to the receiver and the transmitter; the receiver converts serial data sent by an external physical link into parallel data according to a high-speed interface protocol corresponding to the configuration instruction, and then sends the parallel data to the physical coding circuit; and the transmitter converts the parallel data sent by the physical coding circuit into serial data according to a high-speed interface protocol corresponding to the configuration instruction and then sends the serial data to an external physical link. The method improves the applicability of the serializer/deserializer to various high-speed interface protocols and improves the efficiency.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention as set forth above.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a high-speed serial interface protocol circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a serializer/deserializer according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating a relationship between data and control of each functional module in a multi-channel SerDes structure based on a multi-protocol architecture according to an embodiment of the present invention;
fig. 4 is a data flow diagram of a multi-channel SerDes structure of a multi-protocol architecture provided in the embodiment of the present invention in a 4X mode;
fig. 5 is a data flow diagram of a multi-channel SerDes structure of a multi-protocol architecture provided in the embodiment of the present invention in a 2X +2X mode;
fig. 6 is a data flow diagram of a multi-channel SerDes structure of a multi-protocol architecture provided in the embodiment of the present invention in a 2X +1X mode;
fig. 7 is a data flow diagram of a multi-channel SerDes structure of a multi-protocol architecture provided in an embodiment of the present invention in a 1X +2X mode;
fig. 8 is a data flow diagram of a multi-channel SerDes structure of a multi-protocol architecture provided in the embodiment of the present invention in a 1X +1X mode;
fig. 9 is a schematic structural diagram of a high speed interface protocol switching chip according to an embodiment of the present invention.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
With the increasing demand of data processing platforms for data transmission bandwidth and the development of various high-speed serial protocols, there is a need for a heterogeneous protocol interconnection switching chip that can implement non-blocking, low-delay, highly reliable and flexible switching between any two protocols. The high-speed protocol serial interface of the chip requires heterogeneous design and meets the functional performance requirements of various protocols. High speed serial link systems have gradually replaced parallel link systems and become the primary transmission mode for high speed data links. The serial interface adopts a differential signal transmission mode, so that the serial interface has the advantages of longer transmission distance, larger transmission bandwidth, better signal quality and the like compared with a parallel link. The SerDes circuit is a core component of a high-speed serial protocol interface, and the performance of one high-speed protocol interface is good or bad and mostly depends on the SerDes performance.
In most high-speed serial interface protocol circuits currently in the industry, data processing granularity is generally divided into three hierarchies, namely a transmission transaction layer, a data link layer and a physical transmission sublayer, and a SerDes circuit is located in the physical transmission sublayer of a high-speed protocol interface, as shown in fig. 1; the SerDes circuit is responsible for converting the digital signals of the high-speed protocol serial interface into high-speed analog differential signals and then carrying out physical transmission. For different types of protocol structures, the functions and performances of the required physical layer specifications are different, so that each protocol interface carries out differential design on the SerDes component of the protocol interface. At present, a serial interface compatible with a plurality of protocols does not exist, so that the design of a multi-channel SerDes structure capable of meeting the requirements of a plurality of protocols is the premise of supporting a multi-protocol high-speed serial protocol.
The SerDes design of the existing high-speed serial protocol interface is mainly designed according to the function and performance requirements of the physical specification of the protocol, and other protocol interfaces cannot be directly matched and applied. Therefore, the SerDes needs to be designed and adjusted when different protocol interfaces are designed, and the requirement of software definition of multi-protocol-based multi-channel SerDes function cannot be supported.
The invention integrates the functional performance requirements of a plurality of protocols to carry out normalization design, thereby constructing a multi-protocol architecture-based multi-channel SerDes structure serving in a multi-protocol compatible high-speed serial interface of an exchange chip interconnected by heterogeneous protocols.
Based on this, the embodiment of the invention provides a serializer/deserializer and a high-speed interface protocol exchange chip, which can be applied to the field of data transmission.
For the understanding of the present embodiment, a serializer/deserializer disclosed by the embodiment of the present invention will be described in detail first.
The embodiment of the invention provides a serializer/deserializer; the serializer/deserializer is arranged in a high-speed interface protocol exchange chip; the serializer/deserializer is respectively connected with the physical coding circuit, the software defined control circuit and the external physical link; the serializer/deserializer comprises a configuration management circuit and a set number of serializing/deserializing circuits; the serialization/deserialization circuit comprises a receiver, a transmitter and a clock management circuit; the clock management circuit is respectively connected with the receiver and the transmitter.
Taking the set number of 4 as an example, the structure diagram of the serializer/deserializer is shown in fig. 2, and the serializer/deserializer includes a configuration management circuit 10 and a first serializing/deserializing circuit 20a, a second serializing/deserializing circuit 20b, a third serializing/deserializing circuit 20c and a fourth serializing/deserializing circuit 20 d; the configuration management circuit 10 is connected to the first deserializing/deserializing circuit 20a, the second deserializing/deserializing circuit 20b, the third deserializing/deserializing circuit 20c, and the fourth deserializing/deserializing circuit 20d, respectively; the first serializing/deserializing circuit 20a includes a first receiver 201a, a first transmitter 202a, and a first clock management circuit 203 a; the second serializing/deserializing circuit 20b includes a second receiver 201b, a second transmitter 202b, and a second clock management circuit 203 b; the third serializing/deserializing circuit 20c includes a third receiver 201c, a third transmitter 202c, and a third clock management circuit 203 c; the fourth deserializing/deserializing circuit 20d includes a fourth receiver 201d, a fourth transmitter 202d and a fourth clock management circuit 203 d.
The configuration management circuit is used for receiving a configuration instruction sent by the software-defined control circuit; setting each serialization/deserialization circuit according to the configuration instruction; wherein, the configuration instruction comprises a plurality of configuration subcommands; the configuration management circuit sets a serial/deserializing circuit corresponding to the configuration sub-command; the configuration sub-command comprises clock frequency, parallel bit width, channel selection and the like, and configures configurable modules in a clock management circuit, a receiver and a transmitter respectively; each clock management circuit is used for outputting a clock signal corresponding to the configuration instruction to a receiver and a transmitter which belong to the same serialization/deserialization circuit; by configuring the clock management circuit, different serialization/deserialization circuits can work synchronously or asynchronously; after the configurable module of the receiver is configured, the receiver can process the protocol data of the corresponding high-speed interface; the receiver is used for converting serial data sent by an external physical link into parallel data according to a high-speed interface protocol corresponding to the configuration instruction and sending the parallel data to the physical coding circuit; after the configurable module of the transmitter is configured, the transmitter can process the protocol data of the corresponding high-speed interface; and the transmitter is used for converting the parallel data sent by the physical coding circuit into serial data according to a high-speed interface protocol corresponding to the configuration instruction and sending the serial data to an external physical link.
The receiver may include an impedance correction circuit, an Equalizer (CTLE-Continuous Time Linear Equalizer and DFE-Decision Feedback Equalization), a clock data recovery circuit and logic (clock data recovery circuit CDR), a phase difference unit, a parallel bit width configurable serial-to-parallel conversion circuit, PRBS (Pseudo Random Binary Sequence) detection, a built-in receive path loop, and the like; the method is mainly used for adjusting the clock according to input data, so that data sampling is achieved, and serial data are converted into parallel data.
The transmitter can comprise a parallel-serial conversion circuit, an output driver, a pre-emphasis control circuit, an edge control circuit, an impedance correction circuit, a PRBS generation circuit, a built-in transmission path loopback and a parallel-serial conversion circuit with configurable parallel bit width, and the like; the method is mainly used for completing the conversion and driving of data from parallel to serial.
The embodiment of the invention provides a serializer/deserializer; the serializer/deserializer comprises a configuration management circuit and a set number of serializing/deserializing circuits; the serialization/deserialization circuit comprises a receiver, a transmitter and a clock management circuit; the configuration management circuit receives a configuration instruction sent by the software definition control circuit; setting each serialization/deserialization circuit according to the configuration instruction; the clock management circuit outputs a clock signal corresponding to the configuration instruction to the receiver and the transmitter; the receiver converts serial data sent by an external physical link into parallel data according to a high-speed interface protocol corresponding to the configuration instruction, and then sends the parallel data to the physical coding circuit; and the transmitter converts the parallel data sent by the physical coding circuit into serial data according to a high-speed interface protocol corresponding to the configuration instruction and then sends the serial data to an external physical link. The method improves the applicability of the serializer/deserializer to various high-speed interface protocols and improves the efficiency.
An embodiment of the present invention provides a multi-channel SerDes structure (also referred to as a serializer/deserializer) based on a multi-protocol architecture, which is implemented on the basis of the serializer/deserializer shown in fig. 2; the SerDes structure can be suitable for serialization or deserialization of data of which the high-speed interface protocol is one or more of FC-AE-ASM protocol, RapidIO3.0 protocol, 10GBASE-KR protocol and 1000BASE-X protocol.
The multi-channel SerDes circuit supporting multiple protocols is compatible with the physical specification requirements of four serial interface protocols including FC-AE-ASM protocol, RapidIO3.0 protocol and 10GBASE-KR protocol 1000BASE-X, and simultaneously supports channel binding of different protocol modes, and the highest speed can reach 10.3125 Gbps.
The SerDes circuit of the present invention has the main design concept: firstly, analyzing the specification of each protocol physical layer, and sorting the function and performance requirements of each interface protocol; after finishing the requirement arrangement, carrying out normalization design on the same similar functions to be used as a common logic of the SerDes circuit in different protocol working modes; finally, the differentiated functions required by different protocols are designed into the configurable heterogeneous processing circuit according to the design thought definable by software.
The multi-protocol high-speed serial SerDes mainly has the functions of converting data from parallel to high-speed serial signals and sending the signals to a channel, receiving the high-speed serial data from the channel and converting the high-speed serial data into parallel signals for an upper layer to use, and the whole process is completed under the synchronous action of clocks. The SerDes circuit is designed according to a functional requirement in a mode of designing a submodule, the data and control relation of each functional module is shown in figure 3, and the requirements of each protocol on the SerDes function are mostly consistent, so that parts with the same functional requirement are designed into general logic.
SerDes circuits are designed according to a 4Lane group, here called a Bank, each Bank consisting essentially of three parts: 4 receiving and transmitting main channels, a clock processing module, a configuration management and reset module (also called as a reset circuit); wherein, a main transceiver channel is provided with a clock processing module, the two modules are combined to be equivalent to the serialization/deserialization circuit, and the main transceiver channel comprises a receiver and a transmitter; the reset circuit is respectively connected with the configuration management circuit and the serialization/deserialization circuit; the clock processing module is a differential driving module and mainly comprises a phase-locked loop circuit QPLL in a Bank, a phase-locked loop circuit CPLL in a channel, a clock selection circuit, a frequency division circuit and the like; the configuration management mainly comprises a configuration bus management module and a register management module, and is responsible for realizing software configuration control on data path selection, clock frequency, data bit width and submodule working modes; the reset circuit is used for carrying out hard reset on the configuration management circuit and the serialization/deserialization circuit when receiving a reset signal.
In addition, the clock management module can also adopt a scheme that a reference clock is directly input into the phase-locked loop circuit CPLL in the channel to realize the functions, and can be realized as an alternative scheme of the invention.
In particular, the structure of a serializing/deserializing circuit can also be understood from fig. 3; in Lane0 shown in fig. 3, the receiver includes a multi-gradient swing amplitude adjusting circuit, a receiving equalizing circuit, a clock data recovery circuit, a serial-to-parallel conversion circuit, a PRBS detection circuit, and a first data bit width conversion circuit, which are connected in sequence; an eye pattern observation module can be arranged to observe the data condition between the receiving equalization circuit and the clock data recovery circuit module; the configuration management circuit is connected with the first data bit width conversion circuit; the configuration management circuit outputs a control signal to set the parallel bit width of the first data bit width conversion circuit. The transmitter comprises a second data bit width conversion circuit, a first selector, an asynchronous cache circuit, a second selector, a parallel-serial conversion circuit, a pre-emphasis circuit and a driver which are connected in sequence; the transmitter further includes a PRBS sequence source circuit; the PRBS sequence source circuit is connected with the input end of the first selector; the first selector and the second selector are either one-out-of-two selectors; two input ends of the first selector are respectively connected with the PRBS sequence source circuit and the second data bit width conversion circuit; the output end of the first selector is connected with the asynchronous cache circuit; two input ends of the second selector are respectively connected with the parallel-serial conversion circuit and the asynchronous cache circuit; the output end of the second selector is connected with the parallel-serial conversion circuit; the configuration management circuit is respectively connected with the selection end of the first selector, the selection end of the second selector and the second data bit width conversion circuit; the configuration management circuit outputs a control signal to control output signals of output ends of the first selector and the second selector; the configuration management circuit outputs a control signal to set the parallel bit width of the second data bit width conversion circuit.
In addition, one Lane also comprises a configuration interface; the configuration interface is connected with the configuration management circuit; the configuration management circuit is in signal transmission with the software defined control circuit through the configuration interface.
One Lane further includes a first receiving differential port and a second receiving differential port, that is, a receiving differential P and a receiving differential N in fig. 3; the first receiving differential port and the second receiving differential port are connected with the multi-gradient swing amplitude adjusting circuit; the multi-gradient swing adjusting circuit receives serial data sent by an external physical link through a first receiving differential port and a second receiving differential port.
One Lane further includes a first transmitting differential port and a second transmitting differential port, that is, a transmitting differential P and a transmitting differential N in fig. 3; the first sending differential port and the second sending differential port are connected with the pre-emphasis circuit; the pre-emphasis circuit sends the parallel data to the external physical link through the first sending differential port and the second sending differential port.
The SerDes circuit provided by the invention can support the requirements of different application forms, including a mixed protocol path, a path with different channel widths and a path with different rates.
1. For different channel width passages
The same-width access refers to the same Bank of the SerDes, and different channel widths can be defined by software according to different application protocols. Namely, 4 Lanes inside the SerDes support channel multiplexing under 1X/2X/4X mode, and support dynamic configuration of various modes: 4X, 2X +2X, 2X (1X) +1X +1X, 1X +1X +2X (1X), 1X +1X +1X +1X and corresponding redundant mode. Namely, 4 channels contained in 1 SerDes can be dynamically configured into the following three modes, and the redundant mode configuration under the above 3 modes is supported at the same time:
(1) the 4 channels work in a 4X mode, and simultaneously, the redundancy can be configured to be 2X (Lane 2-Lane 3 redundancy) and 1X (Lane 1-Lane 3 redundancy), as shown in fig. 4, the four channels simultaneously process input data or output data, and perform data transmission with the same physical coding circuit.
(2)2 channels operate in 1st 2X mode while being redundantly configurable to 1X (Lane1 redundancy), and the other 2 channels operate in 2X mode while being redundantly configurable to 1X (Lane3 redundancy), as shown in fig. 5.
(3)2 channels are operated in 2X mode, and redundancy is configured to be 1X (Lane1 redundancy), Lane2 is operated in 1X mode, and Lane3 is operated in 1X mode, as shown in fig. 6.
(4) Lane0 operates in 1X mode, Lane1 in 1X mode, Lane 2-Lane 3 in 2X mode, while redundantly configurable to 1X (Lane3 redundancy), as shown in FIG. 7.
(5) Lane0, Lane1, Lane2, and Lane3 each operate in 1x mode as shown in fig. 8.
Wherein, PCS is a physical coding circuit; TX0_ P, TX0_ N are output signals of the transmission differential P and the transmission differential N, respectively; RX0_ P, RX0_ N are input signals for receiving the differential P and receiving the differential N, respectively.
2. For mixed protocol paths
The mixed protocol path refers to the application characteristic that multiple communication protocols can be supported in the same Bank of the SerDes. In consideration of the specificity of RapidIO protocol and the requirement of simplifying controller clock structure, SerDes channels under the hybrid protocol can be distributed as shown in Table 1, wherein the Eth (Ethernet) protocol comprises 10GBASE-KR and 1000BASE-X protocol, FC refers to FC-AE-ASM protocol, and RapidIO refers to RapidIO3.0 protocol.
TABLE 1
3. For different rate paths
A different rate path means that different lanes of SerDes IP may operate at different rates. It should be noted here that the different rate paths are limited to two conditions: the communication protocol of the current channel, the Lane n X width mode of the binding.
The multi-protocol SerDes IP needs to support PHY layer specifications of different protocols, and therefore, a corresponding channel needs to support multiple frequency points under different protocols. Specifically, as shown in table 2. Thus, multi-protocol high-speed SerDes requires rate configuration under each protocol specification.
TABLE 2
In addition, since SerDes can operate in different operation modes, in which n channels operating in Lane n X mode must operate at the same rate and the n channels are required to be synchronized, in particular, Lane0 to Lane1 and Lane2 to Lane3 in 2X +2X mode must operate at the same rate set in view of simplification of the clock structure of the upper layer controller, that is: rate set one: 1.25/2.5/5Gbps, rate set two: 3.125/6.25Gbps, rate set three: 10.3125 Gbps.
The operation flow of the sending-receiving multi-protocol multi-channel SerDes circuit is shown in FIG. 2, taking RapidIO3.0 protocol x4 channel/10.3125G rate operation as an example.
1. Under RapidIO3.0 protocol x4 channel/10.3125 Gbps rate mode, the multichannel SerDes circuit sends a path work flow:
a) the chip is hard reset by the entire SerDes circuit and the sub-modules associated with the SerDes.
b) The user configures the protocol to meet the current protocol function and performance requirements through the configuration management module: configuring an originating data path selection (two MUXs in FIG. 5) which is a functional mode data path; configuring a clock management module and outputting a clock frequency corresponding to the rate of 10.3125 Gbps; and configuring four data bit width conversion modules of the Lane transmitting end, wherein the working mode is an x4 mode.
c) The user completes the configuration and starts to initiate data transmission, which is sent into the physical link via the SerDes circuitry.
2. Under RapidIO3.0 protocol x4 channel/10.3125 Gbps rate mode, the multichannel SerDes circuit receives the path workflow:
a) the chip is hard reset by the entire SerDes circuit and the sub-modules associated with the SerDes.
b) The user configures the protocol to meet the current protocol function and performance requirements through the configuration management module: configuring an originating data path selection (three MUXs in FIG. 2) which is a functional mode data path; configuring a clock management module and outputting a clock frequency corresponding to the rate of 10.3125 Gbps; and configuring four data bit width conversion modules of the Lane transmitting end, wherein the working mode is an x4 mode.
c) The user completes the configuration and starts to start data reception, and the received data from the physical link enters the subsequent chip circuit through the SerDes.
The multi-channel SerDes circuit based on the multi-protocol architecture has the following advantages:
1. the method supports the physical specification requirements of four serial interface protocols including FC-AE-ASM protocol, RapidIO3.0 protocol and 10GBASE-KR protocol 1000BASE-X, realizes the switching of programmable working modes, and greatly increases the applicability of the SerDes circuit to different protocol application scenes.
2. The single SerDes circuit hybrid protocol works simultaneously, and the application form of the high-speed serial interface using the SerDes circuit is more flexible. The multi-protocol data interaction system designed by the invention can greatly reduce the system hardware scale and the volume, weight and power consumption overhead.
3. In the circuit, built-in test loop paths are designed on a plurality of key data paths, so that the testability of the circuit is improved.
The embodiment of the present invention further provides a high speed interface protocol exchange chip, and a schematic structural diagram of the chip is shown in fig. 9; the chip comprises a software defined control circuit 80, the above mentioned serializer/deserializer 81, a physical coding circuit 82, a data link circuit 83 and a transmission transaction circuit 84 connected in sequence.
The high-speed interface protocol exchange chip provided by the embodiment of the invention has the same technical characteristics as the serializer/deserializer provided by the embodiment, so that the same technical problems can be solved, and the same technical effect is achieved.
The computer program product of the serializer/deserializer and the high-speed interface protocol exchange chip provided by the embodiment of the invention includes a computer readable storage medium storing a program code, and instructions included in the program code can be used for executing the method described in the foregoing method embodiment.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the system and/or the apparatus described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In addition, in the description of the embodiments of the present invention, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present invention, which are used for illustrating the technical solutions of the present invention and not for limiting the same, and the protection scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. A serializer/deserializer, wherein the serializer/deserializer is disposed in a high speed interface protocol exchange chip; the serializer/deserializer is respectively connected with the physical coding circuit, the software defined control circuit and the external physical link; the serializer/deserializer comprises a configuration management circuit and a set number of serializing/deserializing circuits; the configuration management circuit is respectively connected with the serialization/deserialization circuit; the serializing/deserializing circuit includes a receiver, a transmitter, and a clock management circuit; the clock management circuit is respectively connected with the receiver and the transmitter;
the configuration management circuit is used for receiving a configuration instruction sent by the software-defined control circuit; setting each serializing/deserializing circuit according to the configuration instruction;
the clock management circuit is used for outputting a clock signal corresponding to the configuration instruction to the receiver and the transmitter;
the receiver is used for converting serial data sent by the external physical link into parallel data according to a high-speed interface protocol corresponding to the configuration instruction, and sending the parallel data to the physical coding circuit;
the transmitter is used for converting the parallel data sent by the physical coding circuit into serial data according to a high-speed interface protocol corresponding to the configuration instruction and sending the serial data to the external physical link;
the receiver comprises a multi-gradient swing amplitude adjusting circuit, a receiving equalizing circuit, a clock data recovery circuit, a serial-parallel conversion circuit, a PRBS detection circuit and a first data bit width conversion circuit which are sequentially connected;
the configuration management circuit is connected with the first data bit width conversion circuit; and the configuration management circuit outputs a control signal to set the parallel bit width of the first data bit width conversion circuit.
2. The serializer/deserializer of claim 1, wherein the configuration instruction comprises a plurality of configuration subcommands; the configuration management circuit sets a serialization/deserialization circuit corresponding to the configuration subcommand; the configuration subcommands include clock frequency, parallel bit width, and channel selection.
3. The serializer/deserializer of claim 1, wherein the high-speed interface protocol comprises one or more of a FC-AE-ASM protocol, a RapidIO3.0 protocol, a 10GBASE-KR protocol, and a 1000BASE-X protocol.
4. The serializer/deserializer of claim 1, wherein the serializer/deserializer circuit further comprises a first receiving differential port and a second receiving differential port; the first receiving differential port and the second receiving differential port are connected with the multi-gradient swing adjusting circuit; and the multi-gradient swing adjusting circuit receives serial data sent by the external physical link through the first receiving differential port and the second receiving differential port.
5. The serializer/deserializer of claim 3, wherein the transmitter comprises a second data bit width converting circuit, a first selector, an asynchronous buffer circuit, a second selector, a parallel-serial converting circuit, a pre-emphasis circuit and a driver, which are connected in sequence; the transmitter further includes a PRBS sequence source circuit; the PRBS sequence source circuit is connected with the input end of the first selector;
the first selector and the second selector are either one-out-of-two selectors; two input ends of the first selector are respectively connected with the PRBS sequence source circuit and the second data bit width conversion circuit; the output end of the first selector is connected with the asynchronous cache circuit; two input ends of the second selector are respectively connected with the parallel-serial conversion circuit and the asynchronous cache circuit; the output end of the second selector is connected with the parallel-serial conversion circuit;
the configuration management circuit is respectively connected with the selection end of the first selector, the selection end of the second selector and the second data bit width conversion circuit; the configuration management circuit outputs a control signal to control output signals of output ends of the first selector and the second selector; and the configuration management circuit outputs a control signal to set the parallel bit width of the second data bit width conversion circuit.
6. The serializer/deserializer of claim 5, wherein the serializer/deserializer circuit further comprises a first transmit differential port and a second transmit differential port; the first transmitting differential port and the second transmitting differential port are connected with the pre-emphasis circuit; the pre-emphasis circuit sends parallel data to the external physical link through the first sending differential port and the second sending differential port.
7. The serializer/deserializer of claim 1, further comprising a reset circuit; the reset circuit is respectively connected with the configuration management circuit and the serialization/deserialization circuit;
the reset circuit is used for carrying out hard reset on the configuration management circuit and the serialization/deserialization circuit when receiving a reset signal.
8. The serializer/deserializer of claim 1, wherein the serializer/deserializer circuit further comprises a configuration interface; the configuration interface is connected with the configuration management circuit; the configuration management circuit is in signal transmission with the software defined control circuit through the configuration interface.
9. A high speed interface protocol switching chip comprising software defined control circuitry, a serializer/deserializer as claimed in any one of claims 1 to 8, physical coding circuitry, data link circuitry and transport transaction circuitry connected in series.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910212722.6A CN109947681B (en) | 2019-03-20 | 2019-03-20 | Serializer/deserializer and high-speed interface protocol exchange chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910212722.6A CN109947681B (en) | 2019-03-20 | 2019-03-20 | Serializer/deserializer and high-speed interface protocol exchange chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109947681A CN109947681A (en) | 2019-06-28 |
| CN109947681B true CN109947681B (en) | 2020-12-01 |
Family
ID=67011141
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910212722.6A Active CN109947681B (en) | 2019-03-20 | 2019-03-20 | Serializer/deserializer and high-speed interface protocol exchange chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109947681B (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110493310B (en) * | 2019-07-17 | 2021-09-10 | 中国人民解放军战略支援部队信息工程大学 | Software defined protocol controller and method |
| EP4084403B1 (en) * | 2020-01-21 | 2024-03-06 | Huawei Technologies Co., Ltd. | Switch element and switch apparatus |
| CN112685355B (en) * | 2021-01-11 | 2022-03-18 | 龙迅半导体（合肥）股份有限公司 | String adding device |
| WO2022193328A1 (en) * | 2021-03-19 | 2022-09-22 | 华为技术有限公司 | Serializing/deserializing circuit, serial data receiving method, and chip |
| CN113572486B (en) * | 2021-06-29 | 2022-06-24 | 中国人民解放军战略支援部队信息工程大学 | Transmitter with low-speed SerDes interface, receiver with low-speed SerDes interface and circuit design method of transmitter |
| CN113626364B (en) * | 2021-06-30 | 2024-05-31 | 海光信息技术股份有限公司 | High-speed serial interface and conversion circuit for same |
| CN114143513B (en) * | 2021-12-29 | 2023-04-14 | 重庆紫光华山智安科技有限公司 | Multi-dimensional feature acquisition device and image acquisition method |
| CN116414755A (en) * | 2021-12-31 | 2023-07-11 | 华为技术有限公司 | High-speed serial interface and data transmission method |
| CN114336197B (en) * | 2022-01-20 | 2024-03-08 | 深圳宏芯宇电子股份有限公司 | Interface conversion device, test board and card reader |
| CN114968875B (en) * | 2022-05-31 | 2023-08-25 | 重庆长安汽车股份有限公司 | Self-adaptive system supporting vehicle-mounted serial deserializing link and automatic driving automobile |
| CN115882870B (en) * | 2023-02-01 | 2023-05-26 | 井芯微电子技术(天津)有限公司 | High-speed serializer and deserializer integration method and electronic equipment |
| CN117539818B (en) * | 2024-01-10 | 2024-04-02 | 富瀚微电子(成都)有限公司 | Interface based on PHY model, chip integrating interface and chip simulation system |
| CN117749263B (en) * | 2024-02-08 | 2024-04-26 | 合肥国家实验室 | Receiving device based on space laser communication and space laser communication system |
| CN118093493A (en) * | 2024-04-23 | 2024-05-28 | 北京集创北方科技股份有限公司 | Data processing device, processing method, processing system, display device and chip |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105680871A (en) * | 2016-04-07 | 2016-06-15 | 武汉芯泰科技有限公司 | Parallel-serial/ serial-parallel conversion device for data serial transmission |
| CN109495519A (en) * | 2019-01-09 | 2019-03-19 | 天津芯海创科技有限公司 | Physical code circuit and high speed interface protocol exchange chip |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6901126B1 (en) * | 2000-06-30 | 2005-05-31 | Texas Instruments Incorporated | Time division multiplex data recovery system using close loop phase and delay locked loop |
| CN101394678B (en) * | 2008-11-07 | 2010-12-08 | 烽火通信科技股份有限公司 | Serialization/de-serialization interface module generally used in GEPON/GPON |
| CN102257849B (en) * | 2011-06-08 | 2014-06-04 | 华为技术有限公司 | Method, system and apparatus for dynamically adjusting link |
| CN102323877B (en) * | 2011-08-31 | 2014-09-24 | 广东威创视讯科技股份有限公司 | SERDES-based video processing system |
| CN204362064U (en) * | 2015-01-14 | 2015-05-27 | 灿芯半导体(上海)有限公司 | Data sink, data receiving system and data transmission system |
| CN105119715B (en) * | 2015-07-03 | 2018-04-03 | 合肥工业大学 | Digital circuit is interconnected between a kind of virtual IO pieces of FPGA based on re-encryption algorithm |
| CN106230826B (en) * | 2016-08-02 | 2019-03-29 | 哈尔滨工业大学 | Application system interface protocol automatic analyzer |
| US10069660B1 (en) * | 2017-04-13 | 2018-09-04 | Credo Technology Group Limited | Low power SerDes architecture and protocol |
| CN108039961A (en) * | 2017-12-01 | 2018-05-15 | 周阳 | A kind of apparatus and method for automatically configuring high speed serialization transceiver parameters |
-
2019
- 2019-03-20 CN CN201910212722.6A patent/CN109947681B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105680871A (en) * | 2016-04-07 | 2016-06-15 | 武汉芯泰科技有限公司 | Parallel-serial/ serial-parallel conversion device for data serial transmission |
| CN109495519A (en) * | 2019-01-09 | 2019-03-19 | 天津芯海创科技有限公司 | Physical code circuit and high speed interface protocol exchange chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109947681A (en) | 2019-06-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109947681B (en) | Serializer/deserializer and high-speed interface protocol exchange chip | |
| EP1480391B1 (en) | A physical layer device having an analog serdes pass through mode | |
| EP2020104B1 (en) | Multiple fiber optic gigabit ethernet links channelized over single optical link | |
| JP5882530B2 (en) | Configurable multi-mode media independent interface | |
| US9008504B2 (en) | Transmission apparatus and method for serial and parallel channel interworking in optical transport network | |
| US11265400B2 (en) | Multimode interconnection interface controller for converged network | |
| US20090046745A1 (en) | Apparatus for transmitting and receiving data with various data capacities at high speed | |
| JP2015515195A (en) | Multiple serial media independent interface | |
| CN219227609U (en) | JESD204B data transmission system based on optical fiber medium | |
| CN106209292B (en) | Method and device for realizing SDH optical interface of STM-1 by utilizing oversampling method | |
| CN201910048U (en) | LVDS (Low Voltage Differential Signaling) node module | |
| WO2011152818A1 (en) | Multiplexed serial media independent interface | |
| CN105406931B (en) | Time multiplexing date polymerization on high-speed serializer/deserializer channel | |
| WO2018196833A1 (en) | Message sending method and message receiving method and apparatus | |
| EP2498446B1 (en) | Method and apparatus compatible with 10ge lan port and wan port | |
| CN101296063B (en) | Main/standby switching device, method and single plate | |
| US8472482B2 (en) | Multiple infiniband ports within a higher data rate port using multiplexing | |
| WO2003081785A1 (en) | Physcial layer device having an analog serdes pass through mode | |
| CN115017081B (en) | Multipath SRIO interface clock resource sharing system based on domestic FPGA | |
| KR100406490B1 (en) | Apparatus for Conversing Interface of Board about Bus Structure In Router System | |
| TW200527854A (en) | System architecture and related method for communication between network layers serially | |
| KR20120125953A (en) | Transmitting apparatus and method of serial and parallel channel interworking in optical transport network | |
| CN115269487A (en) | Inter-chip data high-speed transmission method and device | |
| CN116860687A (en) | Serial deserialization IP for multiple link lanes | |
| CN117130973A (en) | High-speed data transmission architecture based on FPGA Serdes interface |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |