CN114336197B - Interface conversion device, test board and card reader - Google Patents
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Abstract
The interface conversion device generates serial data in PCI-E format through a first physical layer, under the control of an interface detection unit, the first physical layer and a PCI-E protocol control circuit are connected through a first switching unit, or the first physical layer and a UFS protocol conversion circuit are connected, the received serial data in PCI-E format is converted into serial data in USB format through the PCI-E protocol control circuit to be sent to a second physical layer, or the received serial data in PCI-E format is converted into serial data in UFS format through the UFS protocol conversion circuit to be sent to the second physical layer, finally the serial data in USB format is converted into corresponding parallel transmission data through the second physical layer, or the serial data in UFS format is converted into corresponding parallel transmission data, and data transmission efficiency between different equipment interfaces is improved.
Description
Technical Field
The application relates to the technical field of communication, in particular to an interface conversion device, a test board and a card reader.
Background
With the development of storage technology, the transmission quantity of the existing data is larger and larger, and the functional requirements on the storage interface are more and more increased.
The UFS card is generally used when storing data on a mobile phone platform, however, the transmission amount of the UFS interface is limited, and the transmission efficiency is low.
Disclosure of Invention
In view of this, the application provides an interface conversion device, a test board and a card reader, which can combine respective advantages of a PCI-E interface and a UFS interface, and can greatly improve a transmission rate of the UFS interface.
An interface conversion device for converting a first PCI-E interface into a second PCI-E interface or UFS interface, the interface conversion device comprising:
the first physical layer is used for receiving a first data signal sent by the external device and generating serial data in PCI-E format;
the interface detection unit is used for detecting the access information of each of the second PCI-E interface and the UFS interface so as to generate a corresponding first detection signal or second detection signal, and sending the first detection signal or the second detection signal to the first switch switching unit;
the first switch switching unit is used for switching on the first physical layer and the PCI-E protocol control circuit according to a first detection signal or switching on the first physical layer and the UFS protocol conversion circuit according to a second detection signal;
the PCI-E protocol control circuit is used for receiving the serial data in the PCI-E format sent by the first physical layer and sending the serial data in the PCI-E format to the second physical layer when the PCI-E protocol control circuit is connected with the first physical layer;
the UFS protocol conversion circuit is used for receiving the serial data in the PCI-E format sent by the first physical layer when being communicated with the first physical layer, converting the serial data in the PCI-E format into the serial data in the UFS format and sending the serial data to the second physical layer;
and the second physical layer is used for receiving the first detection signal or the second detection signal sent by the interface detection unit, converting serial data in the PCI-E format into corresponding parallel transmission data according to the first detection signal, or converting serial data in the UFS format into corresponding parallel transmission data according to the second detection signal.
In one embodiment, the second physical layer includes a physical decoding sublayer and a first physical medium additional sublayer electrically connected in sequence, the physical decoding sublayer includes a first FIFO interface unit, a second switch switching unit, a first decoding unit and a second decoding unit, and the first decoding unit and the second decoding unit are electrically connected with the first physical medium additional sublayer respectively;
the first physical medium additional sub-layer is used for receiving serial data in a USB format, converting the serial data in the USB format into corresponding USB parallel data and sending the corresponding USB parallel data to the first decoding unit, or receiving serial data in a UFS format, converting the serial data in the UFS format into corresponding UFS parallel data and sending the corresponding UFS parallel data to the second decoding unit;
the second switch switching unit is used for switching on the first FIFO interface unit and the first decoding unit to form a first path when being switched on between the first physical layer and the PCI-E protocol control circuit according to the first detection signal, or switching on the first FIFO interface unit and the second decoding unit to form a second path when being switched on between the first physical layer and the UFS protocol conversion circuit according to the second detection signal;
the first decoding unit is used for decoding the USB parallel data to generate corresponding parallel transmission data when the first path is formed, and outputting the parallel transmission data through the first FIFO interface unit;
the second decoding unit is used for decoding the UFS parallel data to generate corresponding parallel transmission data when the second path is formed, and outputting the parallel transmission data through the first FIFO interface unit.
In one embodiment, the second physical medium layer further includes a second physical medium additional sub-layer and a physical coding sub-layer electrically connected in sequence, the physical coding sub-layer includes a second FIFO interface unit, a third switch switching unit, a first coding unit and a second coding unit, and the first coding unit and the second coding unit are electrically connected with the second physical medium additional sub-layer respectively;
the third switch switching unit is used for switching on the second FIFO interface unit and the first coding unit and forming a third path when being switched on between the first physical layer and the PCI-E protocol control circuit according to the first detection signal, or switching on the second FIFO interface unit and the second coding unit to form a fourth path when being switched on between the first physical layer and the UFS protocol conversion circuit;
the second FIFO interface unit is used for receiving a second data signal transmitted from outside, and transmitting the second data signal to the first coding unit according to the first detection signal when a third channel is formed;
the first coding unit is used for coding the second data signal to obtain first coded data and transmitting the first coded data to the second physical medium additional sub-layer;
the second FIFO interface unit is further configured to send a second data signal to the second encoding unit according to the second detection signal when the fourth channel is formed;
the second coding unit is used for coding the second data signal to obtain second coded data and transmitting the second coded data to the second physical medium additional sub-layer;
the second physical medium additional sub-layer is used for converting the first coded data into serial data in a corresponding PCI-E format and sending the serial data to the PCI-E protocol control circuit, or converting the second coded data into serial data in a corresponding UFS format and sending the serial data to the UFS protocol conversion circuit;
the PCI-E protocol control circuit is also used for transmitting serial data in a corresponding PCI-E format to the first physical layer after being communicated with the first physical layer;
the UFS protocol conversion circuit is also used for converting serial data in a corresponding UFS format into serial data in a corresponding PCI-E format after being communicated with the first physical layer and sending the serial data to the first physical layer;
the first physical layer is further configured to convert serial data in a PCI-E format corresponding to the second data signal into parallel transmission data for data transmission.
In one embodiment, the first physical medium attachment sublayer comprises a receiver, a arbitration feedback equalizer, a clock recovery circuit, and a deserializer, which are electrically connected in sequence.
In one embodiment, the second physical medium additional sub-layer includes a serializer, a feedback equalizer, and a driver electrically connected in sequence.
In one embodiment, the interface detection unit adopts a single-chip microcomputer detection chip, and the single-chip microcomputer detection chip is provided with a USB interface detection unit and a UFS interface detection unit;
the single chip microcomputer detection chip is used for detecting equipment access information of the USB interface through the USB interface detection unit, and generating a first detection signal when equipment access exists in the USB interface;
the single chip microcomputer detection chip is also used for detecting equipment access information of the UFS interface through the UFS interface detection unit, and generating a second detection signal when equipment access exists in the UFS interface.
In one embodiment, the first decoding unit comprises an electrically connected 128b132b decoder and a first non-return-to-zero inverse decoder, the first encoding unit comprises an electrically connected 128b132b encoder and a first non-return-to-zero inverse encoder, the second decoding unit comprises an electrically connected 8b10b decoder and a second non-return-to-zero inverse decoder, and the first encoding unit comprises an electrically connected 8b10b encoder and a second non-return-to-zero inverse encoder.
In one embodiment, the first switch switching unit employs a single pole double throw switch.
In one embodiment, the first switching unit employs a MOS transistor switching circuit or a triode switching circuit.
In one embodiment, the interface conversion device further includes a phase-locked loop unit, where the phase-locked loop unit is configured to receive the first detection signal sent by the interface detection unit and generate a first set of clock signals, or receive the second detection signal sent by the interface detection unit and generate a second set of clock signals;
the first group of clock signals are used as internal clock signals corresponding to the operation of the first PCI-E interface to the second PCI-E interface, and the second group of clock signals are used as internal clock signals corresponding to the operation of the first PCI-E interface to the UFS interface.
In addition, a test board is provided, and the interface conversion device is arranged on the test board.
In addition, a card reader is provided with the interface conversion device.
The first physical layer, the switch control unit, the first switch switching unit, the PCI-E protocol control circuit, the UFS protocol conversion circuit and the second physical layer are arranged, serial data in PCI-E format is generated through the first physical layer, then under the control of the switch control unit, the first physical layer and the PCI-E protocol control circuit are connected through the first switch switching unit, or the first physical layer and the UFS protocol conversion circuit are connected according to the second switch control signal, when the PCI-E protocol control circuit is connected with the first physical layer, the serial data in PCI-E format sent by the first physical layer is received, the serial data in PCI-E format is converted into the serial data in USB format, and the serial data in PCI-E format is sent to the second physical layer, or when the UFS protocol conversion circuit is connected with the first physical layer, the serial data in the PCI-E format sent by the first physical layer is received, the serial data in the PCI-E format is converted into the serial data in the UFS format to be sent to the second physical layer, and finally, the first detection signal or the second detection signal sent by the switch control unit is received through the second physical layer, the serial data in the USB format is converted into corresponding parallel transmission data according to the first detection signal, or the serial data in the UFS format is converted into corresponding parallel transmission data according to the second detection signal, so that external first input data can be converted into the second PCI-E interface or the UFS interface through the first PCI-E interface to be subjected to data output, and the data transmission efficiency between different equipment interfaces is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a control chip for converting a PCI-E interface into a USB or UFS interface according to an embodiment of the present application;
FIG. 2 is a schematic structural diagram of a second physical layer according to an embodiment of the present disclosure;
fig. 3 is a schematic circuit diagram of a switch control unit according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a first decoding unit according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a first coding unit according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of a second decoding unit according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of a second encoding unit according to an embodiment of the present application;
fig. 8 is a block diagram of a test board according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application. The various embodiments described below and their technical features can be combined with each other without conflict.
As shown in fig. 1, an interface conversion device 100 is provided for converting a first PCI-E interface into a second PCI-E interface or UFS interface, the interface conversion device 100 including:
the first physical layer 110 is configured to receive a first data signal sent by an external device and generate serial data in PCI-E format.
The external device includes a device having a PCI-E plug, and the first Physical Layer is also commonly referred to as a PHY Layer (PHY) for converting the received first input data into serial data in a PCI-E format.
Among them, PCI-E formats include PCI-E1.0, PCI-E2.0, PCI-E3.0, PCI-E4.0, and PCI-E5.0.
The interface detection unit 120 is configured to detect access information of each of the second PCI-E interface and the UFS interface, generate a corresponding first detection signal or second detection signal, and send the first detection signal or the second detection signal to the first switching unit 130.
When the PCI-E interface of the control chip 100 has device access, the interface detection unit 120 correspondingly generates a first detection signal, and when the UFS interface of the control chip 100 has device access, the interface detection unit 120 correspondingly generates a second detection signal.
In one embodiment, the interface detecting unit 120 may be implemented by a single chip circuit structure, or may be implemented by a MOS transistor switch circuit or a triode switch circuit.
Wherein, the PCI-E interface and the UFS interface cannot work simultaneously.
In one embodiment, if the PCI-E interface and the UFS interface both have device access, the interface detecting unit 120 generates a corresponding detection signal according to the sequence of the device access corresponding to the PCI-E interface and the device access corresponding to the UFS interface, for example, when the device corresponding to the PCI-E interface is first accessed, the interface detecting unit 120 generates a corresponding first detection signal; when the device corresponding to the UFS interface is first accessed, the interface detecting unit 120 generates a corresponding second detection signal.
The first switching unit 130 is configured to switch on the first physical layer 110 and the PCI-E protocol control circuit 140 according to the first detection signal, or switch on the first physical layer 110 and the UFS protocol conversion circuit 160 according to the second detection signal.
The PCI-E protocol control circuit 140 is configured to receive the serial data in the PCI-E format sent by the first physical layer 110 and send the serial data in the PCI-E format to the second physical layer 150 when the first physical layer 110 is turned on.
The UFS protocol conversion circuit 160 is configured to receive serial data in the PCI-E format sent by the first physical layer 110, and convert the serial data in the PCI-E format into serial data in the UFS format for sending to the second physical layer 150 when the first physical layer 110 is turned on.
The UFS protocol refers to the abbreviation of Universal Flash Storage (universal flash memory) protocol.
The UFS protocol includes UFS2.2, UFS3.0, or UFS3.1.
The second physical layer 150 is configured to receive the first detection signal or the second detection signal sent by the interface detection unit 120, and convert serial data in the PCI-E format into corresponding parallel transmission data according to the first detection signal, or convert serial data in the UFS format into corresponding parallel transmission data according to the second detection signal.
The interface conversion device 100 is provided with a first physical layer 110, a switch control unit, a first switching unit 130, a PCI-E protocol control circuit 140, a UFS protocol conversion circuit 160 and a second physical layer 150, generates serial data in a PCI-E format through the first physical layer 110, then under the control of the switch control unit, switches on the first physical layer 110 and the PCI-E protocol control circuit 140 through the first switching unit 130, or switches on the first physical layer 110 and the UFS protocol conversion circuit 160 according to a second detection signal, further receives serial data in a PCI-E format sent by the first physical layer 110 through the PCI-E protocol control circuit 140 when the first physical layer 110 is switched on, converts the serial data in a PCI-E format into serial data in a PCI-E format to be sent to the second physical layer 150, or receives the serial data in a PCI-E format sent by the first physical layer 110 when the first physical layer 110 is switched on through the UFS protocol conversion circuit 160, converts the serial data in a PCI-E format into serial data to be sent to the second physical layer 150, and finally detects that the serial data in a PCI-E format is not converted into a serial data in a PCI-E format through the first physical layer 150, and the parallel data is detected through the first physical layer or the second physical layer is detected to be capable of being transferred to a parallel data in a parallel data transmission interface, and the parallel data is further converted into a serial data in accordance with the first interface.
In one embodiment, the second physical layer 150 includes a physical decoding sublayer 152 and a first physical medium adding sublayer 154 electrically connected in sequence, the physical decoding sublayer 152 includes a first FIFO interface unit 152a, a second switching unit 152b, a first decoding unit 152c and a second decoding unit 152d, and the first decoding unit 152c and the second decoding unit 152d are electrically connected to the first physical medium adding sublayer 154 respectively.
The first physical medium attachment sublayer 154 is used for receiving serial data in a PCI-E format, converting the serial data in the PCI-E format into corresponding PCI-E parallel data and transmitting the corresponding PCI-E parallel data to the first decoding unit 152c, or receiving serial data in a UFS format, converting the serial data in the UFS format into corresponding UFS parallel data and transmitting the corresponding UFS parallel data to the second decoding unit 152d.
The second switching unit 152b is configured to switch on the first FIFO interface unit 152a and the first decoding unit 152c and form a first path when switching on between the first physical layer 110 and the PCI-E protocol control circuit 140 according to the first detection signal, or switch on the first FIFO interface unit 152a and the second decoding unit 152d to form a second path when switching on between the first physical layer 110 and the UFS protocol conversion circuit 160 according to the second detection signal.
As can be seen from fig. 1 and 2, in the process of forming the first path, the first physical layer 110, the first switching unit 130, the PCI-E protocol control circuit 140, the first physical medium adding sublayer 154, the first decoding unit 152c, the second switching unit 152b and the first FIFO interface unit 152a form a path, the first physical layer 110 inputs the first input data, and the first FIFO interface unit 152a outputs the corresponding parallel transmission data.
Similarly, as can be seen from fig. 1 and 2, in the process of forming the second path, the first physical layer 110, the first switching unit 130, the UFS protocol conversion unit 140, the first physical medium additional sublayer 154, the second decoding unit 152d, the second switching unit 152b, and the first FIFO interface unit 152a form a path, the first physical layer 110 inputs the first input data, and the first FIFO interface unit 152a outputs the corresponding parallel transmission data.
The first decoding unit 152c is configured to decode the PCI-E parallel data to generate corresponding parallel transmission data when the first path is formed, and output the parallel transmission data through the first FIFO interface unit 152 a;
the second decoding unit 152d is configured to decode the UFS parallel data to generate corresponding parallel transmission data when the second path is formed, and output the parallel transmission data through the first FIFO interface unit 152 a.
In one embodiment, the second physical layer 150 further includes a second physical medium additional sub-layer and a physical coding sub-layer electrically connected in sequence, the physical coding sub-layer includes a second FIFO interface unit, a third switching unit, a first coding unit, and a second coding unit, and the first coding unit and the second coding unit are electrically connected with the second physical medium additional sub-layer, respectively;
the third switching unit is configured to switch on the second FIFO interface unit and the first encoding unit to form a third path when switching on between the first physical layer 110 and the PCI-E protocol control circuit 140, or to switch on the second FIFO interface unit and the second encoding unit to form a fourth path when switching on between the first physical layer 110 and the UFS protocol conversion circuit 160, according to the first detection signal.
The second FIFO interface unit is configured to receive the externally transmitted second data signal, and transmit the second data signal to the first encoding unit according to the first detection signal when the third path is formed.
The first coding unit is used for coding the second data signal to obtain first coded data and transmitting the first coded data to the second physical medium additional sub-layer.
The second FIFO interface unit is further configured to send a second data signal to the second encoding unit according to the second detection signal when the fourth channel is formed.
The second encoding unit is used for encoding the second data signal to obtain second encoded data and transmitting the second encoded data to the second physical medium additional sub-layer.
The second physical medium attachment sublayer is configured to convert the first encoded data into serial data in a corresponding PCI-E format and send the serial data to the PCI-E protocol control circuit 140, or convert the second encoded data into serial data in a corresponding UFS format and send the serial data to the UFS protocol conversion circuit 160.
The PCI-E protocol control circuit 140 is further configured to send serial data in a corresponding PCI-E format to the first physical layer 110 after being switched in with the first physical layer 110.
The UFS protocol conversion circuit 160 is further configured to convert serial data in a corresponding UFS format into serial data in a corresponding PCI-E format and send the serial data to the first physical layer 110 after being turned on with the first physical layer 110.
The first physical layer 110 is further configured to convert serial data in a PCI-E format corresponding to the second data signal into parallel transmission data for data transmission.
In one embodiment, as shown in FIG. 2, includes a receiver 154a, a arbitration feedback equalizer 154b, a clock recovery circuit 154c, and a deserializer 154d, electrically connected in sequence.
In one embodiment, as shown in FIG. 2, the second physical medium attachment sublayer 156 includes a serializer 156a, a feedback equalizer 156b, and a driver 156c that are electrically connected in sequence.
In one embodiment, as shown in fig. 3, the interface detection unit 120 employs a single-chip microcomputer detection chip 122, where the single-chip microcomputer detection chip 122 is provided with a PCI-E interface detection unit 124 and a UFS interface detection unit 126;
the single chip microcomputer detection chip 122 is used for detecting equipment access information of the PCI-E interface through the PCI-E interface detection unit 124, and generating a first detection signal when equipment access exists in the PCI-E interface;
the single-chip microcomputer detection chip 122 is further configured to detect device access information of the UFS interface through the UFS interface detection unit 126, and generate a second detection signal when device access exists on the UFS interface.
When the single-chip microcomputer detection chip 122 generates the first detection signal, the first detection signal is output to the first switching unit 130 through the first output end OUT1, and the single-chip microcomputer detection chip 122 generates the second detection signal and outputs the second detection signal to the first switching unit 130 through the second output end OUT 2.
The PCI-E interface detecting unit 124 may be implemented by using a conventional PCI-E device insertion detecting method, and the UFS interface detecting unit 126 may be implemented by using a conventional UFS device insertion detecting method.
The single chip microcomputer detection chip is also used for detecting equipment access information of the UFS interface through the UFS interface detection unit, and generating a second detection signal when equipment access exists in the UFS interface.
In one embodiment, as shown in fig. 4, the first decoding unit 152c includes an electrically connected 128b132b decoder 152c1 and a first non-return-to-zero inverse decoder 152c2, as shown in fig. 5, the first encoding unit 158c includes an electrically connected 128b132b encoder 158c1 and a first non-return-to-zero inverse encoder 158c2, as shown in fig. 6, the second decoding unit 152d includes an electrically connected 8b10b decoder 152d1 and a second non-return-to-zero inverse decoder 152d2, as shown in fig. 7, and the second encoding unit 158d includes an electrically connected 8b10b encoder 158d1 and a second non-return-to-zero inverse encoder 158d2.
In one embodiment, the first switching unit 130 employs a single pole double throw switch.
In one embodiment, the first switching unit 130 employs a MOS transistor switching circuit or a triode switching circuit.
In one embodiment, the interface conversion device 100 further includes a phase-locked loop unit, where the phase-locked loop unit is configured to receive the first detection signal sent by the interface detection unit 120 and generate a first set of clock signals, or receive the second detection signal sent by the interface detection unit 120 and generate a second set of clock signals;
the first group of clock signals are used as internal clock signals corresponding to the operation of the first PCI-E interface to the second PCI-E interface, and the second group of clock signals are used as internal clock signals corresponding to the operation of the first PCI-E interface to the UFS interface.
In addition, a test board is provided, and the interface conversion device is arranged on the test board.
In addition, a card reader is provided with the interface conversion device.
That is, the foregoing embodiments are merely examples of the present application, and are not intended to limit the scope of the patent application, and all equivalent structures or equivalent processes using the descriptions and the contents of the present application, such as the combination of technical features of the embodiments, or direct or indirect application to other related technical fields, are included in the scope of the patent protection of the present application.
In addition, the present application may use the same or different reference numerals for structural elements having the same or similar characteristics. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In this application, the term "for example" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as "for example" is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make or use the present application. In the above description, various details are set forth for purposes of explanation.
It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes have not been shown in detail to avoid unnecessarily obscuring the description of the present application. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
Claims (11)
1. An interface conversion device for converting a first PCI-E interface to a second PCI-E interface or UFS interface, the interface conversion device comprising:
the first physical layer is used for receiving a first data signal sent by the external device and generating serial data in PCI-E format;
the interface detection unit is used for detecting the access information of each of the second PCI-E interface and the UFS interface so as to generate a corresponding first detection signal or second detection signal, and sending the first detection signal or the second detection signal to the first switch switching unit;
the first switch switching unit is used for switching on the first physical layer and the PCI-E protocol control circuit according to the first detection signal or switching on the first physical layer and the UFS protocol conversion circuit according to the second detection signal;
the PCI-E protocol control circuit is used for receiving the PCI-E serial data sent by the first physical layer and sending the PCI-E serial data to a second physical layer when the PCI-E protocol control circuit is connected with the first physical layer;
the UFS protocol conversion circuit is configured to receive serial data in a PCI-E format sent by the first physical layer, and convert the serial data in the PCI-E format into serial data in a UFS format for sending to the second physical layer when the UFS protocol conversion circuit is connected to the first physical layer;
the second physical layer is configured to receive a first detection signal or a second detection signal sent by the interface detection unit, and convert serial data in the PCI-E format into corresponding parallel transmission data according to the first detection signal, or convert serial data in the UFS format into corresponding parallel transmission data according to the second detection signal;
the second physical layer comprises a physical decoding sublayer and a first physical medium additional sublayer which are electrically connected in sequence, the physical decoding sublayer comprises a first FIFO interface unit, a second switch switching unit, a first decoding unit and a second decoding unit, and the first decoding unit and the second decoding unit are respectively and electrically connected with the first physical medium additional sublayer; the first physical medium additional sub-layer is used for receiving serial data in a USB format, converting the serial data in the USB format into corresponding USB parallel data and sending the corresponding USB parallel data to the first decoding unit, or receiving serial data in the UFS format, converting the serial data in the UFS format into corresponding UFS parallel data and sending the corresponding UFS parallel data to the second decoding unit; the second switch switching unit is configured to switch on the first FIFO interface unit and the first decoding unit and form a first path when the first physical layer and the PCI-E protocol control circuit are switched on according to the first detection signal, or switch on the first FIFO interface unit and the second decoding unit to form a second path when the first physical layer and the UFS protocol conversion circuit are switched on according to the second detection signal; the first decoding unit is configured to decode the USB parallel data to generate corresponding parallel transmission data when the first path is formed, and output the parallel transmission data through the first FIFO interface unit; the second decoding unit is configured to decode the UFS parallel data to generate corresponding parallel transmission data when the second path is formed, and output the parallel transmission data through the first FIFO interface unit.
2. The interface conversion device according to claim 1, wherein the second physical layer further comprises a second physical medium additional sub-layer and a physical coding sub-layer electrically connected in sequence, the physical coding sub-layer comprising a second FIFO interface unit, a third switch switching unit, a first coding unit and a second coding unit, the first coding unit and the second coding unit being electrically connected with the second physical medium additional sub-layer, respectively;
the third switch switching unit is configured to switch on the second FIFO interface unit and the first encoding unit and form a third path when the first physical layer and the PCI-E protocol control circuit are switched on, or switch on the second FIFO interface unit and the second encoding unit when the first physical layer and the UFS protocol conversion circuit are switched on, according to the first detection signal, to form a fourth path;
the second FIFO interface unit is configured to receive a second data signal sent from the outside, and send the second data signal to the first encoding unit according to the first detection signal when the third path is formed;
the first coding unit is used for coding the second data signal to obtain first coded data and transmitting the first coded data to the second physical medium additional sub-layer;
the second FIFO interface unit is further configured to send the second data signal to the second encoding unit according to the second detection signal when the fourth path is formed;
the second coding unit is used for coding the second data signal to obtain second coded data and transmitting the second coded data to the second physical medium additional sub-layer;
the second physical medium additional sub-layer is configured to convert the first encoded data into serial data in the corresponding PCI-E format and send the serial data to the PCI-E protocol control circuit, or convert the second encoded data into serial data in the corresponding UFS format and send the serial data to the UFS protocol conversion circuit;
the PCI-E protocol control circuit is further used for sending serial data in the corresponding PCI-E format to the first physical layer after being communicated with the first physical layer;
the UFS protocol conversion circuit is further configured to convert serial data in the corresponding UFS format into serial data in the corresponding PCI-E format and send the serial data to the first physical layer after the serial data in the corresponding UFS format is connected to the first physical layer;
the first physical layer is further configured to convert serial data in a PCI-E format corresponding to the second data signal into parallel transmission data for data transmission.
3. The interface conversion device of claim 1, wherein the first physical medium attachment sublayer comprises a receiver, a arbitration feedback equalizer, a clock recovery circuit, and a deserializer electrically connected in sequence.
4. The interface conversion device according to claim 2, wherein the second physical medium additional sub-layer comprises a serializer, a feedback equalizer, and a driver electrically connected in sequence.
5. The interface conversion device according to claim 1, wherein the interface detection unit adopts a single-chip microcomputer detection chip, and the single-chip microcomputer detection chip is provided with a USB interface detection unit and a UFS interface detection unit;
the single chip microcomputer detection chip is used for detecting equipment access information of the USB interface through the USB interface detection unit, and generating the first detection signal when equipment access exists in the USB interface;
the single chip microcomputer detection chip is further used for detecting equipment access information of the UFS interface through the UFS interface detection unit, and generating the second detection signal when equipment access exists in the UFS interface.
6. The interface conversion device of claim 2, wherein the first decoding unit comprises an electrically connected 128b132b decoder and a first non-return-to-zero inverse decoder, the first encoding unit comprises an electrically connected 128b132b encoder and a first non-return-to-zero inverse encoder, the second decoding unit comprises an electrically connected 8b10b decoder and a second non-return-to-zero inverse decoder, and the first encoding unit comprises an electrically connected 8b10b encoder and a second non-return-to-zero inverse encoder.
7. The interface conversion device according to claim 1, wherein the first switch switching unit employs a single pole double throw switch.
8. The interface conversion device according to claim 1, wherein the first switching unit adopts a MOS transistor switching circuit or a triode switching circuit.
9. The interface conversion device according to claim 1, further comprising a phase-locked loop unit for receiving a first detection signal sent by the interface detection unit and generating a first set of clock signals, or receiving a second detection signal sent by the interface detection unit and generating a second set of clock signals;
the first group of clock signals are used as internal clock signals corresponding to the operation of the first PCI-E interface to the second PCI-E interface, and the second group of clock signals are used as internal clock signals corresponding to the operation of the first PCI-E interface to the UFS interface.
10. A test board, characterized in that the test board is provided with an interface conversion device according to any one of claims 1 to 9.
11. A card reader, characterized in that the card reader is provided with an interface conversion device according to any one of claims 1 to 9.
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| US9720866B2 (en) * | 2014-09-11 | 2017-08-01 | Kabushiki Kaisha Toshiba | Interface circuit executing protocol control in compliance with first and second interface standards |
| US9971644B2 (en) * | 2015-12-24 | 2018-05-15 | Intel Corporation | Serial I/O functional tester |
| US20170286357A1 (en) * | 2016-03-30 | 2017-10-05 | Intel Corporation | Method, Apparatus And System For Communicating Between Multiple Protocols |
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| CN101556572A (en) * | 2008-04-07 | 2009-10-14 | 联咏科技股份有限公司 | Interface control circuit |
| CN107391322A (en) * | 2016-05-17 | 2017-11-24 | 三星电子株式会社 | Test equipment based on binary vector |
| CN109032856A (en) * | 2017-06-08 | 2018-12-18 | 三星电子株式会社 | Execute the serial communication interface circuit and electronic device of external loop test |
| CN109947681A (en) * | 2019-03-20 | 2019-06-28 | 天津芯海创科技有限公司 | Stringization/deserializer and high speed interface protocol exchange chip |
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