CN114336197A - Interface conversion device, test board and card reader - Google Patents
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Abstract
The application relates to an interface conversion device, a test board and a card reader, wherein the interface conversion device generates serial data in PCI-E format through a first physical layer, under the control of an interface detection unit, the first physical layer and a PCI-E protocol control circuit are connected through a first switching unit, or the first physical layer and a UFS protocol conversion circuit are connected, the received serial data in PCI-E format is converted into serial data in USB format through the PCI-E protocol control circuit to be sent to a second physical layer, or the received serial data in PCI-E format is converted into serial data in UFS format through the UFS protocol conversion circuit to be sent to the second physical layer, and finally the serial data in USB format is converted into corresponding parallel transmission data through the second physical layer, or the serial data in UFS format is converted into corresponding parallel transmission data, the data transmission efficiency among different equipment interfaces is improved.
Description
Technical Field
The application relates to the technical field of communication, in particular to an interface conversion device, a test board and a card reader.
Background
With the development of storage technology, the transmission amount of the existing data is larger and larger, and the functional requirements on the storage interface are more and more.
The UFS card is generally used for storing data on a mobile phone platform, however, the UFS interface is limited in transmission capacity and low in transmission efficiency.
Disclosure of Invention
In view of this, the present application provides an interface conversion device, a test board and a card reader, which can combine respective advantages of a PCI-E interface and a UFS interface, and can greatly increase the transmission rate of the UFS interface.
An interface conversion device for converting a first PCI-E interface into a second PCI-E interface or a UFS interface, the interface conversion device comprising:
the first physical layer is used for receiving a first data signal sent by an external device and generating serial data in a PCI-E format;
the interface detection unit is used for detecting respective access information of the second PCI-E interface and the UFS interface to generate a corresponding first detection signal or second detection signal and sending the first detection signal or the second detection signal to the first switch switching unit;
the first switch switching unit is used for switching on the first physical layer and the PCI-E protocol control circuit according to the first detection signal or switching on the first physical layer and the UFS protocol conversion circuit according to the second detection signal;
the PCI-E protocol control circuit is used for receiving the serial data in the PCI-E format sent by the first physical layer and sending the serial data in the PCI-E format to the second physical layer when the PCI-E protocol control circuit is communicated with the first physical layer;
the UFS protocol conversion circuit is used for receiving the PCI-E format serial data sent by the first physical layer when the UFS protocol conversion circuit is connected with the first physical layer, and converting the PCI-E format serial data into UFS format serial data to be sent to the second physical layer;
and the second physical layer is used for receiving the first detection signal or the second detection signal sent by the interface detection unit, converting the serial data in the PCI-E format into corresponding parallel transmission data according to the first detection control signal, or converting the serial data in the UFS format into corresponding parallel transmission data according to the second detection control signal.
In one embodiment, the second physical layer includes a physical decoding sublayer and a first physical medium additional sublayer electrically connected in sequence, the physical decoding sublayer includes a first FIFO interface unit, a second switch switching unit, a first decoding unit and a second decoding unit, the first decoding unit and the second decoding unit are respectively electrically connected with the first physical medium additional sublayer;
the first physical medium attachment sublayer is used for receiving serial data in a USB format, converting the serial data in the USB format into corresponding USB parallel data and sending the USB parallel data to the first decoding unit, or receiving serial data in a UFS format, converting the serial data in the UFS format into corresponding UFS parallel data and sending the UFS parallel data to the second decoding unit;
the second switch switching unit is used for switching on the first FIFO interface unit and the first decoding unit to form a first channel when the first physical layer is switched on with the PCI-E protocol control circuit according to the first detection signal, or switching on the first FIFO interface unit and the second decoding unit to form a second channel when the first physical layer is switched on with the UFS protocol conversion circuit according to the second detection signal;
the first decoding unit is used for decoding the USB parallel data to generate corresponding parallel transmission data when the first path is formed, and outputting the parallel transmission data through the first FIFO interface unit;
and the second decoding unit is used for decoding the UFS parallel data to generate corresponding parallel transmission data when the second path is formed, and outputting the data through the first FIFO interface unit.
In one embodiment, the second physical layer further includes a second physical medium additional sublayer and a physical coding sublayer electrically connected in sequence, the physical coding sublayer includes a second FIFO interface unit, a third switch switching unit, a first coding unit and a second coding unit, and the first coding unit and the second coding unit are respectively electrically connected with the second physical medium additional sublayer;
the third switch switching unit is used for switching on the second FIFO interface unit and the first coding unit to form a third channel when the first physical layer and the PCI-E protocol control circuit are switched on or switching on the second FIFO interface unit and the second coding unit to form a fourth channel when the first physical layer and the UFS protocol conversion circuit are switched on according to the first detection signal;
the second FIFO interface unit is used for receiving a second data signal sent from the outside and sending the second data signal to the first encoding unit according to the first detection signal when a third path is formed;
the first coding unit is used for coding the second data signal to obtain first coded data and sending the first coded data to the second physical medium additional sublayer;
the second FIFO interface unit is also used for sending a second data signal to the second encoding unit according to the second detection signal when a fourth path is formed;
the second coding unit is used for coding the second data signal to obtain second coded data and sending the second coded data to the second physical medium additional sublayer;
the second physical medium additional sublayer is used for converting the first coded data into serial data in a corresponding PCI format and sending the serial data to the PCI-E protocol control circuit, or converting the second coded data into serial data in a corresponding UFS format and sending the serial data to the UFS protocol conversion circuit;
the PCI-E protocol control circuit is also used for transmitting the serial data in the corresponding PCI format to the first physical layer after being communicated with the first physical layer;
the UFS protocol conversion circuit is also used for converting the corresponding serial data in the UFS format into the corresponding serial data in the PCI-E format and sending the serial data to the first physical layer after the UFS protocol conversion circuit is connected with the first physical layer;
the first physical layer is also used for converting the PCI-E format serial data corresponding to the second data signal into parallel transmission data for data transmission.
In one embodiment, the first physical medium attachment sublayer comprises a receiver, an arbitration feedback equalizer, a clock recovery circuit, and a deserializer electrically connected in sequence.
In one embodiment, the second physical medium additional sublayer comprises a serializer, a feedback equalizer and a driver electrically connected in sequence.
In one embodiment, the interface detection unit adopts a single chip microcomputer detection chip, and the single chip microcomputer detection chip is provided with a USB interface detection unit and a UFS interface detection unit;
the single chip microcomputer detection chip is used for detecting equipment access information of the USB interface through the USB interface detection unit and generating a first detection signal when the equipment access exists in the USB interface;
the single chip detection chip is further configured to detect device access information of the UFS interface through the UFS interface detection unit, and generate a second detection signal when the UFS interface has device access.
In one embodiment, the first decoding unit comprises a 128b132b decoder and a first non-return-to-zero inversion decoder electrically connected, the first encoding unit comprises a 128b132b encoder and a first non-return-to-zero inversion encoder electrically connected, the second decoding unit comprises an 8b10b decoder and a second non-return-to-zero inversion decoder electrically connected, and the first encoding unit comprises an 8b10b encoder and a second non-return-to-zero inversion encoder electrically connected.
In one embodiment, the first switch switching unit employs a single pole double throw switch.
In one embodiment, the first switch switching unit adopts a MOS transistor switch circuit or a triode switch circuit.
In one embodiment, the interface conversion apparatus further includes a phase-locked loop unit, configured to receive the first detection signal sent by the interface detection unit and generate a first set of clock signals, or receive the second detection signal sent by the interface detection unit and generate a second set of clock signals;
the first group of clock signals are used as internal clock signals corresponding to the first PCI-E interface to the second PCI-E interface when the first PCI-E interface works, and the second group of clock signals are used as internal clock signals corresponding to the first PCI-E interface to the UFS interface when the second PCI-E interface works.
In addition, a test board is also provided, and the test board is provided with the interface conversion device.
In addition, still provide a card reader, the card reader is provided with above-mentioned interface conversion equipment.
The device is provided with a first physical layer, a switch control unit, a first switch switching unit, a PCI-E protocol control circuit, a UFS protocol conversion circuit and a second physical layer, serial data in a PCI-E format is generated through the first physical layer, then the first physical layer and the PCI-E protocol control circuit are connected through the first switch switching unit under the control of the switch control unit, or the first physical layer and the UFS protocol conversion circuit are connected according to a second switch control signal, and when the PCI-E protocol control circuit is connected with the first physical layer, the serial data in the PCI-E format sent by the first physical layer is received and converted into serial data in a USB format to be sent to the second physical layer, or when the PCI-E protocol conversion circuit is connected with the first physical layer, the method comprises the steps of receiving PCI-E format serial data sent by a first physical layer, converting the PCI-E format serial data into UFS format serial data to be sent to a second physical layer, finally receiving a first detection signal or a second detection signal sent by a switch control unit through the second physical layer, converting the USB format serial data into corresponding parallel transmission data according to the first detection signal, or converting the UFS format serial data into corresponding parallel transmission data according to the second detection signal, further enabling external first input data to be converted into second PCI-E interfaces or UFS interfaces through the first PCI-E interfaces to output data, and improving data transmission efficiency among different equipment interfaces.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a control chip for converting PCI-E to USB or UFS interface provided in an embodiment of the present application;
fig. 2 is a schematic structural diagram of a second physical layer according to an embodiment of the present disclosure;
fig. 3 is a schematic circuit structure diagram of a switch control unit according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a first decoding unit according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a first encoding unit according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of a second decoding unit according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of a second encoding unit according to an embodiment of the present application;
fig. 8 is a block diagram of a test board according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. The following embodiments and their technical features may be combined with each other without conflict.
As shown in fig. 1, an interface conversion apparatus 100 is provided for converting a first PCI-E interface into a second PCI-E interface or a UFS interface, where the interface conversion apparatus 100 includes:
the first physical layer 110 is configured to receive a first data signal transmitted by an external device and generate PCI-E formatted serial data.
Where the first input data is parallel input data and the external device comprises a device having a PCI-E plug, the first Physical Layer, also commonly referred to as PHY Layer, is used to convert the received first input data into serial data in PCI-E format.
Among them, PCI-E formats include PCI-E1.0, PCI-E2.0, PCI-E3.0, PCI-E4.0, and PCI-E5.0.
The interface detecting unit 120 is configured to detect respective access information of the second PCI-E interface and the UFS interface to generate a corresponding first detection signal or second detection signal, and send the first detection signal or the second detection signal to the first switching unit 130.
When the PCI-E interface of the control chip 100 has device access, the interface detection unit 120 generates a first detection signal correspondingly, and when the UFS interface of the control chip 100 has device access, the interface detection unit 120 generates a second detection signal correspondingly.
In an embodiment, the interface detection unit 120 may be implemented by a single chip or a MOS transistor switch circuit or a triode switch circuit.
Wherein, the PCI-E interface and the UFS interface can not work simultaneously.
In an embodiment, if both the PCI-E interface and the UFS interface have device access, the interface detection unit 120 may generate a corresponding detection signal according to an order of the device access corresponding to the PCI-E interface and the device access corresponding to the UFS interface, for example, when the device corresponding to the PCI-E interface is accessed first, the interface detection unit 120 may generate a corresponding first detection signal; when the device corresponding to the UFS interface is accessed first, the interface detection unit 120 generates a corresponding second detection signal.
The first switching unit 130 is configured to switch on the first physical layer 110 and the PCI-E protocol control circuit 140 according to the first detection signal, or switch on the first physical layer 110 and the UFS protocol conversion circuit 160 according to the second detection signal.
The PCI-E protocol control circuit 140 is configured to receive the PCI-E formatted serial data transmitted by the first physical layer 110 and transmit the PCI-E formatted serial data to the second physical layer 150 when the PCI-E protocol control circuit is connected to the first physical layer 110.
The UFS protocol conversion circuit 160 is configured to receive the PCI-E format serial data sent by the first physical layer 110 when the first physical layer 110 is connected to the UFS protocol conversion circuit, and convert the PCI-E format serial data into UFS format serial data to send to the second physical layer 150.
The UFS protocol is an abbreviation of Universal Flash Storage (Universal Flash memory) protocol.
The UFS protocol includes UFS2.2, UFS3.0, or UFS 3.1.
The second physical layer 150 is configured to receive the first detection signal or the second detection signal sent by the interface detection unit 120, and convert the PCI-E format serial data into corresponding parallel transmission data according to the first detection control signal, or convert the UFS format serial data into corresponding parallel transmission data according to the second detection control signal.
The interface conversion device 100 is provided with a first physical layer 110, a switch control unit, a first switching unit 130, a PCI-E protocol control circuit 140, a UFS protocol conversion circuit 160, and a second physical layer 150, generates PCI-E format serial data by the first physical layer 110, then under the control of the switch control unit, turns on the first physical layer 110 and the PCI-E protocol control circuit 140 by the first switching unit 130, or turns on the first physical layer 110 and the UFS protocol conversion circuit 160 according to a second detection signal, further receives PCI-E format serial data transmitted by the first physical layer 110 when the interface conversion device is turned on with the first physical layer 110 by the PCI-E protocol control circuit 140, and converts the PCI-E format serial data into PCI-E format serial data to be transmitted to the second physical layer 150, or turns on with the first physical layer 110 by the UFS protocol conversion circuit 160, the method includes the steps of receiving PCI-E format serial data sent by a first physical layer 110, converting the PCI-E format serial data into UFS format serial data to be sent to a second physical layer 150, finally receiving a first detection signal or a second detection signal sent by a switch control unit through the second physical layer 150, converting the PCI-E format serial data into corresponding parallel transmission data according to the first detection signal, or converting the UFS format serial data into corresponding parallel transmission data according to the second detection signal, and further enabling external first input data to be converted into second PCI-E interfaces or UFS interfaces through the first PCI-E interfaces to be output in a data output mode, and improving data transmission efficiency among different equipment interfaces.
In one embodiment, the second physical layer 150 includes a physical decoding sublayer 152 and a first physical medium addition sublayer 154 electrically connected in sequence, the physical decoding sublayer 152 includes a first FIFO interface unit 152a, a second switching unit 152b, a first decoding unit 152c and a second decoding unit 152d, and the first decoding unit 152c and the second decoding unit 152d are electrically connected to the first physical medium addition sublayer 154 respectively.
The first physical medium attachment sublayer 154 is configured to receive PCI-E formatted serial data, convert the PCI-E formatted serial data into corresponding PCI-E parallel data, and send the PCI-E parallel data to the first decoding unit 152c, or receive UFS formatted serial data, convert the UFS formatted serial data into corresponding UFS parallel data, and send the UFS parallel data to the second decoding unit 152 d.
The second switching unit 152b is configured to turn on the first FIFO interface unit 152a and the first decoding unit 152c and form a first path when the connection is made between the first physical layer 110 and the PCI-E protocol control circuit 140 according to the first detection signal, or turn on the first FIFO interface unit 152a and the second decoding unit 152d and form a second path when the connection is made between the first physical layer 110 and the UFS protocol conversion circuit 160 according to the second detection signal.
As can be seen from fig. 1 and fig. 2, in the process of forming the first path, the first physical layer 110, the first switching unit 130, the PCI-E protocol control circuit 140, the first physical medium attachment sublayer 154, the first decoding unit 152c, the second switching unit 152b, and the first FIFO interface unit 152a form a path, the first physical layer 110 inputs the first input data, and the first FIFO interface unit 152a outputs the corresponding parallel transmission data.
Similarly, as can be seen from fig. 1 and fig. 2, in the process of forming the second path, the first physical layer 110, the first switching unit 130, the UFS protocol conversion unit 140, the first physical medium addition sublayer 154, the second decoding unit 152d, the second switching unit 152b, and the first FIFO interface unit 152a form a path, the first physical layer 110 inputs the first input data, and the first FIFO interface unit 152a outputs the corresponding parallel transmission data.
The first decoding unit 152c is configured to decode the PCI-E parallel data to generate corresponding parallel transmission data when the first path is formed, and output the parallel transmission data through the first FIFO interface unit 152 a;
the second decoding unit 152d is configured to decode the UFS parallel data to generate corresponding parallel transmission data when the second path is formed, and output the data through the first FIFO interface unit 152 a.
In one embodiment, the second physical layer 150 further includes a second physical medium additional sublayer and a physical coding sublayer electrically connected in sequence, the physical coding sublayer includes a second FIFO interface unit, a third switching unit, a first coding unit and a second coding unit, and the first coding unit and the second coding unit are respectively electrically connected to the second physical medium additional sublayer;
the third switching unit is configured to switch on the second FIFO interface unit and the first encoding unit and form a third path when the first physical layer 110 and the PCI-E protocol control circuit 140 are connected, or switch on the second FIFO interface unit and the second encoding unit and form a fourth path when the first physical layer 110 and the UFS protocol conversion circuit 160 are connected, according to the first detection signal.
The second FIFO interface unit is used for receiving a second data signal sent from the outside, and sending the second data signal to the first encoding unit according to the first detection signal when a third path is formed.
The first coding unit is used for coding the second data signal to obtain first coded data, and sending the first coded data to the second physical medium additional sub-layer.
The second FIFO interface unit is further used for sending the second data signal to the second encoding unit according to the second detection signal when the fourth path is formed.
The second coding unit is used for coding the second data signal to obtain second coded data, and sending the second coded data to the second physical medium additional sub-layer.
The second physical medium additional sublayer is used for converting the first encoded data into serial data in a corresponding PCI format and sending the serial data to the PCI-E protocol control circuit 140, or converting the second encoded data into serial data in a corresponding UFS format and sending the serial data to the UFS protocol conversion circuit 160.
The PCI-E protocol control circuit 140 is further configured to transmit the serial data in the corresponding PCI format to the first physical layer 110 after the connection with the first physical layer 110.
The UFS protocol conversion circuit 160 is further configured to convert the serial data in the UFS format into the serial data in the PCI-E format after the UFS protocol conversion circuit is connected to the first physical layer 110, and send the serial data to the first physical layer 110.
The first physical layer 110 is also configured to convert the PCI-E formatted serial data corresponding to the second data signal into parallel transmission data for data transmission.
In one embodiment, as shown in fig. 2, the receiver 154a, the arbitration feedback equalizer 154b, the clock recovery circuit 154c, and the deserializer 154d are electrically connected in sequence.
In one embodiment, as shown in fig. 2, the second physical medium additional sub-layer 156 includes a serializer 156a, a feedback equalizer 156b and a driver 156c electrically connected in sequence.
In one embodiment, as shown in fig. 3, the interface detection unit 120 employs a single chip microcomputer detection chip 122, and the single chip microcomputer detection chip 122 is provided with a PCI-E interface detection unit 124 and a UFS interface detection unit 126;
the single chip microcomputer detection chip 122 is configured to detect the device access information of the PCI-E interface through the PCI-E interface detection unit 124, and generate a first detection signal when the PCI-E interface has device access;
the single chip microcomputer detection chip 122 is further configured to detect device access information of the UFS interface through the UFS interface detection unit 126, and generate a second detection signal when the UFS interface has device access.
When the single chip microcomputer detection chip 122 generates the first detection signal, the first detection signal is output to the first switching unit 130 through the first output terminal OUT1, and the second detection signal is generated by the single chip microcomputer detection chip 122 and output to the first switching unit 130 through the second output terminal OUT 2.
The PCI-E interface detection unit 124 may be implemented by using a conventional PCI-E device insertion detection method, and the UFS interface detection unit 126 may also be implemented by using a conventional UFS device insertion detection method.
The single chip detection chip is further configured to detect device access information of the UFS interface through the UFS interface detection unit, and generate a second detection signal when the UFS interface has device access.
In one embodiment, as shown in fig. 4, the first decoding unit 152c includes a 128b132b decoder 152c1 and a first non-return-to-zero inversion decoder 152c2 electrically connected, as shown in fig. 5, the first encoding unit 158c includes a 128b132b encoder 158c1 and a first non-return-to-zero inversion encoder 158c2 electrically connected, as shown in fig. 6, the second decoding unit 152d includes an 8b10b decoder 152d1 and a second non-return-to-zero inversion decoder 152d2 electrically connected, as shown in fig. 7, the second encoding unit 158d includes an 8b10b encoder 158d1 and a second non-return-to-zero inversion encoder 158d2 electrically connected.
In one embodiment, the first switching unit 130 employs a single pole double throw switch.
In one embodiment, the first switching unit 130 employs a MOS transistor switching circuit or a triode switching circuit.
In one embodiment, the interface conversion apparatus 100 further includes a phase-locked loop unit, configured to receive the first detection signal sent by the interface detection unit 120 and generate a first set of clock signals, or receive the second detection signal sent by the interface detection unit 120 and generate a second set of clock signals;
the first group of clock signals are used as internal clock signals corresponding to the first PCI-E interface to the second PCI-E interface when the first PCI-E interface works, and the second group of clock signals are used as internal clock signals corresponding to the first PCI-E interface to the UFS interface when the second PCI-E interface works.
In addition, a test board is also provided, and the test board is provided with the interface conversion device.
In addition, still provide a card reader, the card reader is provided with above-mentioned interface conversion equipment.
That is, the above description is only an embodiment of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by using the contents of the specification and the drawings, such as mutual combination of technical features between various embodiments, or direct or indirect application to other related technical fields, are included in the scope of the present application.
In addition, structural elements having the same or similar characteristics may be identified by the same or different reference numerals. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In this application, the word "for example" is used to mean "serving as an example, instance, or illustration". Any embodiment described herein as "for example" is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make and use the present application. In the foregoing description, various details have been set forth for the purpose of explanation.
It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes are not shown in detail to avoid obscuring the description of the present application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
Claims (12)
1. An interface conversion apparatus, for converting a first PCI-E interface into a second PCI-E interface or a UFS interface, the interface conversion apparatus comprising:
the first physical layer is used for receiving a first data signal sent by an external device and generating serial data in a PCI-E format;
the interface detection unit is used for detecting respective access information of the second PCI-E interface and the UFS interface to generate a corresponding first detection signal or a second detection signal, and sending the first detection signal or the second detection signal to the first switch switching unit;
the first switch switching unit is used for switching on the first physical layer and the PCI-E protocol control circuit according to the first detection signal or switching on the first physical layer and the UFS protocol conversion circuit according to the second detection signal;
the PCI-E protocol control circuit is used for receiving the serial data in the PCI-E format sent by the first physical layer and sending the serial data in the PCI-E format to the second physical layer when the PCI-E protocol control circuit is connected with the first physical layer;
the UFS protocol conversion circuit is configured to receive PCI-E formatted serial data sent by the first physical layer when the UFS protocol conversion circuit is connected to the first physical layer, and convert the PCI-E formatted serial data into UFS formatted serial data to send to the second physical layer;
the second physical layer is configured to receive the first detection signal or the second detection signal sent by the interface detection unit, and convert the serial data in the PCI-E format into corresponding parallel transmission data according to the first detection control signal, or convert the serial data in the UFS format into corresponding parallel transmission data according to the second detection control signal.
2. The interface conversion apparatus according to claim 1, wherein the second physical layer comprises a physical decoding sublayer and a first physical medium additional sublayer electrically connected in sequence, the physical decoding sublayer comprises a first FIFO interface unit, a second switch switching unit, a first decoding unit and a second decoding unit, and the first decoding unit and the second decoding unit are electrically connected to the first physical medium additional sublayer respectively;
the first physical medium attachment sublayer is used for receiving the serial data in the USB format, converting the serial data in the USB format into corresponding USB parallel data and sending the USB parallel data to the first decoding unit, or receiving the serial data in the UFS format, converting the serial data in the UFS format into corresponding UFS parallel data and sending the UFS parallel data to the second decoding unit;
the second switch switching unit is configured to switch on the first FIFO interface unit and the first decoding unit to form a first path when the first physical layer and the PCI-E protocol control circuit are connected, according to the first detection signal, or switch on the first FIFO interface unit and the second decoding unit to form a second path when the first physical layer and the UFS protocol conversion circuit are connected, according to the second detection signal;
the first decoding unit is used for decoding the USB parallel data to generate corresponding parallel transmission data when the first channel is formed, and outputting the parallel transmission data through the first FIFO interface unit;
and the second decoding unit is used for decoding the UFS parallel data to generate corresponding parallel transmission data when the second channel is formed, and outputting the data through the first FIFO interface unit.
3. The interface conversion apparatus according to claim 2, wherein the second physical layer further comprises a second physical medium additional sublayer and a physical coding sublayer electrically connected in sequence, the physical coding sublayer comprises a second FIFO interface unit, a third switch switching unit, a first coding unit and a second coding unit, and the first coding unit and the second coding unit are electrically connected to the second physical medium additional sublayer respectively;
the third switch switching unit is configured to, according to the first detection signal, turn on the second FIFO interface unit and the first encoding unit and form a third path when the connection between the first physical layer and the PCI-E protocol control circuit is established, or turn on the second FIFO interface unit and the second encoding unit and form a fourth path when the connection between the first physical layer and the UFS protocol conversion circuit is established;
the second FIFO interface unit is used for receiving a second data signal sent from the outside, and sending the second data signal to the first encoding unit according to the first detection signal when the third path is formed;
the first coding unit is configured to perform coding processing on the second data signal to obtain first coded data, and send the first coded data to the second physical medium additional sublayer;
the second FIFO interface unit is further used for sending the second data signal to the second encoding unit according to the second detection signal when the fourth path is formed;
the second coding unit is configured to perform coding processing on the second data signal to obtain second coded data, and send the second coded data to the second physical medium additional sublayer;
the second physical medium additional sublayer is used for converting the first coded data into corresponding serial data in the PCI format and sending the serial data to the PCI-E protocol control circuit, or converting the second coded data into corresponding serial data in the UFS format and sending the serial data to the UFS protocol conversion circuit;
the PCI-E protocol control circuit is also used for sending the corresponding serial data in the PCI format to the first physical layer after the PCI-E protocol control circuit is connected with the first physical layer;
the UFS protocol conversion circuit is further configured to convert the corresponding serial data in the UFS format into the corresponding serial data in the PCI-E format and send the converted serial data to the first physical layer after the UFS protocol conversion circuit is connected to the first physical layer;
the first physical layer is further configured to convert the PCI-E formatted serial data corresponding to the second data signal into parallel transmission data for data transmission.
4. The interface converting apparatus as claimed in claim 2, wherein the first physical medium attachment sublayer comprises a receiver, an arbitration feedback equalizer, a clock recovery circuit and a deserializer electrically connected in sequence.
5. The interface converting apparatus according to claim 3, wherein the second physical medium additional sub-layer comprises a serializer, a feedback equalizer and a driver electrically connected in sequence.
6. The interface conversion device according to claim 1, wherein the interface detection unit employs a single chip microcomputer detection chip, and the single chip microcomputer detection chip is provided with a USB interface detection unit and a UFS interface detection unit;
the single chip microcomputer detection chip is used for detecting equipment access information of the USB interface through the USB interface detection unit and generating the first detection signal when the equipment access exists in the USB interface;
the single chip microcomputer detection chip is also used for detecting the equipment access information of the UFS interface through the UFS interface detection unit and generating the second detection signal when the equipment access exists in the UFS interface.
7. The interface converting apparatus as claimed in claim 1, wherein the first decoding unit comprises a 128b132b decoder and a first nrz decoder electrically connected, the first encoding unit comprises a 128b132b encoder and a first nrz encoder electrically connected, the second decoding unit comprises an 8b10b decoder and a second nrz decoder electrically connected, and the first encoding unit comprises an 8b10b encoder and a second nrz encoder electrically connected.
8. The interface converting apparatus according to claim 1, wherein the first switch switching unit employs a single-pole double-throw switch.
9. The interface conversion apparatus according to claim 1, wherein the first switch switching unit employs a MOS transistor switch circuit or a triode switch circuit.
10. The interface conversion apparatus according to claim 1, further comprising a phase-locked loop unit, wherein the phase-locked loop unit is configured to receive the first detection signal sent by the interface detection unit and generate a first set of clock signals, or receive the second detection signal sent by the interface detection unit and generate a second set of clock signals;
the first group of clock signals are used as internal clock signals corresponding to the first PCI-E interface to the second PCI-E interface when working, and the second group of clock signals are used as internal clock signals corresponding to the first PCI-E interface to the UFS interface when working.
11. A test board, characterized in that it is provided with an interface conversion device according to any one of claims 1 to 10.
12. A card reader, characterized in that the card reader is provided with an interface conversion device according to any one of 1 to 10.
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