US20160077994A1 - Interface circuit - Google Patents
Interface circuit Download PDFInfo
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- US20160077994A1 US20160077994A1 US14/657,281 US201514657281A US2016077994A1 US 20160077994 A1 US20160077994 A1 US 20160077994A1 US 201514657281 A US201514657281 A US 201514657281A US 2016077994 A1 US2016077994 A1 US 2016077994A1
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- interface
- interface circuit
- circuit according
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
Definitions
- Embodiments described herein relate generally to an interface circuit.
- FIG. 1 is a schematic block diagram illustrating a configuration of an interface circuit according to a first embodiment
- FIG. 2 is a block diagram illustrating a configuration of the interface circuit illustrated in FIG. 1 in conformity with UFS standard;
- FIG. 3 is a block diagram illustrating a configuration of the interface circuit illustrated in FIG. 1 in conformity with M-PCIe standard;
- FIG. 4 is a block diagram illustrating a configuration of the interface circuit illustrated in FIG. 1 in conformity with PCIe standard.
- FIG. 5 is a block diagram illustrating a configuration of a storage device to which an interface circuit according to a second embodiment is applied.
- an interface circuit includes a first module, a second module, and a third module.
- the first module is responsible for protocol control in compliance with a first interface standard.
- the second module is provided separately from the first interface module and is responsible for protocol control in compliance with a second interface standard.
- the third module is responsible for a physical layer shared between the first interface standard and the second interface standard.
- FIG. 1 is a schematic block diagram illustrating a configuration of an interface circuit according to a first embodiment.
- an interface circuit 1 includes a UFS (Universal Flash Storage) higher-level module 2 , a transaction module 3 , a data link module 4 , switch control units 5 and 9 , a UniPro (Unified Protocol) module 6 , MAC (Media Access Layer) modules 7 and 8 , and PHY (Physical Layer) modules 10 and 11 .
- the UFS higher-level module 2 , the UniPro module 6 , and the PHY module 10 can conform to UFS standard.
- the transaction module 3 , the data link module 4 , the MAC module 7 , and the PHY module 10 can conform to M-PCIe (Mobile-Peripheral Component Interconnect Express) standard.
- M-PCIe Mobile-Peripheral Component Interconnect Express
- the transaction module 3 , the data link module 4 , the MAC module 8 , and the PHY module 11 can conform to PCIe (Peripheral Component Interconnect Express) standard.
- the PHY module 10 here is shared between the UFS standard and the M-PCIe standard.
- the transaction module 3 and the data link module 4 are shared between the M-PCIe standard and the PCIe standard.
- the switch control unit 5 can switch the destination for connection of the data link module 4 between the MAC module 7 and the MAC module 8 .
- the switch control unit 9 can switch the destination for connection of the PHY module 10 between the UniPro module 6 and the MAC module 7 .
- the UFS standard defines specifications for high-speed serial data communications applied to digital cameras, mobile phones, home electronic devices, and the like.
- the PCIe standard defines specifications for high-speed serial data communications applied to personal computers and the like.
- the M-PCIe standard defines specifications for high-speed serial data communications for graphic extension applied to notebook computers and the like based on the PCI
- the UFS higher-level module 2 and the UniPro module 6 can be responsible for protocol control in conformity with the UFS standard.
- the UFS higher-level module 2 can be responsible for UPIU transmission/reception.
- data, commands, queries, and the like are transferred in packets.
- Write command is equivalent to a command transmission packet (command UPIU).
- the command transfer packet has a header, a command description portion in a packet body section, and a simplified SCSI (small computer system interface) command stored in the command description portion.
- the SCSI command includes a write command, an address, and a write data size.
- the UniPro module 6 can conform to a communication protocol for interconnection of devices. For example, under the UniPro, the UniPro module 6 can exchange data between clock domains, select a device as a destination for connection, establish connection, and the like.
- the PHY module 10 can be responsible for a physical layer shared between the UFS standard and the M-PCIe standard.
- the PHY module 10 here can conform to a MIPI (Mobile Industry Processor Interface) M-PHY.
- the MIPI defines interface standards for cameras and displays in mobile devices.
- the MIPI M-PHY is an interface supporting both its own clock (source-synchronous) and an embedded clock.
- the MIPI M-PHY can realize 8-bit/10-bit conversion, control code insertion/removal, serial-parallel conversion, differential signal conversion, and the like.
- the transaction module 3 and the data link module 4 can be responsible for protocol control shared between the PCIe standard and the M-PCIe standard.
- the transaction module 3 can be responsible for a transaction layer.
- the transaction layer basically can be in charge of generation and decoding of a transaction layer packet (TLP).
- TLP transaction layer packet
- the transaction layer generates a TLP according to a request from a CPU.
- the transaction layer decrypts it and passes the request to the CPU.
- the transaction layer retrieves a payload and status from it and passes them to the CPU.
- the transaction layer optionally checks data consistency end to end.
- the data link module 4 can be responsible for a data link layer.
- the data link layer basically can be in charge of management of a PCIe link, and detection and correction of an error.
- the data link layer can perform data exchange, error detection and re-transmission, free control packet communication, initialization, power management, and the like.
- the PHY module 11 can be responsible for a physical layer in compliance with the PCIe standard.
- the PHY module 11 here can conform to PCIe PHY.
- the PCIe PHY can realize 8-bit/10-bit conversion, elastic buffer/receiver detection, serial-parallel conversion, analog buffer, and the like.
- the MAC module 7 can realize access to the PHY module 10 .
- the MAC module 8 can realize access to the PHY module 11 .
- the MAC modules 7 and 8 can realize byte stripping, link training state machine, scramble/descramble, inter-lane de-skew, and the like.
- the UniPro module 6 , the MAC module 7 , and the PHY module 10 can conform to RMMI (Reference M-PHY Module Interface).
- the MAC module 8 and the PHY module 11 can conform to PIPE (Physical Interface for PCI Express).
- a first pin that is intrinsic to UFS standard, a second pin that is intrinsic to M-PCIe standard, and a third pin that is intrinsic to PCIe standard may be provided for the interface circuit 1 .
- FIG. 2 is a block diagram illustrating a configuration of the interface circuit illustrated in FIG. 1 in conformity with the UFS standard.
- the PHY module 10 is connected to the UniPro module 6 via the switch control unit 9 . Accordingly, the UFS higher-level module 2 , the UniPro module 6 , and the PHY module 10 constitute a UFS module 1 A. As a result, the interface circuit 1 can transmit and receive data in conformity with the UFS standards.
- FIG. 3 is a block diagram illustrating a configuration of the interface circuit illustrated in FIG. 1 in conformity with the M-PCIe standard.
- the PHY module 10 is connected to the MAC module 7 via the switch control unit 9 .
- the MAC module 7 is connected to the data link module 4 via the switch control unit 5 .
- the transaction module 3 , the data link module 4 , the MAC module 7 , and the PHY module 10 constitute an M-PCIe module 1 B.
- the interface circuit 1 can transmit and receive data in conformity with the M-PCIe standard.
- FIG. 4 is a block diagram illustrating a configuration of the interface circuit illustrated in FIG. 1 in conformity with the PCIe standard.
- the interface circuit 1 when the interface circuit 1 is to conform to the PCIe standard, the MAC module 8 is connected to the data link module 4 via the switch control unit 5 . Accordingly, the transaction module 3 , the data link module 4 , the MAC module 8 , and the PHY module 11 constitute a PCIe module 1 C. As a result, the interface circuit 1 can transmit and receive data in conformity with the PCIe standard.
- Sharing the PHY module 10 between the UFS standard and the M-PCIe standard eliminates the need to provide the PHY module 10 for each of the UFS standard and the M-PCIe standard.
- sharing the transaction module 3 and the data link module 4 between the M-PCIe standard and the PCIe standard eliminates the need to provide the transaction module 3 and the data link module 4 for each of the M-PCIe standard and the PCIe standard. This makes it possible to allow the interface circuit 1 to conform to the UFS standard, the PCIe standard, and the M-PCIe standard, while suppressing increase in parts count.
- the interface circuit 1 conforms to the UFS standard, the PCIe standard, and the M-PCIe standard as an example.
- the present invention may be applied to an interface circuit in conformity with the UFS standard and the PCIe standard, or an interface circuit in conformity with the PCIe standard and the M-PCIe standard.
- FIG. 5 is a block diagram illustrating a configuration of a storage device to which an interface circuit according to a second embodiment is applied.
- a storage device 31 includes a memory element 32 and a memory controller 35 .
- the memory controller 35 has an interface circuit 21 and a CPU 33 mounted therein.
- a host 34 is connected to the memory element 32 and the CPU 33 via the interface circuit 21 .
- the host 34 may be a personal computer, a notebook computer, a digital camera, a mobile phone, or a processor that gives instructions to the memory controller 35 .
- the storage device 31 may be an external storage device such as an SSD.
- the memory element 32 can use an NAND flash memory, and the memory controller 35 can use an NAND controller.
- the interface circuit 21 is formed such that decoders 12 and 13 are added to the interface circuit 1 illustrated in FIG. 1 .
- the decoder 12 can instruct the switch control unit 9 to switch the destination for connection of the PHY module 10 according to a selection signal SE 1 .
- the decoder 13 can instruct the switch control unit 5 to switch the destination for connection of the data link module 4 according to a selection signal SE 2 .
- a reception channel MRCh and a transmission channel MTCh can be provided between the host 34 and the PHY module 10 .
- a reception channel PRCh and a transmission channel PTCh can be provided between the host 34 and the PHY module 11 .
- the PHY module 10 is connected to the UniPro module 6 via the switch control unit 9 to allow the interface circuit 21 to conform to the UFS standard.
- the PHY module 10 is connected to the MAC module 7 via the switch control unit 9 and the MAC module 7 is connected to the data link module 4 via the switch control unit 5 to allow the interface circuit 21 to conform to the M-PCIe standard.
- the MAC module 8 is connected to the data link module 4 via the switch control unit 5 to allow the interface circuit 21 to conform to the PCIe standard. This allows the storage device 31 to realize data communications with the host 34 in conformity with a different standard without having to replace the interface circuit 21 .
Abstract
Description
- This application is based upon and claims the benefit of priority from U.S. Provisional Application No. 62/049,173, filed on Sep. 11, 2014; the entire contents of which are incorporated herein by reference.
- Embodiments described herein relate generally to an interface circuit.
- There are various standards for interface circuits depending on high-speed performance, portability, and the like of a device. This causes the device to be equipped with individual interface circuits in conformity with the standards, which leads to increase in parts count.
-
FIG. 1 is a schematic block diagram illustrating a configuration of an interface circuit according to a first embodiment; -
FIG. 2 is a block diagram illustrating a configuration of the interface circuit illustrated inFIG. 1 in conformity with UFS standard; -
FIG. 3 is a block diagram illustrating a configuration of the interface circuit illustrated inFIG. 1 in conformity with M-PCIe standard; -
FIG. 4 is a block diagram illustrating a configuration of the interface circuit illustrated inFIG. 1 in conformity with PCIe standard; and -
FIG. 5 is a block diagram illustrating a configuration of a storage device to which an interface circuit according to a second embodiment is applied. - In general, according to one embodiment, an interface circuit includes a first module, a second module, and a third module. The first module is responsible for protocol control in compliance with a first interface standard. The second module is provided separately from the first interface module and is responsible for protocol control in compliance with a second interface standard. The third module is responsible for a physical layer shared between the first interface standard and the second interface standard.
- Exemplary embodiments of an interface circuit will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments.
-
FIG. 1 is a schematic block diagram illustrating a configuration of an interface circuit according to a first embodiment. - Referring to
FIG. 1 , aninterface circuit 1 includes a UFS (Universal Flash Storage) higher-level module 2, atransaction module 3, adata link module 4,switch control units module 6, MAC (Media Access Layer)modules modules level module 2, the UniPromodule 6, and thePHY module 10 can conform to UFS standard. Thetransaction module 3, thedata link module 4, theMAC module 7, and thePHY module 10 can conform to M-PCIe (Mobile-Peripheral Component Interconnect Express) standard. Thetransaction module 3, thedata link module 4, theMAC module 8, and thePHY module 11 can conform to PCIe (Peripheral Component Interconnect Express) standard. ThePHY module 10 here is shared between the UFS standard and the M-PCIe standard. Thetransaction module 3 and thedata link module 4 are shared between the M-PCIe standard and the PCIe standard. Theswitch control unit 5 can switch the destination for connection of thedata link module 4 between theMAC module 7 and theMAC module 8. Theswitch control unit 9 can switch the destination for connection of thePHY module 10 between the UniPromodule 6 and theMAC module 7. The UFS standard defines specifications for high-speed serial data communications applied to digital cameras, mobile phones, home electronic devices, and the like. The PCIe standard defines specifications for high-speed serial data communications applied to personal computers and the like. The M-PCIe standard defines specifications for high-speed serial data communications for graphic extension applied to notebook computers and the like based on the PCIe standard. - The UFS higher-
level module 2 and the UniPromodule 6 can be responsible for protocol control in conformity with the UFS standard. For example, the UFS higher-level module 2 can be responsible for UPIU transmission/reception. Under the UFS standard, data, commands, queries, and the like are transferred in packets. Write command is equivalent to a command transmission packet (command UPIU). The command transfer packet has a header, a command description portion in a packet body section, and a simplified SCSI (small computer system interface) command stored in the command description portion. The SCSI command includes a write command, an address, and a write data size. The UniPromodule 6 can conform to a communication protocol for interconnection of devices. For example, under the UniPro, the UniPromodule 6 can exchange data between clock domains, select a device as a destination for connection, establish connection, and the like. - The
PHY module 10 can be responsible for a physical layer shared between the UFS standard and the M-PCIe standard. ThePHY module 10 here can conform to a MIPI (Mobile Industry Processor Interface) M-PHY. The MIPI defines interface standards for cameras and displays in mobile devices. The MIPI M-PHY is an interface supporting both its own clock (source-synchronous) and an embedded clock. For example, the MIPI M-PHY can realize 8-bit/10-bit conversion, control code insertion/removal, serial-parallel conversion, differential signal conversion, and the like. - The
transaction module 3 and thedata link module 4 can be responsible for protocol control shared between the PCIe standard and the M-PCIe standard. - The
transaction module 3 can be responsible for a transaction layer. The transaction layer basically can be in charge of generation and decoding of a transaction layer packet (TLP). For example, the transaction layer generates a TLP according to a request from a CPU. In addition, upon receipt of a request TLP, the transaction layer decrypts it and passes the request to the CPU. Further, upon receipt of a completion TLP, the transaction layer retrieves a payload and status from it and passes them to the CPU. The transaction layer optionally checks data consistency end to end. - The
data link module 4 can be responsible for a data link layer. The data link layer basically can be in charge of management of a PCIe link, and detection and correction of an error. For example, the data link layer can perform data exchange, error detection and re-transmission, free control packet communication, initialization, power management, and the like. - The
PHY module 11 can be responsible for a physical layer in compliance with the PCIe standard. ThePHY module 11 here can conform to PCIe PHY. For example, the PCIe PHY can realize 8-bit/10-bit conversion, elastic buffer/receiver detection, serial-parallel conversion, analog buffer, and the like. - The
MAC module 7 can realize access to thePHY module 10. TheMAC module 8 can realize access to thePHY module 11. For example, theMAC modules - In addition, the UniPro
module 6, theMAC module 7, and thePHY module 10 can conform to RMMI (Reference M-PHY Module Interface). TheMAC module 8 and thePHY module 11 can conform to PIPE (Physical Interface for PCI Express). - In addition, a first pin that is intrinsic to UFS standard, a second pin that is intrinsic to M-PCIe standard, and a third pin that is intrinsic to PCIe standard may be provided for the
interface circuit 1. -
FIG. 2 is a block diagram illustrating a configuration of the interface circuit illustrated inFIG. 1 in conformity with the UFS standard. - Referring to
FIG. 2 , when theinterface circuit 1 is to conform to the UFS standard, thePHY module 10 is connected to theUniPro module 6 via theswitch control unit 9. Accordingly, the UFS higher-level module 2, theUniPro module 6, and thePHY module 10 constitute aUFS module 1A. As a result, theinterface circuit 1 can transmit and receive data in conformity with the UFS standards. -
FIG. 3 is a block diagram illustrating a configuration of the interface circuit illustrated inFIG. 1 in conformity with the M-PCIe standard. - Referring to
FIG. 3 , when theinterface circuit 1 is to conform to the M-PCIe standard, thePHY module 10 is connected to theMAC module 7 via theswitch control unit 9. In addition, theMAC module 7 is connected to thedata link module 4 via theswitch control unit 5. Accordingly, thetransaction module 3, thedata link module 4, theMAC module 7, and thePHY module 10 constitute an M-PCIe module 1B. As a result, theinterface circuit 1 can transmit and receive data in conformity with the M-PCIe standard. -
FIG. 4 is a block diagram illustrating a configuration of the interface circuit illustrated in FIG. 1 in conformity with the PCIe standard. - Referring to
FIG. 4 , when theinterface circuit 1 is to conform to the PCIe standard, theMAC module 8 is connected to thedata link module 4 via theswitch control unit 5. Accordingly, thetransaction module 3, thedata link module 4, theMAC module 8, and thePHY module 11 constitute aPCIe module 1C. As a result, theinterface circuit 1 can transmit and receive data in conformity with the PCIe standard. - Sharing the
PHY module 10 between the UFS standard and the M-PCIe standard eliminates the need to provide thePHY module 10 for each of the UFS standard and the M-PCIe standard. In addition, sharing thetransaction module 3 and thedata link module 4 between the M-PCIe standard and the PCIe standard eliminates the need to provide thetransaction module 3 and thedata link module 4 for each of the M-PCIe standard and the PCIe standard. This makes it possible to allow theinterface circuit 1 to conform to the UFS standard, the PCIe standard, and the M-PCIe standard, while suppressing increase in parts count. - In the foregoing embodiment, the
interface circuit 1 conforms to the UFS standard, the PCIe standard, and the M-PCIe standard as an example. Alternatively, the present invention may be applied to an interface circuit in conformity with the UFS standard and the PCIe standard, or an interface circuit in conformity with the PCIe standard and the M-PCIe standard. -
FIG. 5 is a block diagram illustrating a configuration of a storage device to which an interface circuit according to a second embodiment is applied. - Referring to
FIG. 5 , astorage device 31 includes amemory element 32 and amemory controller 35. Thememory controller 35 has aninterface circuit 21 and aCPU 33 mounted therein. Ahost 34 is connected to thememory element 32 and theCPU 33 via theinterface circuit 21. Thehost 34 may be a personal computer, a notebook computer, a digital camera, a mobile phone, or a processor that gives instructions to thememory controller 35. Thestorage device 31 may be an external storage device such as an SSD. Thememory element 32 can use an NAND flash memory, and thememory controller 35 can use an NAND controller. - The
interface circuit 21 is formed such thatdecoders interface circuit 1 illustrated inFIG. 1 . Thedecoder 12 can instruct theswitch control unit 9 to switch the destination for connection of thePHY module 10 according to a selection signal SE1. Thedecoder 13 can instruct theswitch control unit 5 to switch the destination for connection of thedata link module 4 according to a selection signal SE2. A reception channel MRCh and a transmission channel MTCh can be provided between thehost 34 and thePHY module 10. A reception channel PRCh and a transmission channel PTCh can be provided between thehost 34 and thePHY module 11. - For example, if the
host 34 is a digital camera, thePHY module 10 is connected to theUniPro module 6 via theswitch control unit 9 to allow theinterface circuit 21 to conform to the UFS standard. In addition, if thehost 34 is a notebook computer, thePHY module 10 is connected to theMAC module 7 via theswitch control unit 9 and theMAC module 7 is connected to thedata link module 4 via theswitch control unit 5 to allow theinterface circuit 21 to conform to the M-PCIe standard. Further, if thehost 34 is a notebook computer, theMAC module 8 is connected to thedata link module 4 via theswitch control unit 5 to allow theinterface circuit 21 to conform to the PCIe standard. This allows thestorage device 31 to realize data communications with thehost 34 in conformity with a different standard without having to replace theinterface circuit 21. - While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
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US201462049173P | 2014-09-11 | 2014-09-11 | |
US14/657,281 US9720866B2 (en) | 2014-09-11 | 2015-03-13 | Interface circuit executing protocol control in compliance with first and second interface standards |
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