CN107391322A - Test equipment based on binary vector - Google Patents
Test equipment based on binary vector Download PDFInfo
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- CN107391322A CN107391322A CN201710342176.9A CN201710342176A CN107391322A CN 107391322 A CN107391322 A CN 107391322A CN 201710342176 A CN201710342176 A CN 201710342176A CN 107391322 A CN107391322 A CN 107391322A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56016—Apparatus features
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2247—Verification or detection of system hardware configuration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2284—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by power-on test, e.g. power-on self test [POST]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
- G06F11/2635—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers using a storage for the test inputs, e.g. test ROM, script files
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56012—Timing aspects, clock generation, synchronisation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C2029/5602—Interface to device under test
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/30—Circuits for homodyne or synchrodyne receivers
- H04B2001/305—Circuits for homodyne or synchrodyne receivers using dc offset compensation techniques
Abstract
A kind of test equipment, including tested device (DUT) and test controller, wherein tested device is configured with serial interface protocol to exchange data, and test controller is configured as receiving corresponding to the binary vector that the binary vector and buffering of the physical layer of serial interface protocol and transmission receive to DUT from external device (ED).
Description
The cross reference of related application
This application claims on May 17th, 2016 the 10-2016-0060361 korean patent applications submitted it is preferential
Power, the entire disclosure of which are incorporated herein by reference.
Background technology
The example embodiment of present inventive concept relates generally to test equipment, more particularly, to can test multiple interfaces
The test equipment of the storage device of agreement.
Test board or test equipment may include to be exclusively used in the semiconductor that semiconductor device manufactures to test after packaging technology
The test controller of device.Semiconductor device can remove from test board or test equipment.When semiconductor device is during test
When on test board, order or data that test controller decodable code provides from external entity (such as ATE), and can be transmitted
The result of decoding is to semiconductor device.Therefore, the interface of the test controller for performing test may depend on semiconductor device
Interface protocol.
Test controller can be exclusively used in the specific protocol for being applied to tested semiconductor device.Therefore, replaceable testing and control
Device is to test and other protocol-dependent semiconductor devices.For example, the replaceable chip for performing test controller function.Work as test
When controller is configured with field programmable gate array (hereinafter referred to as " FPGA "), it is possible to provide the FPGA of new programming is used for it to test
The semiconductor device of his interface protocol.
, it is necessary to which substantial amounts of time and efforts develops various surveys under the test environment of the semiconductor device of production in enormous quantities
Try controller.In addition, come neatly to correspond to required test volume using common interface protocol solution.
The content of the invention
This disclosure relates to a kind of general purpose test equipment, it is assisted independent of the interface of the semiconductor device as test target
View.
It may include that being configured with serial interface protocol hands over according to the test equipment of the example embodiment of present inventive concept
Change the tested device (DUT) of data and be configured as entering from external device (ED) reception corresponding to the two of the physical layer of serial interface protocol
System is vectorial and buffers and send the binary vector of reception to DUT test controller.
It may include to be configured as turning over binary data according to the general purpose test equipment of the example embodiment of present inventive concept
It is translated into the test controller of (translate into) serial transfer signal, is configured as via differential signal line to being controlled from test
Device processed receives the tested device (DUT) of serial transfer signal and is configured to respond to come the direct current offset of self test controller
The DC offset blocks of direct current (DC) skew of control signal adjustment differential signal line pair.Direct current offset block may include at least one passive
Element.
According to the test equipment of the example embodiment of present inventive concept may include to be configured with multi-layer testing agreement with
The test controller of tested device (DUT) communication, and the ATE unit coupled to test controller.Automatic test
Equipment unit is configured as implementing at least one layer in multi-layer testing agreement, and test controller is configured as implementing except by automatic
The remaining layer of the multi-layer testing agreement outside at least one layer in the multi-layer testing agreement that test equipment is implemented.
It should be noted that although do not carry out specific description to it, but the side of the present inventive concept described according to an embodiment
Face can be included in different embodiments.That is the feature of all embodiments and/or any embodiment can with appoint
Where formula and/or combination be combined.These to present inventive concept and other aspects are explained in detail in the following description.
Brief description of the drawings
The foregoing of present inventive concept is more fully described below with reference to the non-limiting example embodiment of present inventive concept
With other features, wherein identical reference marker refers to the same parts through different views.Accompanying drawing is not necessarily to scale
, and it is intended to the diagram principle of Special attention will be given to present inventive concept.In the accompanying drawings：
Fig. 1 is the block diagram according to the test system of the example embodiment of present inventive concept；
Fig. 2 shows to generate the process of binary vector in Fig. 1 ATE；
Fig. 3 is the block diagram of the configuration for the test controller for showing the example embodiment according to present inventive concept；
Fig. 4 shows the process of the buffering and serialization performed in Fig. 3 test controller；
Fig. 5 is the flow chart for showing to generate the method for binary vector according to the example embodiment of present inventive concept；
Fig. 6 is the block diagram according to the tested device of the example embodiment of present inventive concept；
Fig. 7 shows the test system of the example embodiment according to present inventive concept；
Fig. 8 is the block diagram according to the test board of the example embodiment of present inventive concept；
Fig. 9 is the circuit diagram of the example for the DC offset blocks for showing Fig. 8；
Figure 10 is the circuit diagram of another example for the DC offset blocks for showing Fig. 8；
Figure 11 is to show the difference for depending on the supply (provision) that DC is offset according to present inventive concept example embodiment
The time diagram of the signal level variation of sub-signal line；And
Figure 12 is the block diagram according to the test board of the example embodiment of present inventive concept.
Embodiment
Term " binary vector " used herein refers to correspond between test controller and tested device (DUT)
The data of the physical layer of interface protocol.That is binary vector refers to be supplied to tested device (DUT) to perform the one of test
Binary series data.In general, there is provided order or multiple data are to perform test.However, order or data are convertible into
The order of the transaction layer or link layer of interface protocol or data.Hereinafter, the vector changed completely will be referred to as binary system to
Amount.Therefore, if receiving binary vector in tested device (DUT), although it stores in a buffer and led to by driver
Cross serial line interface transmission, the operation of still executable request.
Now by describing present inventive concept for testing test board or the test equipment of semiconductor storage
Example embodiment.It is to be appreciated, however, that it can be not only applicable to survey according to the test equipment of the example embodiment of present inventive concept
Try semiconductor storage and available for the technology for testing a variety of semiconductor devices, such as application processor and ASIC.
Fig. 1 is the block diagram according to the test system of the example embodiment of present inventive concept.As illustrated, test system includes
ATE (ATE) 100 and test board 200.Test board 200 may include test controller 210 and removable tested dress
Put (DUT) 230.Hereinafter, test board 200 will be referred to as test equipment.
ATE 100, which is generated, will be provided to DUT 230 binary vector BV.The generations of ATE 100 connecing corresponding to DUT 230
The binary vector BV of mouth agreement.For example, when the interface protocol used in DUT 230 is UFS standards, ATE 100 generate from
The binary vector of the order decoding of UFS standards.That is the generations of ATE 100, which are sent to DUT 230 and are used as, corresponds to DUT
The binary vector BV of 230 interface protocol order or Data Concurrent give the order or data to test controller 210.Can
The multiple interfaces agreement used, including but not limited to PCIe, UFS and M.2 agreement or communication plan.Retouched below with reference to Fig. 2
State generation binary vector BV process.
Controller 210 stores the binary vector BV generated by ATE 100 in buffer (not shown).Test controller
210 serial signals that can be converted into sending by signal wire by the binary vector BV stored in a buffer according to interface protocol
BV_S and transmittable serial signal BV_S to DUT 230.When the interface protocol between test controller 210 and DUT 230 is string
During row transportation protocol, the binary vector BV of buffering can be converted into serial signal BV_S by test controller 210.Test controller
210 can accelerate the serial signal BV_S of conversion and can send the serial signal BV_S accelerated extremely with high speed serialization transmission mode
DUT 230.That is test controller 210 can be used for conversion from the binary vector BV of the offers of ATE 100 with corresponding to interface
The physical layer transmission signal of agreement.Test controller 210 is used to buffer binary vector BV without individually decoding, and for using
First interface 215 sends buffering binary vector BV.
In addition, test controller 210 can receive the output information OUT exported from DUT 230.Output information OUT can be to ring
Should be in the serial signal BV_S signals exported or data.When output information OUT indicates test result, test controller 210 can
Test result is sent to ATE 100.When whether output information instruction serial signal BV_S is received, test controller 210 can
Resend serial signal BV_S.
DUT 230 receives the serial signal BV_S provided from test controller 210 and performs the serial signal BV_ by receiving
The operation of S instructions.DUT 230 can provide output information OUT to test controller 210 as the behaviour asked by serial signal BV_S
The result of work.DUT 230 may include the second interface 231 for exchanging data with test controller 210.Second interface 231 can
Function with the physical layer defined in MIPI M-PHY standard agreements.Second interface 231, which can be used, has link layer (example
Such as, UniPro) and transaction layer (for example, UFS) interface protocol.DUT 230 can be non-easy with such as HSSI High-Speed Serial Interface
The property lost storage device.
For providing the first interface 215 and second interface 231 of interface between test controller 210 and DUT 230
Physical layer (PHY layer) can be mutually the same.However, ATE 100 can provide the link layer of first interface 215 or the function of transaction layer.
Thus, test controller 210 can be used for sending from the binary vector BV that ATE 100 is provided as connecing corresponding to DUT 230
The physical signalling of the agreement of mouth.
In the exemplary embodiment, the physical layer of first interface 215 and second interface 231 can be defined by " M-PHY " specification.M-
PHY is the interface protocol proposed by mobile Industry Processor Interface (MIPI) alliance.However, present inventive concept is not limited to above reality
Apply mode.As described below, present inventive concept can be used in the interface circuit for including physical layer.Embodiment of above is merely illustrative
To more fully understand present inventive concept.
According to above-mentioned test system, physical layer, link layer etc. can be by ATE depending on the function of DUT 230 interface protocol
100 rather than test controller 210 perform.Therefore, it is possible to provided with improved versatility using serial transfer protocol
DUT 230。
Fig. 2 shows to generate the process of binary vector in Fig. 1 ATE 100.Reference picture 2, the generations of ATE 100 have spy
The order (such as Write (10)) for determining purposes is used as binary vector BV.To hereinafter it be described in greater detail now.
In S10, ATE 100 generates the order Write (10) for being sent to test board 200.ATE 100 can be generated in spy
Determine the multiple orders used in cycle tests.In multiple orders for test, it is possible to provide the Write as scsi command
(10).The operation of ATE 100 and then execution based on interface protocol by command translation to be sent into binary vector.
In S20, Write (10) can be converted into UniPro packets by ATE 100.For example, program can be used in ATE 100
(burst starts the UniPro packets for generating Write (10) to provide corresponding to Write (10), TCO, burst terminates, burst is opened
Beginning, AFC0, AFC1 and burst terminate).Scsi command is converted into the operation of UniPro packets corresponding to UFS interface protocols
Link layer operation.
In S30, ATE 100 can will correspond to the burst of UniPro packets and start (Start of Burst), TCO, prominent
Hair terminates (End of Burst), burst starts (Start of Burst), AFC0, AFC1 and the field terminated that happens suddenly and turned over respectively
It is translated into corresponding binary sequence BC7C, BC07 ..., DC3C, BD7C, BCC3 ..., BCC3 ... and DC3C.UniPro packets to
The conversion of binary code can perform according to the mapping defined in each interface protocol.ATE 100 sends the binary system of conversion
Sequence B C7C, BC07 ..., DC3C, BD7C, BCC3 ..., BCC3 ... and DC3C are to test controller 210 as binary vector BV.
The function of above generating binary vector BV on ATE 100 is described.Binary vector BV life
It can be determined into operating method according to DUT 230 interface protocol.As described above, order is converted into transmission to the two of physical layer
The form of binary signal.This means the change of link layer or transaction layer can be adjusted by changing transfer algorithm in ATE 100
Save (accommodate).Therefore, when only physical layer or when only Signalling method matches, test board 200 can test multiple interfaces
The tested device (DUTs) 230 of agreement.Therefore, universal test device can be achieved.
Although have been described for generate binary vector BV in ATE 100, but the example embodiment of present inventive concept is not
It is limited to this.It is to be understood that can not only be generated by ATE 100 can also be by multiple devices and/or software by binary vector BV
To generate, and it is provided to test controller 210.
Fig. 3 is the block diagram for the configuration for showing the test controller 210 according to the example embodiment of present inventive concept.As its institute
Show, test controller 210 may include buffer 211 and serializer 213.
Buffer 211 stores the binary vector BV provided from ATE 100.For example, buffer 211 can be stored from ATE
100 binary sequence BC7C, BC07 ... received, DC3C, BD7C, BCC3 ..., BCC3 ... and DC3C simultaneously can be corresponding to first
BC7C, BC07 ..., DC3C, BD7C, BCC3 ..., BCC3 ... and DC3C are reset in the output sequence of interface 215.
Serializer 213 serialize be stored in binary sequence BC7C, BC07 ... in buffer 211, DC3C, BD7C,
BCC3 ..., BCC3 ... and DC3C.Although being not shown, acceleration function may be added to that serializer 213 has first to match
The serialization binary vector BV of transfer rate (data rate) defined in interface 215.
Test controller 210 does not possess the transaction layer of interface protocol or the function of link layer such as applied to DUT 230
(see Fig. 1).However, the absorbing external of test controller 210 provide binary vector BV and according to the signal transfer bar of physical layer
Part sends the binary vector BV to DUT 230 of buffering.Therefore, test board 200 may not include the work(of some layers of interface protocol
Energy.Thus, the limitation that test board 200 can relatively free to from being forced by the layer of interface protocol.
Fig. 4 shows the buffering performed in Fig. 3 test controller 210 of the example embodiment according to present inventive concept
With serial process.The signal data unit B C7C for describing to send binary vector BV now with reference to Fig. 4 believes as binary system
Number process.
Binary vector BC7C can be provided to test controller 210 and is used as binary value 1011,1100,0111 and 1100.
Binary value 1011,1100,0111 and 1100 is stored in buffer 211.The binary value being stored in buffer 211
1011st, 1100,0111,1100 by the way that serializer 213 of the 8 bit cell data conversions into order binary sequence is exported as string
Row signal.Serializer 213 can also possess acceleration function to send serial signal at a high speed.
Fig. 5 is the flow chart for showing to generate the method for binary vector according to the example embodiment of present inventive concept.Reference
Fig. 5, ATE 100 provides order to be sent or data to test board 200 as binary vector BV.
In S110, ATE 100 can generate the order or data for test.Order and/or data for test can
Generated by ATE 100 according to test dispatching or received at user.
In S120, ATE 100 can will order or data translation into binary sequence.The operation may correspond to such as UFS
Link layer in interface protocol.
In S130, ATE 100 sends the order for translating into binary sequence or data to test controller 210 and is used as two
System vector BV.Binary vector BV can be received in test controller 210 and just can be transmitted to DUT without coding or processing
230 are used as serial signal.
The operation that ATE 100 is performed by advanced processing in transaction layer or link layer is extremely tested to send order or data
Controller 210.Test controller 210 can not have the function according to interface protocol translator command or data.Thus, it can be achieved to survey
The versatility for being generally limited by the function according to interface protocol translator command or data of test plate (panel).
Fig. 6 is the block diagram according to the tested device (DUT) 230 of the example embodiment of present inventive concept.As shown in it, DUT
230 may include interface 231, storage control 233 and Nonvolatile memory devices 235.
Interface 231 receives the serial signal provided from test controller 210.Binary system can be recovered from the serial signal of reception
Vectorial BV.For example, the recovery of binary vector BV within the physical layer can be carried out in the M-PHY 232 for forming physical layer.
The binary vector BV that binary signal is reverted in interface 231 is convertible into data format corresponding to storage control 233.
Storage control 233 performs the operation asked in ATE 100 by binary vector BV.Storage control 233 can
It is configured to respond to ATE 100 request control Nonvolatile memory devices 235.Storage control 233 is by non-volatile
Storage device 235 interacts with ATE 100.Storage control 233 controls non-volatile memories in response to ATE 100 write request
Device 235 writes data.Storage control 233 controls Nonvolatile memory devices in response to the reading order from ATE 100
235 read operation.
Storage control 233 can drive the software (or firmware) for being referred to alternatively as flash transport layer (hereinafter referred to " FTL ")
To control Nonvolatile memory devices 235.FTL provides interface with the file system of main frame and Nonvolatile memory devices 235
Between hide Nonvolatile memory devices 235 erasing operation.Such as before write-in between erasing and erasing and writing unit
The aspect of unmatched Nonvolatile memory devices 235 can be supplemented by FTL.In addition, FTL is in Nonvolatile memory devices 235
Write operation during the logical address LA generated by file system mapped into Nonvolatile memory devices 235 physically
On the PA of location.
Nonvolatile memory devices 235 perform erasing, reading and write operation according to the control of storage control 233.It is non-
Volatile storage 235 may include multiple memory blocks, and each memory block may include to deposit with the multiple of the matrix arrangement of row and column
Storage unit.Each of memory cell can be arranged as with two-dimensional array structure or three-dimensional (or vertical) array structure.
Nonvolatile memory devices 235 may include multiple memory block BLK1 to BLKi.Memory block BLK1's to BLKi is each
It is individual all to form single erasing unit.Each of memory block BLK1 to BLKi may include to be stacked on perpendicular to Component units string
Multiple memory cell on the direction of substrate.Alternatively, each of memory block BLK1 to BLKi can be parallel to be stacked on
There is provided in the form of multiple unit strings on the direction of substrate.Due to being formed as having the memory block BLK1 of foregoing three-dimensional structure extremely
Caused by BLKi, the capacity of single memory block persistently dramatically increases.Nand flash memory will be described and be used as Nonvolatile memory devices 235
The example of storaging medium.However, other Nonvolatile memory devices can be used as storaging medium.For example, PRAM, MRAM, ReRAM,
FRAM can be used as storaging medium with NOR flash memory and can be applied to wherein be used together the mixing storage of different types of storage device
System.
Example of the storage device including Nonvolatile memory devices as tested device (DUT) 230 is described.So
And, it is to be understood that DUT 230 can not be only storage device, and can be the various interface protocols of application, on-chip system or storage
The application processor (AP) of one of card.
Fig. 7 shows the test system 200 according to the example embodiment of present inventive concept.Reference picture 7, test system 200
Binary vector BV can be received to perform test operation in tested device (DUT) 230.
In S210, ATE 100 transmits binary vector BV to test controller 210.Binary vector BV is according to test
Interface protocol between controller 210 and DUT 230 determines.Binary vector BV can be generated in ATE 100 and is not limited to DUT
230 interface protocol type.
In S220, test controller 210 stores the binary vector BV transmitted from ATE 100.For example, test controller
210 store binary vector BV in buffer 211.
In S230, the binary vector BV that test controller 210 is directed at output order to store in buffer 211 turns
Change serial signal into.Alignment methods above are described with regard to Fig. 4.What test controller 210 made to store in buffer 211 two enters
Make serial transmission of the vectorial BV acceleration for binary vector BV.
In S240, the transmission of test controller 210 is converted into the binary vector HS_Signal of high-speed serial signals extremely
DUT 230。
In S250, DUT 230 checks whether the binary vector HS_Signal that have received and sent as serial signal.
Binary vector HS_Signal as serial signal is converted into binary data by DUT 230.DUT 230 is being converted into two
Error checking operation is performed on the binary vector BV of binary form.
In S260, when not determining binary vector BV by error free reception by error checking operation, DUT 230 can be sent out
Send and receive error message N_ACK to test controller 210.Then, test controller 210 can be resend sends out as serial signal
The binary vector HS_Signal sent.
In S270, when determining binary vector BV by error free reception by error checking operation, DUT 230 sends and connect
End signal ACK is received to test controller 210.
In S280, test controller 210 can transmit binary vector BV transmission result or test result TST_O extremely
ATE 100。
Binary vector BV is described above to transmit to DUT 230 process.According to test controller 210 and DUT
Interface protocol between 230 generates binary vector BV in ATE 100.Thus, test controller 210 can be transmitted from ATE
The 100 binary vector BV to DUT 230 provided.Due to said structure, test controller 210 need not perform DUT's 230
The transaction layer or link layer functionality of interface protocol.Because the operating function of interface protocol can be realized in ATE 100.Cause
And test board 200 can provide the versatility for being substantially independent of the interface protocol type that DUT 230 is used.
Fig. 8 is the block diagram according to the test board 300 of the example embodiment of present inventive concept.As illustrated, test board 300 wraps
Include test controller 310, tested device (DUT) 330 and direct current offset block 350.Because DUT 330 generally with described in Fig. 1
It is identical, DUT 330 detailed functions will not described below.
Test controller 310 can store from external reception binary vector BV and in a buffer the binary vector of reception
BV.The binary vector BV stored in buffer can be converted into serial signal and accelerate and send string by test controller 310
Row signal is to DUT 330.Test controller 310 may include the first transmitter circuit (TX1) that DUT 330 is sent to for signal
311 and for signal receive first acceptor circuit (RX1) 313.First transmitter circuit 311 and first acceptor circuit
313 may make up single channel.First transmitter circuit 311 sends differential signal to differential signal line TX+ and TX-.First receiver
Circuit 313 receives differential signal by differential signal line RX+ and RX-.Surveyed when sending data by the first transmitter circuit 311
Examination controller 310 can provide DC offset control signals DCOS to DC offset blocks 350.DC offset control signals DCOS can be according to DUT
330 operator scheme or DUT 330 interface protocol adjustment.
DUT 330 receives binary vector BV using the second acceptor circuit (RX2) 331 from test controller 310.DUT
330 change according to interface protocol and handle the binary vector BV of reception.DUT 330 passes through the second transmitter circuit (TX2) 333
Transmission process result or the data of request are to test controller 310.Second acceptor circuit 331 can pass through differential signal line TX+
The first transmitter circuit 311 is connected to TX-.Second transmitter circuit 333 can be connected to by differential signal line RX+ and RX-
First acceptor circuit 313.
DC offset blocks 350 receive the direct current offset control signal provided from test controller 310.Direct current offset block 350 is controlled
The direct current offset of differential signal line TX+ and TX- between test controller 310 and DUT 330 processed.Direct current offset block 350 can base
Change differential signal line TX+ and TX- direct current offset in DC offset control signals DCOS.Direct current offset block 350 can be used passive
Element is realized to provide direct current offset.
For example, DC offset blocks 350 can adjust DC skews according to operator scheme.When the first transmitter circuit 311 is in dormancy
During state, DC offset blocks 350 can provide DC skews as 0 volt of voltage.When the first transmitter circuit 311 is changed from resting state
For for sending the wake-up states of data or during in bursty state for sending data, it is inclined that DC offset blocks 350 increase direct current
Move to predetermined level.
In addition, DC offset blocks 350 can adjust DC skews according to interface protocol.For using serial line interface with it is polytype
The direct current offset block 350 that DUT 330 is interacted can adjust differential signal line TX+ and TX- serial skew to plurality of level.
Fig. 9 is the circuit diagram for the example for showing the DC offset blocks 350 in Fig. 8.Reference picture 9, there is provided offset and control corresponding to DC
The inductor L of signal DCOS processed DC skews may be connected to each of differential signal line TX+ and TX-.
Differential signal line between first transmitter circuit 311 and the second acceptor circuit 331 passes through coupled capacitor device C1
Differential signal line TX+ and TX- are connected to C2.Each of node N1 and N2 have according to the one end for being supplied to inductor L
DC offset control signals DCOS level direct current offset.DC offset control signals DCOS level offsets for DC.
Figure 10 is the circuit diagram for another example for showing the direct current offset block 350 in Fig. 8.Reference picture 10, separated resistance
Device R1 and R2 can be respectively connecting to differential signal line TX+ and TX-, to divide DC offset control signals DCOS and provide what is be divided
DC offset control signals DCOS is offset as DC.
Differential signal line between first transmitter circuit 311 and the second acceptor circuit 331 passes through coupled capacitor device C1
Each of differential signal line TX+ and TX- are connected to C2.Separated resistor R1 and R2 can be respectively connecting to node N1 and
N2.The DC offset control signals DCOS voltage being divided is provided to each work in first node N1 and section point N2
For direct current offset.
Using passive element provide DC offset to differential signal line TX+ and TX- DC offset blocks 350 example embodiment
It is described.The DC offset blocks 350 of above structure can be implemented on the substrate comprising test board 300.
Figure 11 is the letter for the differential signal line for showing the offer offset based on DC according to present inventive concept example embodiment
The timing diagram of number level change.Reference picture 11, send to differential signal line TX+ and TX- signal DC skew can be based on DC it is inclined
Move control signal DCOS and change.
For example, it can be sent in time point T0, serial signal D1, D2, D3 and D4 by differential signal line TX+ and TX-.This point
It it will be assumed as DC offset control signals DCOS to be provided as to the time point at 0 volt of voltage.
Enabled in time point T1, DC offset control signals DCOS by test controller 310.In the case, difference is believed
Number line TX+ and TX- DC skews are provided by inductor L or separated resistor R1 and R2.Thus, serial signal D5, D6, D7
The level corresponding to DC skews can be changed to D8.
It is to be understood that DC offset control signals DCOS may be provided as with according to the more of interface protocol or operator scheme
Kind value.
Figure 12 is the block diagram according to the test board 400 of the example embodiment of present inventive concept.As shown in it, test board 400
Including test controller 410, the DC offset blocks 450 of tested device (DUT) the 430, the first and the 2nd DC offset blocks 470.Because DUT
430 substantially with that relative to identical described by Fig. 8, will omit DUT 430 detailed description below.
Test controller 410 can store from external reception binary vector BV and in a buffer the binary vector of reception
BV.The binary vector BV stored in a buffer can be converted into serial signal and accelerate and send by test controller 410
Serial signal is to DUT 430.Test controller 410 sends serial signal to DUT 430 using differential signal line TX+ and TX-.Survey
Try controller 410 and differential signal is received from DUT 430 by differential signal line RX+ and RX-.
When sending data by differential signal line TX+ and TX-, the first DC skew controls can be used in test controller 410
Signal DCOS1 control differential signal lines TX+ and TX- direct current offset.Test controller 410 can offset control letter via the first DC
Number DCOS1 controls the first DC offset blocks 450.
In addition, when receiving data by differential signal line RX+ and RX-, the 2nd DC can be used to offset for test controller 410
Control signal DCOS2 control differential signal lines RX+ and RX- DC skews.Test controller 410 can offset via the 2nd DC and control
Signal DCOS2 controls the 2nd DC offset blocks 470.
According to the above-mentioned embodiment of present inventive concept, test controller 410 can receive binary vector BV and send and connect
The binary vector BV to DUT 430 of receipts.In addition, test controller 410 can independent control be used for transmit differential signal and reception
The direct current offset of differential signal.
When using above-mentioned test board 400, the design of test controller 410 need not be according to DUT 430 interface protocol
Change.High universalizable thus can be provided.
As described above, the test equipment for the semiconductor device that can test multiple interfaces agreement can be realized.
Above-disclosed theme is considered as illustrative and not restrictive, and appended claims are intended to belong to this
The true spirit of the inventive concept and all modifications of scope, enhancing and other features.Thus, allowed at utmost in law
On, the scope of present inventive concept most can allow to explain to determine extensively by appended claims and its equivalent, without should
It is limited to foregoing detailed description.Although some example embodiments are specifically illustrated and have described, those of ordinary skill in the art's meeting
Understand, can carry out being modified without departing from spirit and scope by the claims in form and details.
Claims (25)
1. a kind of test equipment, including：
Tested device (DUT), it is configured with serial interface protocol and exchanges data；And
Test controller, it is configured as receiving the binary vector of the physical layer corresponding to serial interface protocol from external device (ED),
And the binary vector received is buffered and sent to the tested device (DUT).
2. test equipment according to claim 1, wherein the test controller includes：
Buffer, it is configured as storing the binary vector；And
Serializer, it is configured as the binary vector of storage being converted into the serial letter corresponding to the serial interface protocol
Number.
3. test equipment according to claim 2, wherein the serializer is additionally configured to turn the binary vector
It is changed to the differential signal corresponding to the serial interface protocol, and acceleration and output data.
4. test equipment according to claim 1, wherein the binary vector is via the serial interface protocol
The sequence of binary signals that differential signal in physical layer receives.
5. test equipment according to claim 1, wherein the test controller does not have the serial interface protocol
The function of transaction layer and link layer.
6. test equipment according to claim 5, wherein the test controller includes field programmable gate array
(FPGA)。
7. test equipment according to claim 1, wherein the serial interface protocol includes PCIe, UFS and M.2 communication party
At least one of case.
8. test equipment according to claim 1, wherein the physical layer of the serial interface protocol corresponds to MIPI
M-PHY specifications.
9. test equipment according to claim 1, wherein the external device (ED) is to be configured as the order by for test
Or data translation is into the ATE (ATE) of the binary vector.
10. test equipment according to claim 1, wherein the test controller also includes DC offset blocks, the DC is inclined
Block is moved to be configured as by least one differential signal line to sending the binary vector to the tested device (DUT) and adjusting
The DC skews of the whole differential signal line centering.
11. test equipment according to claim 10, wherein the DC offset blocks include at least one passive element, it is described
The DC offset control signals that at least one passive element is configured to respond to provide from the test controller apply the DC
It is offset to the differential signal line.
12. a kind of general purpose test equipment, including：
Test controller, it is configured as the binary data of reception translating into serial transfer signal；
Tested device (DUT), it is configured as via differential signal line to serially transferring letter from described in test controller reception
Number；And
DC offset blocks, it is configured to respond to the DC offset control signals from the test controller and adjusts the differential signal
The DC skews of line pair.
Wherein described DC offset blocks include at least one passive element.
13. general purpose test equipment according to claim 12, wherein the test controller is additionally configured to based on described
The type of the interface protocol of tested device (DUT) generates the DC offset control signals.
14. general purpose test equipment according to claim 12, wherein the test controller is additionally configured to based on described
The operator scheme of tested device (DUT) determines the level of the DC offset control signals.
15. general purpose test equipment according to claim 12, wherein the DC offset blocks include inductor, the inductor
It is configured as receiving the DC offset control signals and provides the DC offset control signals as the differential signal line centering
The DC skews of at least one line.
16. general purpose test equipment according to claim 12, wherein the DC offset blocks include multiple separated resistors,
The resistor is configured as dividing the direct current offset control signal and provides the DC offset control signals being divided as institute
State the direct current offset of at least one line of differential signal line centering.
17. general purpose test equipment according to claim 12, wherein the binary data received is to be mapped to the quilt
Survey the data of the physical layer of the interface protocol of device (DUT).
18. general purpose test equipment according to claim 17, wherein the tested device (DUT) can be set from the test
It is standby to remove.
19. general purpose test equipment according to claim 12, wherein the test controller includes field-programmable gate array
Arrange (FPGA).
20. general purpose test equipment according to claim 12, wherein the test controller and the tested device (DUT)
Each it is additionally configured to send serial transfer signal, at least one serial line interface association according at least one serial interface protocol
View includes PCIe, UFS and M.2 at least one of communication plan.
21. a kind of test equipment, including：
Test controller, it is configured with multi-layer testing agreement and is communicated with tested device (DUT)；And
ATE unit, it is coupled to the test controller；
Wherein described ATE unit is configured as implementing at least one layer of the multi-layer testing agreement, the test control
Device processed is configured as implementing the multilayer outside at least one layer by the multi-layer testing agreement of ATE implementation
The rest layers of test protocol.
22. test equipment according to claim 21, wherein the ATE unit is additionally configured to for institute
The command translation of tested device is stated into binary vector；And
Wherein described test controller includes：
Buffer, it is configured as the binary vector that storage receives from the ATE unit；And
Serializer, it is configured as being converted into corresponding to by the binary vector being used for what is communicated with the tested device (DUT)
The serial signal of serial interface protocol.
23. test equipment according to claim 22, wherein the serializer is configured as accelerating the data of serial signal
Speed is to match the transfer rate between the test controller and the tested device (DUT).
24. test equipment according to claim 22, wherein the binary vector corresponds to the multi-layer testing agreement
Physical layer.
25. test equipment according to claim 21, wherein at least one layer of the multi-layer testing agreement is including described more
At least one of the link layer of layer test protocol and the transaction layer of the multi-layer testing agreement.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2016-0060361 | 2016-05-17 | ||
| KR1020160060361A KR20170130013A (en) | 2016-05-17 | 2016-05-17 | Test apparatus based on binary vector |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107391322A true CN107391322A (en) | 2017-11-24 |
| CN107391322B CN107391322B (en) | 2021-11-23 |
Family
ID=60330365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710342176.9A Active CN107391322B (en) | 2016-05-17 | 2017-05-16 | Test equipment based on binary vector |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US10163525B2 (en) |
| KR (1) | KR20170130013A (en) |
| CN (1) | CN107391322B (en) |
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| CN111431596A (en) * | 2020-03-24 | 2020-07-17 | 中星联华科技（北京）有限公司 | Signal speed-up method and circuit |
| CN114336197A (en) * | 2022-01-20 | 2022-04-12 | 深圳宏芯宇电子股份有限公司 | Interface conversion device, test board and card reader |
| WO2022266959A1 (en) * | 2021-06-24 | 2022-12-29 | 华为技术有限公司 | Chip test circuit and method |
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| US10936046B2 (en) * | 2018-06-11 | 2021-03-02 | Silicon Motion, Inc. | Method for performing power saving control in a memory device, associated memory device and memory controller thereof, and associated electronic device |
| US10877088B2 (en) * | 2019-01-30 | 2020-12-29 | Qualcomm Incorporated | In-system structural testing of a system-on-chip (SoC) using a peripheral interface port |
| WO2021126182A1 (en) * | 2019-12-18 | 2021-06-24 | Mentor Graphics Corporation | Transmission rate adaptation |
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Also Published As
| Publication number | Publication date |
|---|---|
| US20170337988A1 (en) | 2017-11-23 |
| US10163525B2 (en) | 2018-12-25 |
| KR20170130013A (en) | 2017-11-28 |
| CN107391322B (en) | 2021-11-23 |
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