WO2022266959A1

WO2022266959A1 - Chip test circuit and method

Info

Publication number: WO2022266959A1
Application number: PCT/CN2021/102190
Authority: WO
Inventors: 付海涛; 黄俊林; 邓斌; 崔昌明
Original assignee: 华为技术有限公司
Priority date: 2021-06-24
Filing date: 2021-06-24
Publication date: 2022-12-29
Also published as: CN117120856A

Abstract

A chip test circuit and method, which relate to the technical field of chips, and by means of which high-rate test data of a test machine can be received and converted into multi-channel input data by using a high-speed serial test interface, thereby eliminating the limitations on a test data transmission bandwidth of a single channel, and improving the chip test efficiency. The chip test circuit comprises: a high-speed serial test interface, which is used for receiving high-speed serial input data sent by a test machine, converting the high-speed serial input data into multi-channel input data, and sending the multi-channel input data to a first speed changer; the first speed changer, which is used for normalizing the multi-channel input data into single-channel input data so as to test a circuit to be tested; and a second speed changer, which is used for receiving single-channel output data from the circuit to be tested, converting the single-channel output data into multi-channel output data, and outputting the multi-channel output data to the high-speed serial test interface, wherein the high-speed serial test interface is further used for converting the multi-channel output data into high-speed serial output data, and sending same to the test machine.

Description

A chip testing circuit and method

technical field

The present application relates to the field of chip technology, in particular to a chip testing circuit and method.

Background technique

Based on the large-scale production of chips, the logic test of chips requires a large number of multiplexed digital input/output (input/output, I/O) resources to generate test vectors (Test Vector) required for chip testing. With the development of Moore's Law, the growth trend of logic modules in logic mode is very out of sync with the growth of chip I/O resources. Limitation, the parallel test rate of the logic module is reduced, which will lead to the serialization of the Scan test, and when the same I/O resource is allocated to more logic modules, it will lead to the compression ratio of the I/O resource and the Scan chain (chain) Rising, making the Scan test efficiency decrease.

In order to improve the test efficiency of Scan, how to obtain the reusable I/O resources of Scan has become the current bottleneck problem. In the past, SerDes I/O resources were directly multiplexed as low-speed (25-100Mhz) digital I/O resources during the Scan test, and multiplexing low-speed digital I/O resources can improve the transmission of test data The bandwidth is very limited, and it cannot continue to obtain a larger Scan test data transmission bandwidth, which cannot meet the actual mass production requirements of the chip, and the Scan test efficiency is low. The current international standard test protocol describes how to use the serial-to-parallel conversion function of the serializer and deserializer (SerDes) to realize the high-speed transmission of Scan data. The limitation of I/O transmission bandwidth. Scan I/O is a typical form, and the test loading of the chip also needs to take into account other large-bandwidth test data streams.

Contents of the invention

The embodiment of the present application provides a chip test circuit and method, based on the use of serial and deserializers to provide large-bandwidth test data streams or test buses, without restricting the subsequent test purposes of the bus, and being able to use high-speed serial test interfaces to receive The high-speed test data of the test machine is converted into multi-channel input data, which liberates the test data transmission bandwidth limitation of a single channel and improves the chip test efficiency.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

In the first aspect, a chip test circuit is provided, the chip test circuit includes a high-speed serial test interface, a first transmission and a second transmission, the high-speed serial test interface and the test machine are interconnected based on capacitive coupling, and adopt differential transmission The high-speed serial test interface is used to receive the high-speed serial input data sent by the test machine, convert the high-speed serial input data into multi-channel input data, and send the multi-channel input data to the first transmission Data; the rate of high-speed serial input data is greater than or equal to 1.25Gbps; the first transmission is used to normalize the multi-channel input data into single-channel input data, and the single-channel input data is used to test the circuit to be tested, and the circuit to be tested and The chip test circuit is coupled; the second transmission is used to receive single-channel output data from the circuit to be tested, convert the single-channel output data into multi-channel output data, and send the multi-channel output data to the high-speed serial test interface; wherein, the single-channel The output data corresponds to the single-channel input data; the high-speed serial test interface is also used to convert the multi-channel output data into high-speed serial output data, and send the high-speed serial output data to the test machine.

In this way, when the high-speed serial test interface receives high-speed serial data and converts it into multi-channel input data, the transmission of high-speed serial input data and converted multi-channel input data can greatly increase the transmission rate of test data. Secondly, when the application utilizes the high-speed serial test interface to receive high-speed serial input data and output multi-channel input data, even if the logic resources to be tested in the chip continue to increase, the I/O resources for test data transmission only take up There are fewer I/O pins on the chip (pins for high-speed serial input data, pins for high-speed serial output data, pins for multi-channel input data and pins for multi-channel output data). Moreover, through an uplink and downlink transmission (Gearbox, the bit width and frequency of its input and output terminals will change) can realize the normalized integration of multi-channel input data bit width, which can increase the routing frequency of the test bus (Bus).

In a possible design, the multi-channel input data is transmitted on M channels, and M is an integer greater than 1; the first transmission is used to receive the multi-channel input data in the 1-fold frequency clock domain, and the multi-channel input data Perform bit width conversion to obtain single-channel input data; output single-channel input data in the M-multiplied clock domain; the second transmission is used to receive single-channel output data in the M-multiplied clock domain, and bit-bit the single-channel output data Wide conversion to obtain multi-channel output data; output multi-channel output data under 1 multiplied clock; wherein, the bit width occupied by single-channel input data and the bit width occupied by single-channel output data are fixed.

For example, multi-channel input data is transmitted on 4 channels, the input terminal of the first transmission receives 4-channel input data in the 1-multiplied clock domain, and the output terminal of the first transmission outputs a single channel in the 4-multiplied clock domain Input data. In this way, by integrating and normalizing the bit width of multi-channel input data, and inputting data at a 4-fold frequency, the routing frequency of test data on the test bus can be increased. Similarly, when the second transmission receives the single-channel output data at a frequency multiplied by 4, the rate at which the single-channel output data is fed back to the test machine is also increased, thereby improving the chip testing efficiency as a whole.

In a possible design, the first transmission includes a first buffer and a first bit width conversion circuit; the first buffer is used for buffering the multi-channel input received from the high-speed serial test interface under the 1-fold frequency clock domain Data; the first bit width conversion circuit is used to read the multi-channel input data from the first buffer according to the channel bit width of the output single-channel input data, obtain the single-channel input data, and output the single-channel in the M multiplied clock domain Input data; the second speed changer includes a second buffer and a second bit width conversion circuit; the second buffer is used to buffer the single-channel output data received under the M multiplied clock domain; the second bit width conversion circuit uses The method is to read the single-channel output data from the second buffer according to the bit width of each channel for outputting the multi-channel output data, obtain the multi-channel output data, and output the multi-channel output data in the 1-fold frequency clock domain.

In this way, the first transmission can buffer the multi-channel input data and then perform bit width integration and normalization by the bit width conversion component, and input the normalized single-channel input data in the M multiplier clock domain, which can improve the test data Trace frequency on the test bus. Similarly, when the second transmission receives the single-channel output data at an M-multiplied frequency, the rate at which the single-channel output data is fed back to the testing machine is also increased, thereby improving chip testing efficiency as a whole.

In a possible design, the test circuit also includes a decoder, an encoder, a finite state machine FSM, a first flow pipeline and a second flow pipeline; both the first flow pipeline and the second flow pipeline include a multi-level storage unit; the first transmission The output end of the decoder is coupled to the input end of the decoder, and the output end of the decoder is coupled to the input end of the first stream pipeline; the output end of the first stream pipeline is coupled to the test bus of the test circuit; the input end of the second transmission is coupled to the output of the encoder The input end of the encoder is coupled to the output end of the second flow pipeline, and the input end of the second flow pipeline is coupled to the test bus; the FSM is coupled to the decoder, the encoder, the first flow pipeline and the second flow pipeline.

In a possible design, the decoder is used to perform decoding operations on single-channel input data, send the decoded test data to the first-stream pipeline, and send the decoded instructions to the FSM; the FSM is used to Determining the operating state of the encoder, the first stream pipe, and the second stream pipe; the first stream pipe for transmitting test data to the test bus according to the operating state of the first stream pipe determined by the FSM; the second stream pipe for determining according to the FSM The operating state of the second stream pipeline receives the test result returned through the test bus, and sends the test result to the encoder; the encoder is used to encode the test result according to the operating state of the encoder determined by the FSM, to obtain single-channel output data , and send single-channel output data to the second transmission.

In the existing chip test, the test data input to the chip does not go through the decoding and encoding process. This application can decode the received input data through the decoder to obtain the test data, and output the test data to the Test the bus. Feedback test results can also be output to the encoder for encoding after hierarchical buffering in the second stream pipeline to obtain single-channel output data. Wherein, the FSM can determine the operating states of the encoder, the first stream pipeline and the second stream pipeline according to the decoded instruction. In this way, the present application provides a standardized chip test framework, which is applicable to the transmission of test data at various rates.

Exemplarily, the test circuit further includes a gating circuit coupled to each level of storage units in the multi-level storage unit; the first stream pipeline includes a first level storage unit and a second level storage unit; the first level storage unit is used for caching The test data received from the decoder; the first-level storage unit is also used to send the first-level storage unit to the second-level storage unit when receiving the clock signal sent by the gating circuit coupled with the first-level storage unit The test data stored in the storage unit; the second-level storage unit is used to cache the test data received from the first-level storage unit. Therefore, the first stream pipeline and the second stream pipeline provided by the present application provide hierarchical cache output for input data, which can avoid the problem of increased chip overhead caused by using FIFO for data cache in the prior art.

In a possible design, the test circuit also includes a plurality of frame header aligners and channel aligners; the input end of each frame header aligner is coupled with an output port of the high-speed serial test interface, and each frame header aligner The output terminal of the channel aligner is coupled with an input terminal of the channel alignment circuit, and a plurality of output terminals of the channel aligner are coupled with a plurality of input ports of the first transmission; each frame header aligner is used for outputting from an output of the high-speed serial test interface The port receives one channel input data in the multi-channel input data, and performs frame header alignment on the input data of one channel and outputs it to the channel aligner; the channel aligner is used to align the data received from multiple frame header aligners The multi-channel input data is output to the first transmission after data alignment between channels is performed.

This is because when the multi-channel input data output by the high-speed serial test interface is input to the first transmission, the input data packets may be out of sequence, therefore, the frame header aligner can receive the multi-channel input data from the high-speed serial test interface The data is frame header aligned, so that the input data of each channel in the multi-channel input data is sent to the channel aligner in the sequence after the frame header is aligned.

The data alignment between channels by the channel aligner can be understood as, due to the possible inconsistency in the transmission speed of each channel, when a data packet is divided into multiple parts and transmitted on multiple channels, each part of data is transmitted on a different channel may not reach the first transmission at the same time, therefore, the channel aligner can transmit the small data packets of the same data packet to the first transmission at the same time when transmitted on different channels.

Exemplarily, each frame header aligner includes a third buffer and a frame header alignment circuit; the third buffer is used for buffering one channel in the multi-channel input data received from an output port of the high-speed serial test interface Input data; frame header alignment circuit, used to read a channel input data from the third buffer, and sort the input data of a channel according to the frame header and then output to the channel alignment circuit;

The channel aligner includes a fourth buffer and a channel alignment circuit; the fourth buffer is used to buffer multiple channel input data sent from multiple channel alignment circuits; the channel alignment circuit is used to read multiple channels from the fourth buffer. The channel input data is aligned between multiple channels and then output to the first transmission.

In a possible design, the test circuit may further include a descrambler, a scrambler, a demultiplexer and a combiner. Among them, the descrambler is used to descramble the single-channel output data output by the first transmission; the scrambler is used to scramble the single-channel output data output by the encoder and then send it to the second transmission; the demultiplexer is used for The single-channel input data received from the first-stream pipeline is transmitted to the combinational logic circuit of the specified output; the combiner is used to feed back the test results transmitted from the test bus ports with different bit widths to the first through the combiner Secondary pipeline.

In this way, the transmission of data in the chip test circuit is realized through the scrambler and descrambler. As long as the number of stages of the scrambler is selected properly, the code stream after scrambling can be fully random, thereby improving the signal transmission outside the chip. Transmission quality in the transmission channel, etc.

The demultiplexer can be understood as transmitting single-channel input data to a 32-bit wide test bus port for output to the circuit to be tested, or to a 64-bit wide test bus port for output to the circuit to be tested, or to a 128-bit wide The test bus port output to the circuit to be tested and so on. The implementation of the demultiplexer and then the combiner can satisfy the test data transmission in the test bus with various bit widths, so as to realize the test of the circuit to be tested.

In the second aspect, a method for testing a chip is provided, the chip includes a high-speed serial test interface, the high-speed serial test interface and the test machine are interconnected based on capacitive coupling, and the data transmitted by the test machine is received by a differential transmission method. The method includes: the chip receives the high-speed serial input data sent by the testing machine through the high-speed serial test interface, and converts the high-speed serial input data into multi-channel input data; the rate of the high-speed serial input data is greater than or equal to 1.25Gbps; The multi-channel input data is normalized into single-channel input data, and the single-channel input data is used to test the circuit to be tested in the chip; the chip converts the single-channel output data received from the circuit to be tested into multi-channel output data, and the single-channel The output data corresponds to the single-channel input data; the chip converts the multi-channel output data into high-speed serial output data through the high-speed serial test interface, and sends the high-speed serial output data to the test machine.

For the beneficial effects of the second aspect, reference may be made to the description of the first aspect, which will not be repeated here.

In a possible design, the multi-channel input data is transmitted on M channels, and M is an integer greater than 1; the chip normalizes the multi-channel input data into a single-channel input data including: the chip pair is in the 1-fold frequency clock domain The transmitted multi-channel input data is subjected to bit width conversion to obtain the single-channel input data transmitted under the M multiplied clock domain; the chip converts the single-channel output data received from the circuit to be tested into multi-channel output data, including: the chip pair in M The single-channel output data received in the multiplied clock domain is subjected to bit width conversion to obtain the multi-channel output data transmitted under the 1-multiplied clock; among them, the bit width occupied by the single-channel input data and the bit width occupied by the single-channel output data fixed.

Exemplarily, the chip normalizes the multi-channel input data into single-channel input data including: the chip buffers the multi-channel input data received from the high-speed serial test interface in the 1-fold frequency clock domain; the chip outputs the single-channel input data according to the channel The bit width reads the multi-channel input data from the first buffer to obtain the single-channel input data, and outputs the single-channel input data in the M multiplied clock domain;

The chip converts the single-channel output data received from the circuit to be tested into multi-channel output data, including: the chip buffers the single-channel output data received under the M-multiplied clock domain; the chip outputs the multi-channel output data according to each channel The bit width reads single-channel output data from the second buffer to obtain multi-channel output data, and outputs the multi-channel output data in a 1-fold frequency clock domain.

In a possible design, before the chip converts the single-channel output data received from the circuit to be tested into multi-channel output data, the method further includes: the chip decodes the single-channel input data to obtain decoded instructions and test data; the chip outputs the test data to the test bus in the chip after being cached by the multi-level storage unit, and transmits the test data to the circuit to be tested through the test bus; the chip performs the test returned from the circuit to be tested according to the decoded instructions The results are cached by the multi-level storage unit, and the cached output test results are encoded to obtain single-channel output data.

Exemplarily, the multi-level storage unit includes a first-level storage unit and a second-level storage unit; after the chip caches the test data through the multi-level storage unit and then outputs it to the test bus in the chip, it includes: controlling the first-level storage unit cache from The test data received by the decoder; control the first-level storage unit to send the test data stored in the first-level storage unit to the second-level storage unit when receiving the clock signal sent by the gate control circuit coupled with the first-level storage unit Data; control the test data received by the second-level storage single cache from the first-level storage unit.

In a possible design, before the chip normalizes the multi-channel input data into single-channel input data, the method further includes: the chip performs data frame header alignment on the input data of each channel in the multi-channel input data; Perform inter-channel data alignment on the multi-channel input data after frame header alignment.

Exemplarily, the frame header alignment performed by the chip on the input data of each channel in the multi-channel input data includes: the chip controls the third buffer to cache the multi-channel input data received from an output port of the high-speed serial test interface One channel input data; the chip controls the frame header alignment circuit to read one channel input data from the third buffer, and sorts one channel input data according to the frame header and outputs it to the channel alignment circuit;

The chip performs inter-channel data alignment on the multi-channel input data after frame header alignment includes: the chip controls the fourth buffer to cache multiple channel input data sent from multiple channel alignment circuits; the chip controls the channel alignment circuit to read from the fourth buffer The input data of multiple channels is taken, and the input data of multiple channels is aligned between channels, and then output to the first transmission.

In a third aspect, a communication device is provided, including at least one processor, at least one processor is coupled to a memory, and at least one processor is used to read and execute a program stored in the memory, so that the communication device performs the above-mentioned second aspect and Any one possible design of the method of the second aspect.

In a fourth aspect, there is provided a computer-readable storage medium, including computer instructions. When the computer instructions are run on the electronic device, the electronic device is made to execute the method described in the above-mentioned second aspect and any possible design of the second aspect. .

Description of drawings

FIG. 1 is a schematic diagram of a logic scale of a chip provided by an embodiment of the present application and a trend diagram of the I/O bandwidth available for Scan multiplexing;

FIG. 2 is a schematic diagram of a chip test design architecture provided by an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a chip test circuit provided in an embodiment of the present application;

FIG. 4 is a schematic structural diagram of a chip test circuit provided in an embodiment of the present application;

FIG. 5 is a schematic flow chart of a method for testing a chip provided in an embodiment of the present application;

6 is a schematic structural diagram of a chip test circuit when the multi-channel is four 32-bit wide channels provided by the embodiment of the present application;

Fig. 7 is a schematic structural diagram of a first transmission and a second transmission provided by the embodiment of the present application;

FIG. 8 is a schematic diagram of an implementation of a 1-multiplied clock domain and an M-multiplied clock domain provided in an embodiment of the present application;

9 is a schematic diagram of using a PLL to generate a 1-fold frequency clock domain and a 4-fold frequency clock domain in a chip test circuit provided by an embodiment of the present application;

FIG. 10 is a schematic diagram of a state of an FSM provided by an embodiment of the present application;

Fig. 11 is a schematic diagram of inputting test data to the first flow pipeline provided by the embodiment of the present application;

FIG. 12 is a schematic structural diagram of a chip test circuit provided by an embodiment of the present application;

FIG. 13 is a schematic structural diagram of a frame header alignment circuit and a channel alignment circuit provided by an embodiment of the present application;

FIG. 14 is a schematic structural diagram of a chip provided by an embodiment of the present application.

detailed description

For ease of understanding, some descriptions of concepts related to the embodiments of the present application are given by way of example for reference. As follows:

Design for testability (DFT): An integrated circuit design technique that can implant some special structures into the circuit during the design stage so that the circuit can be tested after the design is completed.

Scan test: one of the important methods of digital integrated circuit testing, which can effectively screen out bad chips and improve product quality.

SerDes: including high-speed serial-to-parallel conversion circuits, clock data recovery circuits, data codec circuits, clock correction and channel bonding circuits, etc., providing a physical layer basis for various high-speed serial data transmission protocols. The TX transmitter and RX receiver of SerDes have independent functions, and both are composed of two sublayers: physical media attachment (PMA) and physical coding sublayer (PCS).

Automated tester (Automotive Tester Equipment, ATE): In the semiconductor industry, it means integrated circuit (integrated circuit, IC) automatic tester, which is used to detect the integrity of integrated circuit functions, and is the final process of integrated circuit manufacturing to ensure The quality of integrated circuit manufacturing.

High Speed Serial Test Interface (HSSTI): It can be understood as a high-speed serial test tool, which is used to load test data inside the chip.

Finite state machine (FSM): It is composed of state registers and combinational logic circuits. It can perform state transitions according to the preset state according to the control signal. It is the control center for coordinating related signal actions and completing specific operations.

CMD: Windows command prompt, which is a shell program used to run the Windows control panel program or a certain DOS program under Windows NT; or a shell program used to run the control panel program under Windows CE.

end of packet (EOP): An instruction for the last packet in a data stream.

As the number of test modules of the chip increases, the same I/O resource can be allocated to more logic resources. That is, although the number of logic modules in the chip increases, the I/O resources do not increase accordingly, and the test efficiency of the chip is lower. Low. Figure 1 is a schematic diagram of the digital logic scale of the chip and the transmission bandwidth available for multiplexing of the Scan test vectors. The horizontal axis represents the year, and the two vertical axes represent the digital logic scale and the transmission bandwidth of the Scan test vectors respectively. It can be seen that as time progresses, there are two curves representing the logical scale of the chip: the logical scale of the network project (X-network project) shown by curve 1 and the logical scale of the terminal project (Terminal project) shown by curve 2 Rapid growth; however, among the 2 curves of the total bandwidth of digital pins, curve 3 and curve 4 show that: with the increase of the access frequency of I/O resources in the X-network project from 8Gbps to 10Gbps, and in the Terminal project As the access frequency of I/O resources increases from 6.4Gbps to 8Gbps, the total pin bandwidth of I/O resources (I/O quantityⅹaccess frequency) increases slowly.

At present, the test protocol based on the international standard of Institute of Electrical and Electronics Engineers (IEEE) 1149.10 describes how to use the serial-to-parallel conversion function channel of SerDes to realize the high-speed transmission of Scan data, which can be used as a chip after parallel The tested Scan I/O can solve the limitation of digital I/O transmission bandwidth. For example, a single lane SerDes I/O can be used as a basic functional channel for multiplexing to provide as much Scan test bandwidth as possible. However, the 1149.10 standard does not specify and limit the specific architecture and design of specific user manufacturers. At the same time, this technology is directly related to the SerDes used by each manufacturer. There is no mature design architecture for high-speed transmission of Scan data, that is, the technology maturity is low. Only The relevant package (Packets) protocol part does not regulate its circuit architecture and implementation method, and requires a series of ecosystem support from design, verification, test vectors, and diagnosis. Moreover, major manufacturers choose to construct two complex first-in-first-out (First In First Output, FIFO) inside the codec circuit after serial-to-parallel conversion to realize the Scan test bandwidth, and there is a large internal overhead.

To sum up, the Scan test of the chip needs to reuse I/O resources to complete the expansion of logic modules (or pattern graphics). However, with the deepening of the process and the increase of the logic scale, the number of I/O resources required is not proportional to the I/O bandwidth resources of the actual chip, and it is urgent to expand the reusable I/O bandwidth resources.

In this regard, the present application proposes a chip test circuit for loading and transmitting test data, which can use a high-speed serial test interface, such as HSSTI, to convert the high-speed serial input data received from the test machine into input transmitted in multiple channels Data, through the first transmission, the multi-channel input data is normalized into single-channel input data for chip testing, and the single-channel output data obtained after the test is converted into multiple-channel output data through the second transmission. The high-speed serial test interface converts the output data of multiple channels into high-speed serial output data and feeds it back to the test machine. In this way, when the high-speed serial test interface receives high-speed serial input data and converts it into multi-channel input data, the transmission of high-speed serial input data and converted multi-channel input data can greatly increase the transmission rate of test data. Secondly, when the application utilizes the high-speed serial test interface to receive high-speed serial input data and output multi-channel input data, even if the logic resources to be tested in the chip continue to increase, the I/O resources for test data transmission only take up There are fewer I/O pins on the chip (pins for high-speed serial input data, pins for high-speed serial output data, pins for multi-channel input data and pins for multi-channel output data). Moreover, through an uplink and downlink transmission (Gearbox, the bit width and frequency of its input and output terminals will change) can realize the normalized integration of multi-channel input data bit width, which can increase the routing frequency of the test bus (Bus).

The high-speed serial input data in this application can be understood as the serial input data whose rate is greater than or equal to 1.25 Gbps.

As shown in FIG. 2 , the chip test design framework of the present application can be applied to the docking scene between an automated tester equipment (ATE) and a device under test (DUT). The DUT here can be, for example, a chip.

Exemplarily, ATE can realize, for example, a single-channel high-speed code stream of 5-10Gbps, and when matching the design architecture provided by this application, it can realize test data transmission with a very large bandwidth, meet the test I/O requirements of ultra-large-scale chips, and can approximate Multiplexing resources for 100-400 ordinary low-speed 100Mhz digital I/Os.

For example, as shown in FIG. 3 , in the chip, the chip test circuit provided by the present application may include a high-speed serial test interface, a first transmission and a second transmission. The high-speed serial test interface and the test machine are interconnected based on capacitive coupling, and the data transmitted by the test machine is received in a differential transmission mode. This coupling mode and data transmission mode are to match the high-speed serial test interface to receive high-speed serial input data from the test machine.

Wherein, the output terminal a of the test machine is coupled to the input terminal b of the high-speed serial test interface, and multiple RX ports of the high-speed serial test interface are coupled to multiple input terminals (c, d, ...) of the first transmission, and the second The output terminal e of a transmission is coupled with the test bus; the input terminal f of the second transmission is coupled with the test bus, and multiple output terminals (g, h, ...) of the second transmission are coupled with multiple TX terminals of the high-speed serial test interface , the output end i of the high-speed serial test interface is coupled with the input end j of the test machine.

The high-speed serial test interface can be used to receive the high-speed serial input data sent by the test machine, convert the high-speed serial input data into multi-channel input data, and send the multi-channel input data to the first transmission; for example, the high-speed serial data The input data is 5Gbps, the high-speed serial test interface receives 5GGbps serial input data through a single channel (b port), and after converting the serial input data into multi-channel input data, passes through multiple RX ports of the high-speed serial test interface The multi-channel input data will be output. The multi-channel input data here includes test data to be tested on the circuit to be tested of the chip.

The first transmission is used to normalize multi-channel input data into single-channel input data, the single-channel input data is used to test the circuit to be tested, and the circuit to be tested is coupled with the chip test circuit. The normalization here can be realized by, for example, bit width conversion. For example, 4 channels, each of which transmits 32-bit multi-channel input data, undergoes bit width conversion to obtain single-channel 32-bit input data. The transmission frequency of single-channel 32-bit input data is the frequency of each of the 4 channels. 4 times the transmission frequency.

The second transmission is used to receive single-channel output data from the circuit to be tested, convert the single-channel output data into multi-channel output data, and send the multi-channel output data to the high-speed serial test interface; wherein, the single-channel output data and the single-channel Input data corresponding. For example, single-channel output data can be input to the second transmission at a frequency multiplied by 4, and when the second transmission converts the bit width of the single-channel output data to obtain 4-channel output data, it outputs 4-channel output data at a frequency of 1 multiplication .

The high-speed serial test interface is also used to convert multi-channel output data into high-speed serial output data, and send the serial output data to the test machine. For example, the 4-channel output data can be received from the second transmission through multiple TX ports of the high-speed serial test interface, and the high-speed serial test interface converts the 4-channel output data into high-speed serial output data and outputs it to the test machine.

Thus, when the application utilizes the high-speed serial test interface to receive high-speed serial data from the test machine and convert it into multi-channel input data transmission, the receiving rate of test data can be improved; the high-speed serial test interface receives from the second transmission In the case of channel output data and conversion to high-speed serial output data, the feedback rate of test results can be provided. Moreover, less I/O resources of the high-speed serial test interface can be used to transmit test data. Moreover, through the bit width conversion and frequency conversion of the input data and output data of the uplink and downlink transmissions, the routing frequency of the test data on the test bus can be increased.

Using the chip test circuit shown in FIG. 3 , the present application provides a chip test circuit as shown in FIG. 4 . The chip test circuit also includes a decoder, an encoder, an FSM, a first stream pipeline and a second stream pipeline. The first flow conduit and the second flow conduit include multi-level storage units. The first-stream pipeline and the second-stream pipeline here can be understood as streaming pipes.

The output terminal e of the first transmission is coupled to the input terminal k of the decoder, and the output terminal l of the decoder is coupled to the input terminal m of the first flow pipeline; the output terminal n of the first flow pipeline is coupled to the test bus of the test circuit;

The input terminal f of the second transmission is coupled to the output terminal o of the encoder, the input terminal p of the encoder is coupled to the output terminal q of the second flow pipeline, and the input terminal r of the second flow pipeline is coupled to the test bus;

The FSMs are each coupled to a third end s of the decoder, a third end t of the encoder, a third end u of the first stream pipe and a third end v of the second stream pipe.

Using the chip test circuit shown in Figure 4, the decoder can be used to decode the single-channel input data, send the decoded test data to the first stream pipeline, and send the decoded instructions to the FSM;

an FSM for determining an operating state of the encoder, the first stream pipeline, and the second stream pipeline based on the decoded instructions;

The first-stream pipeline is used to transmit the test data to the test bus according to the operating state of the first-stream pipeline determined by the FSM;

The second stream pipeline is used to receive the test result returned by the test bus according to the operating state of the second stream pipeline determined by the FSM, and send the test result to the encoder;

The encoder is used to encode the test result according to the operating state of the encoder determined by the FSM to obtain single-channel output data, and send the single-channel output data to the second transmission.

Using the chip test circuit shown in Figure 4, the present application provides a method for testing a chip, as shown in Figure 5, the method includes:

501. The chip receives the high-speed serial input data sent by the testing machine through the high-speed serial test interface, and converts the high-speed serial input data into multi-channel input data.

Among them, the serial input data can be understood as the code elements that make up the data and characters are transmitted bit by bit in time sequence. High-speed serial input data, for example, can be understood as serial input data with a transmission rate higher than 100 Mhz and a transmission bandwidth of 5-10 Gbps on a single channel. Multi-channel input data can be understood as data transmitted on multiple channels, for example, a data packet transmitted on a single channel is divided into 4 parts, and input data is transmitted on 4 channels.

Exemplarily, when the test machine is ATE, and the high-speed serial test interface is HSSTI, as shown in Figure 6, HSSTI can receive the high-speed serial input data sent by ATE, and convert the high-speed serial input data into four channels transmission to get 4-channel input data. The transmission rate of high-speed serial input data is 5Gbps, and the bit width is 128 bits. The 128-bit wide high-speed serial input data is switched to 4 copies and input to the first transmission in 4 channels, and the bit width of each channel is 32 bits. .

502. The chip normalizes the multi-channel input data into single-channel input data, and the single-channel input data is used to test the circuit to be tested in the chip.

In some embodiments, it is assumed that multi-channel input data is transmitted on M channels, where M is an integer greater than 1. The first transmission can be used to receive multi-channel input data in the 1-multiple frequency clock domain, perform bit width conversion on the multi-channel input data to obtain single-channel input data; and output single-channel input data in the M-multiple frequency clock domain. Wherein, the bit width occupied by single-channel input data is fixed.

Wherein, the bit width of each of the M channels output by the HSSTI is usually related to the service mode, for example, it may be 16 bits, 32 bits or 40 bits. The bit width shown in FIG. 6 is 32 bits.

In some embodiments, as shown in FIG. 7 (taking four 32-bit wide channels as an example), the first transmission includes a first buffer and a first bit width conversion circuit;

The first buffer is used to buffer the multi-channel input data received from the high-speed serial test interface in the 1-fold clock domain; the first bit width conversion circuit is used to output the channel bit width of the single-channel input data from the first The buffer reads the multi-channel input data, obtains the single-channel input data, and outputs the single-channel input data in the M multiplied clock domain;

Exemplarily, when the first transmission receives input data of four 32-bit wide channels in the 1-fold clock domain, the input data of the four 32-bit wide channels may be buffered in the first buffer first, and then The first bit-width conversion circuit can read input data with a 32-bit width from the first buffer, and output single-channel 32-bit-wide input data in an M-times clock domain, thereby realizing multi-channel data normalization processing.

Wherein, there may be multiple implementation manners for the 1-multiplied clock domain and the M-multiplied clock domain here. For example, as shown in Figure 8, assuming that M is 4, there are clock sources with the same source and no frequency offset on both sides of the first transmission. In HSSTI, the first transmission can be in the clock domain divided by 4 (CLK frequency division 4) Receive input data of four 32-bit wide channels through the first clock pin (rxoclk), and output single-channel 32-bit wide input data through the second clock pin (rxauxclk) in the clock domain divided by 1. In other words, the first transmission receives input data of four 32-bit wide channels through rxoclk in the 1-fold clock domain, and outputs normalized single-channel 32-bit wide input data through rxauxclk in the 4-fold clock domain. The implementation of the second transmission is similar to that of the first transmission. The second transmission receives single-channel 32-bit wide output data through rxauxclk in the 4-fold clock domain, and outputs four 32-bit wide channels through rxoclk in the 1-fold clock domain. Output Data. In some other manners, clock domains with the same source and no frequency offset may also be set in the ATE to ensure that the clock domains at both sides of the first transmission are of the same source.

For another example, as shown in Figure 9, if HSSTI cannot internally divide the frequency to generate 1-frequency division and 4-frequency division clock domains, or the HSSTI 4-frequency division clock is not output to the pins of the module, you can consider Outside the HSSTI, use the second clock pin divided by 1 to instantiate a CLK divided by 4, and the first transmission can use this clock to receive input data from four 32-bit wide channels. Note that the input data at this time comes from the clock domain of the original first clock pin inside the HSSTI, and it is necessary to ensure that the corresponding synchronization process is performed between the clock domain of the received input data and CLK4.

In some embodiments, the bit width of the single-channel input data output by the first transmission is fixed, which is the same as the bit width of the single-channel output data input to the second transmission, that is, the bit width of the single-channel output data input to the second transmission Also fixed. For example, in the example shown in FIG. 6 , the normalized bit width of the first transmission is defined as 32 bits by default, and the bit width input to the second transmission is also 32 bits by default. That is to say, when the bit width of each channel in the multi-channel input data input to the first transmission is any bit width such as 16 or 32 or 40, the multi-channel input data is normalized into a 32-bit fixed frame format Continue processing. This processing of data packets per frame based on a fixed frame format can form a simple and efficient transmission method. Here, the bit width of each channel in the multi-channel input data of HSSTI is generally related to the business mode.

503. The chip decodes the single-channel input data to obtain decoded instructions and test data.

Exemplarily, when the first transmission uses the bit width normalization of the above transmission to output 32-bit wide single-channel input data to the decoder, the decoder can decode the single-channel input data to identify the frame of the input data stream Header, frame trailer, instruction and content, etc. Among them, a single-channel input data can be understood as a frame of data. The FSM may determine the operating states of the encoder, the first stream pipeline, and the second stream pipeline according to the decoded instruction, that is, execute step 504 . The content here can be understood as test data, such as Scan test data.

504. The chip determines the operating states of the encoder, the first stream pipeline, and the second stream pipeline according to the decoded instruction.

It can also be understood that the decoder sends the decoded instruction to the FSM, and the FSM can customize the corresponding state machine sequence of the encoder, the first stream pipeline, and the second stream pipeline according to the decoded command. For example, the sequence in which the encoder enters the encoding state, the sequence in which the first stream pipeline caches the test data in the multi-level storage unit, and the sequence in which the second stream pipeline caches the fed back test data in the multi-level storage unit.

It has been explained above that the bit width of the single-channel input data output by the first transmission is fixed, and the bit width of the single-channel output data input to the second transmission is also fixed, so FSM can be understood as an FSM based on a fixed bit width as one state, Each data frame can be defined as a state.

Exemplarily, according to the definition requirements of the IEEE 1149.10 protocol, in the data stream of single-channel input data:

The format of the frame header can be: 8 bits of frame header + 8 bits of CMD + 16 bits of Payload (content), and the unified name is "CMD";

The format of cyclic redundancy check (Cyclic Redundancy Check, CRC) occupies 32 bits, and is named "CRC" uniformly; it is used to check the single-channel input data;

The format of the frame end occupies 32 bits, and the unified command is "EOP".

When the decoder recognizes the frame header and frame tail according to the definition requirements, and the single-channel input data between the frame header and the frame tail is a complete frame of data.

Wherein, the type of CMD may include common CMD, CHCMD (Chselect CMD, channel selection CMD) and test CMD (ScanCMD). When the decoder recognizes these 3 CMDs and sends them to the FSM, the FSM can enter 3 states according to the 3 CMDs.

Figure 10 is a schematic diagram of the state of the FSM. When the FSM receives the normal CMD in the decoded command, the FSM can jump to the CMD state, that is, enter the state of configuring the test circuit. During the configuration process, the state of the FSM is idle state (idle)-CMD-CRC-EOP. For example, the configuration process can be understood as processing such as resetting the test circuit. That is, the test circuit must be unlocked first, and the circuit configuration is performed, such as selecting some variables in the decoder, performing the configuration of the number of storage units of the first stream pipeline and the second stream pipeline, and configuring the test bus, bit width and rate, etc. ;

When the FSM receives CHCMD in the decoded command, the FSM can jump to the state of CHCMD, that is, enter the operation state of channel selection, so as to determine the test bus for transmitting test data. The state of the FSM in this process may be idle-CHCMD-CH content-CRC-EOP. For example, the test bus includes buses with a bit width of 32, 64, and 128 bits. When the content (Chselect content, CH content) after the CHCMD instruction indicates that the test bus with a 32-bit bit width is selected, the FSM will indicate that the test data transmitted by the first-stream pipeline is in the The 32-bit wide test bus enters the chip.

When the FSM receives the decoded instruction and the test CMD in the content, the FSM can jump to the test CMD state, that is, enter the test data transmission state, so as to transmit the test data on the test bus. The state of the FSM in this process may be idle-test CDM-test content-CRC-EOP. When the FSM recognizes a test CDM, it can instruct the decoder and first stream pipe to transmit test data to the bus.

505. The chip outputs the test data to the test bus in the chip after being buffered by the multi-level storage unit, and transmits the test data to the circuit to be tested through the test bus.

That is to say, when the first stream pipeline receives the test data from the decoder, the first stream pipeline may perform multi-level buffering on the test data through the multi-level storage unit and then output it to the test bus.

In some embodiments, the test circuit further includes a gating circuit coupled to each level of storage units in the multi-level storage unit; the first stream pipeline includes a first level storage unit and a second level storage unit;

The first level storage unit is used for buffering the test data received from the decoder;

The first-level storage unit is further configured to send the test data stored in the first-level storage unit to the second-level storage unit when receiving the clock signal sent by the gate control circuit coupled with the first-level storage unit;

The second-level storage unit is used for buffering the test data received from the first-level storage unit.

Exemplarily, FIG. 11 shows a schematic diagram of inputting test data to the first-stream pipeline. When the decoder decodes single-channel input data to obtain test data, the test data is input to the first-stream pipeline. Wherein, the first stream pipeline is a 3-level storage unit: a 1-level storage unit, a 2-level storage unit, and a 3-level storage unit, and each level of storage unit includes a plurality of storage units (the storage unit can be a register, for example, and FIG. 11 shows 32 register). Each storage unit is coupled with a gate control circuit for beating test data. For example, when gate control circuit A receives write enable (write_enable) signal 1, gate control circuit A can send clock signal (WCLK) 1 to level 1 storage unit, and level 1 sends the test data in the storage unit to level 2; After a period of time, when gate control circuit B receives write enable signal 2, gate control circuit B can send clock signal 2 to level 2, and level 2 sends the test data in the storage unit to level 3; after a period of time, gate When the control circuit C receives the write enable signal 3, the gate control circuit C can send the clock signal 3 to the third stage, and the third stage sends the test data in the storage unit to the test bus. The write enable signal can be triggered by a counter generator in the FSM.

It should be noted that the clock signals of the gate control circuit, the decoder and the FSM can be from the same source, that is, they all come from the same main clock (main clock). The first stream pipe may transmit test data to the test bus according to the operating state of the first stream pipe determined by the FSM (received multiple enable signals).

506. According to the decoded instruction, the chip caches the test result returned from the circuit to be tested through the multi-level storage unit, and encodes the cached output test result to obtain single-channel output data.

When the test data is returned to the second flow pipeline through various timing conversions and various interface transmissions in the chip, the internal structure of the second flow pipeline is similar to that of the first flow pipeline shown in Figure 11, that is, the test result When returning to the second stream pipeline, the second stream pipeline receives the test result returned through the test bus according to the operating state of the second stream pipeline determined by the FSM, and returns the test result to the encoder through the multi-level storage unit in the second stream pipeline . The encoder then encodes the test results to obtain single-channel output data.

It can be understood that in this application, the operating states of the encoder, the first stream pipeline and the second stream pipeline determined by the FSM should coincide with the timing of data processing by the encoder, the first stream pipeline and the second stream pipeline, so as to realize the state and data Seamlessly.

In the embodiment of the present application, the seamless connection between the state and data can be realized by FSM determining the number of storage units that cache data in the first stream pipeline and the second stream pipeline, that is, the number of storage units through the streaming pipe accomplish. That is to say, the number of stages of the storage units of the first stream pipeline and the second stream pipeline is consistent: the FSM triggers the encoder to enter the state of encoding the single-channel response data, which is consistent with the moment when the single-channel response data is returned to the encoder.

That is to say, the number of stages of storage units in the first stream pipeline and the number of stages of storage units in the second stream pipeline can be used to determine the waiting time for the encoder to start encoding the test results. That is, after the test data is sent out, after the number of storage units in the first stream pipeline and the number of storage units in the second stream pipeline, when the test result reaches the encoder for compilation, at this time, the FSM just triggers the encoder to enter the encoding state , which matches the timing when the test results are returned to the encoder, enabling pipelined test data transmission without delay. This implementation method does not require any FIFO to cache test data and test results, and realizes the complete pipeline processing of test data input and test result output through fixed frame FSM, which is less difficult and expensive to implement, and is more friendly to physical implementation and timing.

507. The chip converts the single-channel output data received from the circuit to be tested into multi-channel output data, and the single-channel output data corresponds to the single-channel input data.

The encoder can send the obtained single-channel output data to the second transmission, and the second transmission is used to receive the single-channel output data in the M multiplied clock domain, perform bit width conversion on the single-channel output data, and obtain multi-channel output data ; Output multi-channel output data at 1 multiplier clock.

In some embodiments, the second transmission includes a second buffer and a second bit width conversion circuit;

The second buffer is used to buffer the single-channel output data received under the M-multiplied clock domain; the second bit width conversion circuit is used to transfer from the second buffer according to the bit width of each channel of output multi-channel output data Read single-channel output data, obtain multi-channel output data, and output multi-channel output data in the 1-fold frequency clock domain.

It can be understood that the implementation of the second transmission is similar to that of the first transmission. Assuming that the multi-channel output data is four 32-bit wide output data, it can also be realized by a circuit result similar to that shown in FIG. 8 or FIG. The single-channel 32-bit wide output data is received under the domain, and after buffering in the second buffer of the second transmission, the single-channel 32-bit wide output data is converted into output data of four 32-bit wide channels by the second bit-width conversion circuit , output the output data of four 32-bit wide channels to a high-speed serial test interface in a 1-fold clock domain, for example, to multiple TX ports of HSSTI.

508. The chip converts the multi-channel output data into high-speed serial output data through the high-speed serial test interface, and sends the serial output data to the test machine.

Exemplarily, when multiple TX terminals of the HSSTI receive 4-channel output data, the 4-channel output data can be converted into high-speed serial output data, and the high-speed serial output data can be sent to the test machine through a single channel, so that The test machine can determine whether the circuit to be tested of the chip is normal through the received high-speed serial output data.

It can be understood that when the application utilizes the high-speed serial test interface to receive high-speed serial data from the test machine and convert it into multi-channel input data transmission, the receiving rate of test data can be improved; the high-speed serial test interface receives from the second transmission In the case of channel output data and conversion to high-speed serial output data, the feedback rate of test results can be provided, and overall, the chip test efficiency is improved. Moreover, less I/O resources of the high-speed serial test interface can be used to transmit test data. Moreover, through the bit width conversion and frequency conversion of the input data and output data of the uplink and downlink transmissions, the routing frequency of the test data on the test bus can be increased.

Moreover, this application can normalize the bit width based on the first transmission and the second transmission, and complete the chip test based on the normalized fixed bit width fixed frame state machine, encoder, decoder and streaming pipe, HSSTI peripheral The encoding and decoding circuit structure of the chip is simple, and no cache structure such as FIFO is required, which reduces the chip footprint.

Based on the above method for testing a chip corresponding to FIG. 5 , the present application further provides a chip testing circuit. This chip test circuit comprises outside the circuit structure in Fig. 4, as shown in Fig. 12, also comprises a plurality of frame header alignment (framer) device, pass to alignment (Bonding) device, descrambler, scrambler, multiplexer Distributor (demultiplexer, DEMUX) and combiner (MUX). In FIG. 12 , multi-channel input data is shown by taking four 32-bit channel input data as an example. The example of high-speed serial test interface is HSSTI, and the example of test machine is ATE.

Wherein, a plurality of input ends (s, t, ...) of a plurality of frame header aligners are coupled with a plurality of output ports of a high-speed serial test interface, and a plurality of output ends of a plurality of frame header aligners are coupled with a plurality of output ports of a channel alignment circuit Input terminals (v, w, ...) are coupled. That is, the input end of each frame header aligner is coupled to an output port of the high-speed serial test interface, and the output end of each frame header aligner is coupled to an input end of the channel aligner. Multiple outputs of the channel aligner are coupled to multiple inputs (c, d, . . . ) of the first transmission. The input end of the descrambler is coupled with the output end e of the first transmission, the output end x of the descrambler is coupled with the input end k of the decoder; the output end n of the first stream pipeline is coupled with the input end y of the demultiplexer, The output end of the demultiplexer is coupled with the test bus; the input end of the combiner is coupled with the test bus, and the output end of the combiner is coupled with the input end r of the second stream pipeline; the input end of the scrambler is coupled with the encoder The output terminal o is coupled, and the output terminal A of the scrambler is coupled to the input terminal f of the second transmission.

In some embodiments, each frame header aligner is used to input data from one channel of the multi-channel input data from one output port of the high-speed serial test interface, and perform data framing on the input data of this one channel After the header is aligned, it is output to the channel aligner. Exemplarily, as shown in FIG. 13 , the frame header aligner corresponding to each channel may include a third buffer and a frame header alignment circuit, and the third buffer may be used to output RX from a high-speed serial test interface. The input data of one channel in the received multi-channel input data is buffered, and the frame header alignment circuit can read the multiple input data transmitted by the channel from the third buffer, and perform multiple input data according to the sequence of the frame header output after sorting.

The channel aligner is configured to perform inter-channel data alignment on the multi-channel input data received from multiple frame header alignment circuits, and then output the data to the first transmission. Exemplarily, as shown in FIG. 13, the channel aligner may include a fourth buffer and a channel alignment circuit. The fourth buffer may be used to buffer the received input data sent by multiple channel alignment circuits. The channel alignment The circuit can read input data corresponding to multiple channel alignment circuits from the fourth buffer, and perform channel alignment on multiple input data according to multiple copies of the same data packet, so that the multiple data transmission rates of the same data packet Consistent, the first derailleur can be reached at the same time.

It can be understood that when the input data of the four 32-bit wide channels output from HSSTI is input to the first transmission, the input data packets may be out of order, so the framer can receive the four 32-bit wide channels received from HSSTI The input data is frame-head aligned, so that the input data of each of the 4 channels is sent to the channel aligner in the sequence after the frame header is aligned. The data alignment between channels by the channel aligner can be understood as, due to the possible inconsistency in the transmission speed of each channel, when a data packet is divided into 4 parts and transmitted on 4 channels, each part of data is transmitted on a different channel may not reach the first transmission at the same time, therefore, the channel aligner can transmit the small data packets of the same data packet to the first transmission at the same time when transmitted on different channels.

The descrambler is used to descramble the single-channel input data, that is, the input data sent by the ATE is scrambled. Similarly, when the single-channel output data is to be output, the single-channel output data also needs to be scrambled by a scrambler.

A demultiplexer can be understood as a combinational logic circuit that transfers a single-channel input data to a designated output. For example, the demultiplexer transmits single-channel input data to a 32-bit wide test bus port for output to the circuit under test, or to a 64-bit wide test bus port for output to the circuit under test, or to a 128-bit wide test bus The port outputs to the circuit to be tested, etc.

The combiner can be understood as feeding back the test results transmitted from the test bus ports with different bit widths to the second stream pipeline through the combiner.

When the encoder encodes the test result to obtain single-channel output data, the scrambler is used to scramble the single-channel output data and then output it to the second transmission.

In addition, when the first transmission receives the multi-channel input data sent by the framer, the first transmission can send a read start trigger signal (trigger the read operation) to the second transmission to instruct the second transmission to start working. At this time, the HSSTI, frame header aligner, first transmission, and second transmission in Figure 12 form a closed-loop system, which is similar to the remote parallel loopback mode of SerDes and becomes a Deterministic system. The remote parallel loopback mode of the SerDes can be understood as a path through which the parallel data converted by the SerDes is directly looped back to the TX port of the SerDes without unpacking. The Deterministic system can be understood as a deterministic system, which is used to delay the input data sent by the RX of the SerDes through the deterministic whole deterministic system, and the deterministic expected data can be observed on the TX side of the SerDes. In this closed-loop system, RX and TX form a relatively stable phase relationship, and the first upstream transmission (write side) and the second downstream transmission (reading side) form an internal self-driven synchronous response mode, which maintains the accuracy of the chip test circuit. knowledge and uniqueness.

It can be understood that the Deterministic system is conducive to docking with the waveform generation language (waveform generation language, WGL/Standard for extensions to Standard Test Interface Language, STIL) format vector of the traditional test machine to complete the corresponding chip test. The standard requirements for the hardware and software of the test machine are reduced, which is conducive to the large-scale realization of the mass production of the test machine.

The embodiment of the present application also provides a chip 14, which can be any chip to be tested.

In some embodiments, as shown in FIG. 14 , the chip 14 may include a chip test circuit, a circuit to be tested, a test bus, and the like. The chip test circuit is coupled with the test machine. The chip testing circuit and internal structure of the chip may be any circuit structure as shown in FIGS. 3 to 13 of the present application. The circuit to be tested can be a logic module in the chip. The test bus is used to receive test data from the chip test circuit. The test data is processed by the circuit to be tested and fed back to the test result. The test result is returned to the chip test circuit through the test bus.

It should be noted that, besides ATE, the test machine in this application can also be a system level test (System Level Test, SLT) or even other test machines or lead-in boards.

Thus, the chip provided by the application includes the above-mentioned test circuit, can multiplex the I/O resources of RX and TX in a small part of the high-speed serial test interface as a test data loading channel, transmit high-speed serial input data, and perform serial After conversion, it is sent to the first transmission, and the feedback test results are multi-channel output to the high-speed serial test interface through the second transmission, which can solve the limitation of the I/O transmission bandwidth used for chip testing and avoid internal logic resources of the chip. The problem of low test efficiency caused by the increase in mass production of chips. Moreover, this application does not need to use FIFO to cache test data, but uses streaming pipe to cache test data. Compared with FIFO, the occupied chip area is smaller.

Through the description of the above embodiments, those skilled in the art can understand that for the convenience and brevity of the description, only the division of the above functional modules is used as an example for illustration. In practical applications, the above functions can be assigned by different Completion of functional modules means that the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

In the several embodiments provided in this application, it should be understood that the disclosed devices and methods may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be Incorporation or may be integrated into another device, or some features may be omitted, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.

The unit described as a separate component may or may not be physically separated, and the component displayed as a unit may be one physical unit or multiple physical units, that is, it may be located in one place, or may be distributed to multiple different places . Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

If the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the software product is stored in a storage medium Among them, several instructions are included to make a device (which may be a single-chip microcomputer, a chip, etc.) or a processor (processor) execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: various media that can store program codes such as U disk, mobile hard disk, read only memory (ROM), random access memory (random access memory, RAM), magnetic disk or optical disk.

The above content is only the specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application, and should covered within the scope of protection of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims

A chip test circuit, characterized in that the chip test circuit includes a high-speed serial test interface, a first transmission and a second transmission, the high-speed serial test interface and the test machine are interconnected based on capacitive coupling, and adopt Receive the data transmitted by the test machine in a differential transmission mode;

The high-speed serial test interface is used to receive the high-speed serial input data sent by the test machine, convert the high-speed serial input data into multi-channel input data, and send the multi-channel input data to the first transmission Input data;

The first transmission is used to normalize the multi-channel input data into single-channel input data, the single-channel input data is used to test the circuit to be tested, and the circuit to be tested is coupled to the chip test circuit;

The second transmission is used to receive single-channel output data from the circuit to be tested, convert the single-channel output data into multi-channel output data, and send the multi-channel output data to the high-speed serial test interface , wherein the single-channel output data corresponds to the single-channel input data;

The high-speed serial test interface is also used to convert the multi-channel output data into high-speed serial output data, and send the high-speed serial output data to the test machine.
The test circuit according to claim 1, wherein the multi-channel input data is transmitted on M channels, and M is an integer greater than 1;

The first transmission is configured to receive the multi-channel input data in the 1-multiple frequency clock domain, perform bit width conversion on the multi-channel input data, and obtain the single-channel input data; in the M-multiple frequency clock domain outputting the single-channel input data;

The second transmission is used to receive the single-channel output data in the M-multiplied clock domain, perform bit width conversion on the single-channel output data, and obtain the multi-channel output data; output under the 1-multiplied clock The multi-channel output data;

Wherein, the bit width occupied by the single-channel input data and the bit width occupied by the single-channel output data are fixed.
The test circuit according to claim 2, characterized in that,

The first transmission includes a first buffer and a first bit width conversion circuit;

The first buffer is used for buffering the multi-channel input data received from the high-speed serial test interface under the 1-fold frequency clock domain; the first bit width conversion circuit is used for outputting according to the The channel bit width of the single-channel input data reads the multi-channel input data from the first buffer to obtain the single-channel input data, and outputs the single-channel input data under the M multiplied clock domain ;

The second transmission includes a second buffer and a second bit width conversion circuit;

The second buffer is configured to buffer the single-channel output data received in the M-multiplied clock domain; the second bit width conversion circuit is configured to output the multi-channel output data according to each Read the single-channel output data from the second buffer with a bit width of two channels to obtain the multi-channel output data, and output the multi-channel output data in the 1-fold frequency clock domain.
The test circuit according to any one of claims 1-3, wherein the test circuit further comprises a decoder, an encoder, a finite state machine (FSM), a first flow pipeline and a second flow pipeline; the first flow pipeline and said second flow conduit each comprising a multi-level storage unit;

The output end of the first transmission is coupled to the input end of the decoder, and the output end of the decoder is coupled to the input end of the first flow pipeline; the output end of the first flow pipeline is coupled to the test circuit Test bus coupling;

The input of the second transmission is coupled to the output of the encoder, the input of the encoder is coupled to the output of the second flow conduit, the input of the second flow conduit is coupled to the test bus coupling;

The FSMs are each coupled to the decoder, the encoder, the first stream pipe, and the second stream pipe.
The test circuit according to claim 4, characterized in that,

The decoder is configured to perform a decoding operation on the single-channel input data, send the decoded test data to the first stream pipeline, and send the decoded instruction to the FSM;

the FSM is configured to determine an operating state of the encoder, the first stream pipeline, and the second stream pipeline based on the decoded instructions;

the first stream pipe, configured to transmit the test data to the test bus according to the operating state of the first stream pipe determined by the FSM;

The second stream pipeline is configured to receive a test result returned through the test bus according to the operating state of the second stream pipeline determined by the FSM, and send the test result to the encoder;

The encoder is configured to encode the test result according to the operating state of the encoder determined by the FSM, obtain the single-channel output data, and send the single-channel output data to the second transmission .
The test circuit according to claim 5, wherein the test circuit further comprises a gating circuit coupled to each level of storage units in the multi-level storage units; the first stream pipeline comprises a first level of storage units and secondary storage units;

The first-level storage unit is configured to buffer the test data received from the decoder;

The first-level storage unit is further configured to send the clock signal in the first-level storage unit to the second-level storage unit when receiving a clock signal sent by a gating circuit coupled to the first-level storage unit. said test data stored;

The second-level storage unit is configured to cache the test data received from the first-level storage unit.
The test circuit according to any one of claims 1-6, wherein the test circuit also includes a plurality of frame header aligners and channel aligners; the input end of each frame header aligner is connected to the high-speed serial One output port of the row test interface is coupled, the output end of each frame header aligner is coupled with one input end of the channel aligner, and the multiple output ends of the channel aligner are coupled with the multiple output terminals of the first transmission input port coupling;

Each frame header aligner is used to receive one channel input data in the multi-channel input data from an output port of the high-speed serial test interface, and perform data frame on the input data of the one channel After the head is aligned, it is output to the channel aligner;

The channel aligner is configured to perform inter-channel data alignment on the multi-channel input data received from the plurality of frame header aligners, and then output the data to the first transmission.
The test circuit according to claim 7, characterized in that,

Each frame header aligner includes a third buffer and a frame header alignment circuit;

The third buffer is used for buffering one channel input data in the multi-channel input data received from an output port of the high-speed serial test interface; the frame header alignment circuit is used for Reading the input data of the one channel in the third buffer, and sorting the input data of the one channel according to the frame header and outputting it to the channel alignment circuit;

The channel aligner includes a fourth buffer and a channel alignment circuit;

The fourth buffer is used to buffer multiple channel input data sent from the multiple channel alignment circuits; the channel alignment circuit is used to read the multiple channel input data from the fourth buffer , performing channel-to-channel alignment on the multiple channel input data and outputting it to the first transmission.
A method for testing a chip, characterized in that the chip includes a high-speed serial test interface, the high-speed serial test interface is interconnected with a test machine based on a capacitive coupling method, and the test machine is received by a differential transmission method The data transmitted, the method includes:

The chip receives the high-speed serial input data sent by the test machine through the high-speed serial test interface, and converts the high-speed serial input data into multi-channel input data;

The chip normalizes the multi-channel input data into single-channel input data, and the single-channel input data is used to test the circuit to be tested in the chip;

The chip converts the single-channel output data received from the circuit to be tested into multi-channel output data, and the single-channel output data corresponds to the single-channel input data;

The chip converts the multi-channel output data into high-speed serial output data through the high-speed serial test interface, and sends the high-speed serial output data to the test machine.
The method according to claim 9, wherein the multi-channel input data is transmitted on M channels, and M is an integer greater than 1;

The chip normalizing the multi-channel input data into single-channel input data includes: the chip performs bit width conversion on the multi-channel input data transmitted in the 1-fold frequency clock domain to obtain the M-multiple frequency clock domain. said single-channel input data transmitted;

The chip converting the single-channel output data received from the circuit to be tested into multi-channel output data includes: the chip performs bit width conversion on the single-channel output data received under the M frequency multiplied clock domain, Obtain the multi-channel output data transmitted under 1 multiplied clock;

Wherein, the bit width occupied by the single-channel input data and the bit width occupied by the single-channel output data are fixed.
The method according to claim 10, characterized in that,

The chip normalizing the multi-channel input data into single-channel input data includes:

The chip buffers the multi-channel input data received from the high-speed serial test interface under the 1-fold frequency clock domain; the chip controller outputs the channel bit width of the single-channel input data from the first buffer The device reads the multi-channel input data, obtains the single-channel input data, and outputs the single-channel input data under the M frequency multiplied clock domain;

The chip converting the single-channel output data received from the circuit to be tested into multi-channel output data includes:

The chip buffers the single-channel output data received under the M-multiplied clock domain; the chip reads the multi-channel output data from the second buffer according to the bit width of each channel that outputs the multi-channel output data Single-channel output data, obtaining the multi-channel output data, and outputting the multi-channel output data in the 1-multiplied clock domain.
The method according to any one of claims 9-11, wherein before the chip converts the single-channel output data received from the circuit to be tested into multi-channel output data, the method further comprises:

The chip performs a decoding operation on the single-channel input data to obtain decoded instructions and test data;

The chip outputs the test data to a test bus in the chip after buffering the test data through a multi-level storage unit, and transmits the test data to the circuit to be tested through the test bus;

According to the decoded instructions, the chip caches the test results returned from the circuit to be tested through multi-level storage units, and encodes the cached and outputted test results to obtain the single-channel output data.
The method according to claim 12, wherein the multi-level storage unit includes a first-level storage unit and a second-level storage unit; the chip outputs the test data to the The test bus in the chip includes:

controlling the first-level storage unit to cache the test data received from the decoder;

controlling the first-level storage unit to send all the data stored in the first-level storage unit to the second-level storage unit when receiving a clock signal sent by a gating circuit coupled to the first-level storage unit; The above test data;

and controlling the second-level storage to single-buffer the test data received from the first-level storage unit.
The method according to any one of claims 9-13, wherein before the chip normalizes the multi-channel input data into single-channel input data, the method further comprises:

The chip performs data frame header alignment on the input data of each channel in the multi-channel input data;

The chip performs inter-channel data alignment on the multi-channel input data after frame header alignment.
The method according to claim 14, wherein the frame header alignment performed by the chip on the input data of each channel in the multi-channel input data comprises:

The chip controls the third buffer to cache one channel input data in the multi-channel input data received from an output port of the high-speed serial test interface; the chip controls the frame header alignment circuit from the third Reading the input data of the one channel from the buffer, sorting the input data of the one channel according to the frame header and outputting it to the channel alignment circuit;

The chip performing data alignment between channels on the multi-channel input data after frame header alignment includes:

The chip controls the fourth buffer to cache multiple channel input data sent from the multiple channel alignment circuits; the chip controls the channel alignment circuit to read the multiple channel input data from the fourth buffer, and The input data of the multiple channels is aligned between channels and then output to the first transmission.
A communication device, characterized in that it includes at least one processor, the at least one processor is coupled to a memory, and the at least one processor is used to read and execute a program stored in the memory, so that the communication device Performing a method as claimed in any one of claims 9-15 above.
A computer-readable storage medium is characterized by comprising computer instructions, and when the computer instructions are run on the electronic device, the electronic device is made to execute the method described in any one of claims 9-15.