CN112543158A - Serdes architecture for 64B/66B conversion - Google Patents

Abstract

The invention provides a serdes framework of 64B/66B conversion, which comprises an XLGMII, a PCS layer and a PMA layer, wherein the interface bit width of the PCS layer and the PMA layer is configured to be 66 bit. According to the serdes framework of 64B/66B conversion, the serdes framework of 64B/66B conversion reduces the number of clocks inside a PCS (personal communications System) by configuring the PCS and the interface data width of the PMA to be 66bit, effectively reduces the working frequency and logic complexity inside the PCS, reduces the time sequence requirement of digital design inside the PCS, can effectively reduce the chip design cost, and improves the chip performance and reliability.

Description

Serdes architecture for 64B/66B conversion

[ technical field ] A method for producing a semiconductor device

The invention relates to the technical field of IP design of FPGA chips, in particular to a serdes framework for 64B/66B conversion.

[ background of the invention ]

A High-Speed Serial Transceiver (High Speed Serial Transceiver) is an important functional component in a High-Speed chip including a Field Programmable Gate Array (FPGA), and is composed of an IP such as a Physical Media Adaptation (PMA) layer and a Physical Coding Sub-layer (PCS). The PCS supports a flexible Word Alignment function; channel Bonding: channel alignment, ctc (clock Tolerance compensation): the common functions of compensating the tiny frequency difference of the sending clock and the receiving clock and the like are realized.

In serdes IP, 64B _66B codec is a common function that needs to be supported. In the architecture in the prior art, a sending side needs to switch clock frequencies through tx buffer in a tx _ gear _ box, and since the clock frequencies become faster, a read operation is suspended every 33 clock cycles, and an idle byte is inserted to ensure bandwidth matching. Then the 66bit data is integrated into 64bit data, and the idle byte is deleted to adapt to the requirements of the PCS/PMA interface.

The receiving side is opposite to the transmitting side, in the receiving speed changing box rx _ gear _ box, the 64-bit data is spliced into 66-bit data, and the 66-bit data is written into the rx buffer for clock domain switching, and as the clock domain is switched to a clock domain with lower clock frequency, one beat writing operation is suspended every 33 clock cycles, so that the receiving channel bandwidth matching is ensured.

In the structure, the PCS and PMA interfaces are 64bit (16bit, 20bit, 32bit and 40bit) bit wide, the interface rate is the ratio of the high-speed differential line rate to the bit wide, the PCS internal processing comprises two clock domains, a gear module is required to perform clock domain switching, data is reintegrated, the bit wide is converted, and the complexity of chip design is relatively high.

[ summary of the invention ]

The invention aims to provide a serdes framework of 64B/66B conversion.

In order to achieve the above purpose, the present invention provides a serdes architecture for 64B/66B conversion, which includes an XLGMII, a PCS layer and a PMA layer, and the interface bit width of the PCS layer and the PMA layer is configured to be 66 bits.

Preferably, the PCS layer comprises a PCS transmitting device, the PCS transmitting device comprises a coding module and a scrambling module,

the encoding module is used for encoding the interface data of the XLGMII into 64B _66B block data;

the scrambling module is used for scrambling the 64B _66B block data.

Preferably, the PMA layer comprises a PMA transmitting device.

Preferably, the PCS transmitting device and the PMA transmitting device are in the same clock domain.

Preferably, the PCS layer comprises a PCS receiving device, the PCS receiving device comprises a block synchronization module, a descrambling module and a decoding module,

the block synchronization module is used for synchronously defining the received 64B _66B block data according to the block synchronization header information;

the descrambling module is used for descrambling the 64B _66B block data;

the decoding module is configured to decode the 64B _66B block data after descrambling and send the decoded 64B _66B block data to the XLGMII.

Preferably, the PMA layer comprises a PMA receiving device.

Preferably, the PCS receiving device and the PMA receiving device are in the same clock domain.

The invention has the beneficial effects that: the serdes architecture of 64B/66B conversion is provided, the serdes architecture of 64B/66B conversion reduces the number of clocks inside a PCS (physical control System) by configuring the PCS and the interface data width of PMA to be 66bit, effectively reduces the working frequency and logic complexity inside the PCS, reduces the time sequence requirement of digital design inside the PCS, can effectively reduce the chip design cost, and improves the chip performance and reliability.

[ description of the drawings ]

FIG. 1 is a schematic structural diagram of a serdes architecture for 64B/66B conversion according to an embodiment of the present invention;

fig. 2 is a schematic diagram of frequency generation of a sending direction clock according to an embodiment of the present invention;

fig. 3 is a schematic diagram of frequency generation of a receive direction clock according to an embodiment of the present invention.

[ detailed description ] embodiments

The invention is further described with reference to the following figures and embodiments.

It should be noted that all directional indicators (such as upper, lower, left, right, front, back, inner, outer, top, bottom … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components in a specific posture (as shown in the figure), and if the specific posture is changed, the directional indicator is changed accordingly.

The embodiment of the invention provides a 64B/66B converted servers architecture, which comprises an XLGMII (Media Independent Interface), a PCS (personal communications System) layer and a PMA (physical attachment management) layer, wherein the Interface bit width of the PCS layer and the PMA layer is configured to be 66 bit.

The serdes framework of 64B/66B conversion of the invention reduces the number of PCS internal clocks, effectively reduces the working frequency and logic complexity in PCS, reduces the time sequence requirement of digital design in PCS, can effectively reduce the chip design cost and improve the chip performance and reliability by configuring PCS and the interface data width with PMA to be 66 bit.

Further, a line rate of 1/66 in frequency between the PCS layer and the PMA layer is configured.

In the embodiment, the PCS layer comprises a PCS transmitting device which comprises a coding module and a scrambling module,

the encoding module is used for encoding the XLGMII data into 64B _66B block data;

the scrambling module is used for scrambling the 64B _66B block data.

In this embodiment, the PCS layer comprises a PCS receiving device, the PCS receiving device comprises a block synchronization module, a descrambling module and a decoding module,

the block synchronization module is used for synchronously defining the received 64B _66B block data according to the block synchronization information;

the descrambling module is used for descrambling the 64B _66B block data;

the decoding module is configured to decode the 64B _66B block data after descrambling and send the decoded 64B _66B block data to the XLGMII.

Preferably, the PMA layer comprises a PMA transmitting device. Wherein, the PCS transmitting device and the PMA transmitting device are in the same clock domain.

Preferably, the PMA layer comprises a PMA receiving device. Wherein, the PCS receiving device and the PMA receiving device are in the same clock domain.

As shown in fig. 1, a 64B/66B converted serdes architecture provided in the embodiment of the present invention includes an XLGMII (Media Independent Interface), a PCS layer and a PMA layer, where Interface bit width of the PCS layer and the PMA layer is configured to be 66bit, and a line rate between the PCS layer and the PMA layer is 1/66.

The PCS layer comprises a PCS Transmit device and a PCS Receive device.

The PCS Transmit device comprises an encoding module encode and a scrambling module scrambler.

The encoding module encode is used for encoding the interface data of the XLGMII into 64B _66B block data; 8 data bytes or control words, and a 2-bit sync header (sync _ header) constitute one block of data.

The interface data in the sending direction XLGMII comprises TXD [127:0 ]: data transmission channel, 128 bits parallel data; TXC [15:0 ]: transmitting a channel control signal, wherein when the TXC is 0, the channel control signal indicates that data is transmitted on the TXD, and when the TXC is 1, the channel control signal indicates that control characters are transmitted on the TXD; TX _ CLK: the reference clocks of TXD and TXC sample data on both the rising and falling edges of the clock signal.

The scrambling module scrambles the 64B _66B block data to reduce the number of data connection of '1' to '0' in the 64B _66B block data, and a synchronous head (sync _ header) does not scramble.

The PCS receiving device PCS Receive comprises a block synchronization module block _ sync, a descrambling module descramble and a decoding module decode.

The block synchronization module block _ sync is used for synchronously defining the received 64B _66B block data according to the information of a block synchronization header (sync _ header);

the descrambling module is used for descrambling the 64B _66B block data;

the decoding module is configured to decode the 64B _66B block data after descrambling and send the decoded 64B _66B block data to the XLGMII.

The interface data in the receiving direction XLGMII comprises RXD [127:0 ]: data receive channel, 128 bits parallel data; RXC [15:0 ]: receiving a channel control signal, wherein when RXC is 0, data is transmitted on RXD, and when RXC is 1, control characters are transmitted on RXD; RX _ CLK: the reference clocks for RXD and RXC sample data on both the rising and falling edges of the clock signal.

Preferably, the PMA layer includes a PMA Transmitter apparatus PMA Transmitter and a PMA Receiver apparatus PMA Receiver.

The PCS transmitting device PCS Transmit and the PMA transmitting device PMA Transmit are in the same clock domain, namely, all modules in the transmitting direction work in the same clock domain, and the clock frequency is the transmitting serial data tx _ serial _ data rate/66, so that frequency switching is not needed, resources are saved, and the design complexity is reduced. The PCS receiving device PCS Receive and the PMA receiving device PMA Receive are in the same clock domain, namely, all modules in the receiving direction work in the same clock domain, and the clock frequency is the receiving serial data rx _ serial _ data rate/66, so that frequency switching is not needed, resources are saved, and the design complexity is reduced.

Further, when the PCS layer is generated by the PMA layer by using a clock and has a bit width of 66bit, the frequency of the transmitting side to the parallel clock PMA _ tclk is the transmitting serial data tx _ serial _ data rate/66, and the receiving side receives the serial data rx _ serial _ data rate/66 to the frequency of the parallel clock PMA _ rclk.

The data width of the interface inside the PCS layer and with the PMA layer is 66bit, so that the number of clocks inside the PCS layer is reduced, the working frequency and logic complexity inside the PCS layer are effectively reduced, the time sequence requirement of digital design inside the PCS layer is reduced, the design cost of a chip can be effectively reduced, and the performance and reliability of the chip are improved.

As shown in fig. 2, for generating a schematic diagram of the frequency of the sending-direction parallel clock pma _ tclk, a first initial frequency divider D10 is used for setting a proportional relationship between the sending serial data tx _ serial _ data (txp/n) and the phase-locked loop clock pll clock, and generating a high-speed serial clock s _ clk to the parallel-serial output PISO; and after frequency division is carried out by a first frequency divider D11 and a first frequency divider D12, a sending direction parallel clock pma _ tclk providing a PCS layer is obtained; and the transmission data tx _ data [65:0] outputs the transmission serial data tx _ serial _ data (txp/n) via the parallel serial output PISO. When the interface bit width is 66bit, set D11 to 11 and D12 to 3, i.e., generate the transmit direction parallel clock pma _ tclk at the frequency of the transmit serial data tx _ serial _ data rate/66.

As shown in fig. 3, for the frequency generation schematic diagram of the receiving direction clock pma _ rclk, a second initial divider D20 is used for setting the proportional relationship between the received serial data rx _ serial _ data (rxd) and the CDR recovery clock rec _ clk, and generating a high-speed serial clock rec _ sclk to the serial parallel output SIPO; and after frequency division is carried out by a second frequency divider D21 and a second frequency divider D22, a receiving direction parallel clock pma _ rclk providing a PCS layer is obtained; and receiving serial data rx _ serial _ data (rxd) outputting the received data rx _ data [65:0] via serial-to-parallel output SIPO. When the interface bit width is 66bit, set D21 to 11 and D22 to 3, i.e., generate the receive direction parallel clock pma _ rclk at the frequency of the receive serial data rx _ serial _ data rate/66.

The serdes framework of 64B/66B conversion provided by the embodiment of the invention configures the bit width of the interface data between the PCS layer and the PMA layer into 66bit, and the corresponding interface clock frequency is the tx _ serial _ data transmission rate/66, so that the internal clock frequency of the PCS layer is reduced, and the PCS/XLGIII interface rate is the same as the PCS/PMA interface rate due to the bit width of the PCS/XLGIII interface. The structure has the advantages that only one clock domain is arranged inside the whole PCS layer, a gear box module is omitted, resources are saved, and design complexity is reduced.

While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.

Claims (7)

1. A serdes architecture for 64B/66B conversion is characterized by comprising an XLGMII, a PCS layer and a PMA layer, and interface bit widths of the PCS layer and the PMA layer are configured to be 66 bits.

2. The serdes architecture for 64B/66B conversion, as set forth in claim 1, wherein said PCS layer comprises PCS transmitting means, said PCS transmitting means comprising a coding module and a scrambling module,

the encoding module is used for encoding the interface data of the XLGMII into 64B _66B block data;

the scrambling module is used for scrambling the 64B _66B block data.

3. The 64B/66B converted serdes architecture of claim 2, wherein the PMA layer comprises a PMA sending device.

4. A 64B/66B converted serdes architecture as claimed in claim 3, wherein said PCS transmit means and PMA transmit means are in the same clock domain.

5. The serdes architecture for 64B/66B conversion, as recited in claim 1, wherein the PCS layer comprises a PCS receiving device comprising a block synchronization module, a descrambling module, and a decoding module,

the block synchronization module is used for synchronously defining the received 64B _66B block data according to the block synchronization header information;

the descrambling module is used for descrambling the 64B _66B block data;

the decoding module is configured to decode the 64B _66B block data after descrambling and send the decoded 64B _66B block data to the XLGMII.

6. The 64B/66B converted serdes architecture of claim 5, wherein the PMA layer comprises a PMA receiving device.

7. A64B/66B converted serdes architecture as claimed in claim 6, wherein the PCS and PMA receiving devices are in the same clock domain.

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