CN102710240B - Signal processing apparatus, method, SERDES and processor - Google Patents
Signal processing apparatus, method, SERDES and processor Download PDFInfo
- Publication number
- CN102710240B CN102710240B CN201210058431.4A CN201210058431A CN102710240B CN 102710240 B CN102710240 B CN 102710240B CN 201210058431 A CN201210058431 A CN 201210058431A CN 102710240 B CN102710240 B CN 102710240B
- Authority
- CN
- China
- Prior art keywords
- signal
- parallel
- sampling
- road
- over
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Dc Digital Transmission (AREA)
- Information Transfer Systems (AREA)
Abstract
The present invention discloses a kind of signal processing method, device and SERDES and processor, relates to signal processing technology field.In this device, signal transmitting module comprises the over-sampling encoder be connected with clock generator, for receiving W road parallel input signal, carries out R times of over-sampling coding to W road parallel input signal; Signal receiving module comprises the decoder synthesizer be connected with clock generator, for decode to the parallel signal from deserializer and R doubly synthesizes to obtain W road parallel input signal.When the present invention completes SERDES function, can not the functional modules such as clock recovery circuitry being needed, because this simplify the functional module of SERDES processor or chip, making the realization of more small size become possibility.
Description
Technical field
The present invention relates to signal processing technology field, particularly relate to a kind of signal processing apparatus, method, SERDES and processor.
Background technology
Along with the continuous growth to information flow-rate demand, Traditional parallel interfacing becomes the bottleneck improving message transmission rate further.Serial communication technology SERDES is replacing Traditional parallel bus and is becoming the main flow of high-speed interface technology.
SERDES is the abbreviation of English SERializer (serializer)/DeSerializer (deserializer).It is a kind of time division multiplexing (TDM), the point-to-point communication technology, namely high-speed serial signals is converted at transmitting terminal multi-path low speed parallel signal, through transmission medium (optical cable or copper cash), finally again convert speed parallel signals at receiving terminal high-speed serial signals.This point-to-point serial communication technology makes full use of the channel capacity of transmission medium, the transmission channel needed for minimizing and device pin number, thus greatly reduces communications cost.
SERDES technology is applied to wide area network (WAN) communication the earliest, and present SERDES technology is applied to local area network (LAN) (LAN) communication equally.Along with developing rapidly of semiconductor technology, the performance and application of computer achieves rapid progress., Traditional parallel bussing technique---PCI does not but catch up with processor and improving of memory and becomes the bottleneck improving message transmission rate.For solving Computer I/O bottleneck, PCI Standard PC IExpress of new generation is proposed.PCIExpress is a kind of serial bidirectional communication technology based on SERDES, supporting chip and chip and the communication between backboard and backboard.The rise of Internet and information technology facilitates crossing of computer and the communication technology, and SERDES serial communication technology progressively replaces Traditional parallel bus this imbody crossed just.
HSSI High-Speed Serial Interface based on SERDES adopts following measures to breach the data transmission bottle neck of Traditional parallel I/O interface: one is adopt differential signal transmission to replace single-ended signal transmission, thus enhances antinoise, antijamming capability; Two is adopt clock and data recovery technology to replace transmitting data and clock simultaneously, thus solves the signal clock offset problem of restricting data transmission rate.
As shown in Figure 1, a typical SERDES transceiver is made up of sendaisle and receive path: encoder 13, serializer 14, transmitter 15 and clock generation circuit 11 form sendaisle; Receiver 16, deserializer 17, decoder 18 and clock recovery circuitry 12 form receive path.Encoder 13 and decoder 18 complete coding and decoding function, and wherein 8B/10B, 64B/66B and irregular coding (scrambling) are the most frequently used encoding schemes.Transmitter 15 and receiver 16 complete transmission and the reception of differential signal, and wherein LVDS and CML is two kinds of the most frequently used differential signal standards.Serializer 14 and deserializer 17 are responsible for from parallel-to-serial and from serial-to-parallel conversion.Serializer needs clock generation circuit 11, and clock generating circuit is realized by phase-locked loop (PLL) usually.Deserializer 17 needs clock and data recovery circuit (CDR) 12, and clock recovery circuitry 12 is also realized by phase-locked loop usually, but has multiple way of realization as phase place transplanting, superfluous sampling etc.As a rule, clock generating circuit and clock recovery circuitry are the required assembly of SERDES for signal transacting.
SERDES general cost of the prior art is higher, volume ratio is comparatively large, more difficult in equipment miniaturizations such as daily optical fiber transmission lines.
Summary of the invention
The technical problem that the present invention will solve is to provide a kind of signal processing apparatus and method, has the advantage that cost is low.
According to an aspect of the present invention, a kind of signal processing apparatus is provided, comprises: clock generator, for generation of clock signal; Signal transmitting module, described signal transmitting module comprises: the over-sampling encoder be connected with described clock generator, for receiving W road parallel input signal, R times of over-sampling coding is carried out to W road parallel input signal, parallel signal after output encoder, wherein, W, R be more than or equal to 2 integer; The serializer be connected with described clock generator, for receiving the parallel signal after from the described coding of described over-sampling encoder, is converted to serial signal by the parallel signal after described coding; Transmitter, for receiving the serial signal from described serializer, exports difference serial output signal; And/or signal receiving module, described signal receiving module comprises: receiver, for receiving differential serial input signal, exports serial input signals; The deserializer be connected with described clock generator, for the acquisition parallel signal that unstrings to the serial input signals from described receiver; The decoder synthesizer be connected with described clock generator, for decode to the parallel signal from described deserializer and R doubly synthesizes to obtain W road parallel input signal, wherein, W, R be more than or equal to 2 integer.
Alternatively, clock generator has the clock frequency of N × W × R, and wherein, N is the data rate of W road parallel input signal.
Alternatively, over-sampling encoder comprises: over-sampling unit, for receiving W road parallel input signal, carries out R times of over-sampling to W road parallel input signal, exports R × W road parallel signal of over-sampling; Coding unit, for receiving the R × W road parallel signal from described over-sampling unit, exports after described R × W road parallel signal coding.
Alternatively, decoder synthesizer comprises: decoding unit, for receiving the parallel signal from described deserializer, decodes to the parallel signal from described deserializer, obtains decoded R × W road parallel signal; Synthesis unit, carries out R for the R × W road parallel signal received from described decoding unit and doubly synthesizes to obtain W road parallel input signal.
Alternatively, over-sampling encoder comprises: single ended input buffering area, for W road parallel input signal described in buffer memory; Parallel input register, for synchronous and receive W bit of described single ended input buffering area; Oversampler, for carrying out R times of over-sampling to W bit of described parallel input register, exports W × R bit parallel signal; Encoder, encodes for the W × R bit parallel signal exported described oversampler, the parallel signal after output encoder.
Alternatively, decoder synthesizer comprises: decoder, decodes for the parallel signal that receives from deserializer, exports decoded W × R bit parallel signal; Sampling synthesizer, for receiving W × R bit parallel signal that described decoder exports, carrying out synthesis and exporting W bit parallel signal; Parallel output register, for receiving the W bit parallel signal that described sampling synthesizer exports, W bit parallel signal described in synchronism output; W Single-end output buffering area, for the W bit parallel signal that parallel output register described in buffer memory exports.
Alternatively, the low speed signal of parallel input signal to be speed be kHz; And/or described 3≤R≤10; And/or parallel signal does not comprise clock signal after described coding.
According to a further aspect in the invention, a kind of microprocessor is provided, comprises said signal processing device.
According to a further aspect in the invention, a kind of SERDES is provided, comprises said signal processing device.
According to another aspect of the invention, a kind of signal processing method is provided, comprises: receive W road parallel input signal, W be more than or equal to 2 integer; R times of over-sampling coding is carried out to W road parallel input signal, parallel signal after output encoder, wherein R be more than or equal to 2 integer; Parallel signal after coding is converted to serial signal; Difference serial output signal is exported according to serial signal; And/or export serial input signals according to the differential serial input signal received; Serial input signals is unstringed acquisition parallel signal; Parallel signal to be decoded and R doubly synthesizes to obtain W road parallel input signal, wherein, W, R be more than or equal to 2 integer.
Alternatively, after carrying out R times of over-sampling coding output encoder to W road parallel input signal, parallel signal comprises: receive W road parallel input signal, carry out R times of over-sampling to W road parallel input signal, export R × W road parallel signal of over-sampling; Export after R × W road parallel signal coding.
Alternatively, parallel signal to be decoded and R doubly synthesizes to obtain W road parallel input signal and comprises: parallel signal is decoded, obtains decoded R × W road parallel signal; Carry out R to R × W road parallel signal doubly to synthesize to obtain W road parallel input signal.
Alternatively, the low speed signal of parallel input signal to be speed be kHz; And/or described 3≤R≤10;
Alternatively, after coding, parallel signal does not comprise clock signal.
Signal processing method provided by the invention, device, SERDES and microprocessor, realize signaling protein14-3-3 by the technological means of over-sampling, do not need complicated clock recovery circuitry, have the advantage that cost is low.
Accompanying drawing explanation
Fig. 1 illustrates the structure chart of the SERDES transceiver of prior art;
Fig. 2 illustrates the structure chart of an embodiment of signal processing apparatus of the present invention; Wherein, Fig. 2 A illustrates the structure chart of signal transmitting module; Fig. 2 B illustrates the structure chart of signal receiving module;
Fig. 3 illustrates the structure chart of another embodiment of signal processing apparatus of the present invention;
Fig. 4 illustrates the structure chart of another embodiment of signal processing apparatus of the present invention;
Fig. 5 illustrates the diagram of the example of unidirectional, two-way signaling of the present invention;
Fig. 6 illustrates the flow chart of an embodiment of signaling method of the present invention;
Fig. 7 illustrates the flow chart of an embodiment of signal acceptance method of the present invention.
Embodiment
With reference to the accompanying drawings the present invention is described more fully, exemplary embodiment of the present invention is wherein described.
Fig. 2 A illustrates the theory diagram of an embodiment of apparatus for transmitting signal of the present invention.In fig. 2, transmitting terminal synchronously receives parallel signal afterwards, samples to parallel signal, then based on tailor-made algorithm, parallel signal is converted into serial signal, sends.If transmitting terminal also supports Received signal strength, then unstring based on the serial signal of tailor-made algorithm by reception, export as parallel signal after synchronous.
Fig. 2 B illustrates the theory diagram of an embodiment of signal receiver of the present invention.In fig. 2b, serial input is converted into parallel output based on tailor-made algorithm by receiving terminal, is exported by parallel signal after synchronous.If transmitting terminal is also supported to send, then receive parallel signal after synchronous, parallel signal is sampled, then based on tailor-made algorithm, parallel signal is converted into serial signal, send.
When embodiments of the invention complete SERDES function, can not the functional modules such as clock recovery circuitry being needed, because this simplify the functional module of SERDES processor or chip, making the realization of more small size become possibility.
Fig. 2 A illustrates the structure chart of an embodiment of signal processing apparatus of the present invention, and this signal processing apparatus is embodied in signal transmitting module.As shown in Figure 2 A, this signal transmitting module comprises: the tranmitting data register generator 210 of clocking, the over-sampling encoder 211 be connected with tranmitting data register generator 210 respectively and serializer 212, and transmitter 213.Over-sampling encoder 211 receives W road parallel input signal, carries out R times of over-sampling (OverSampling) coding, the parallel signal after output encoder to W road parallel input signal, wherein, W, R be more than or equal to 2 integer.Serializer 212 receives parallel signal after the coding from over-sampling encoder 211, and parallel signal after coding is converted to serial signal; Transmitter 213 receives the serial signal from serializer 212, exports difference serial output signal.Such as, each signal repeated sampling in over-sampling encoder 211 pairs of W road parallel input signal R time, and sample frequency is promoted to original R doubly, like this, each signal in the input signal of W road is sent R time by generator.In one embodiment, R be more than or equal to 3 and be less than or equal to 10 natural number.
Fig. 2 B illustrates the structure chart of an embodiment of signal processing apparatus of the present invention, and this signal processing apparatus is embodied in signal receiving module.As shown in Figure 2 B, this signal receiving module comprises: the receive clock generator 220 of clocking, receiver 223, and the deserializer 222 be connected with receive clock generator 220 respectively and decoder synthesizer 221.Wherein, receiver 223 receives differential serial input signal, exports serial input signals; Deserializer 222 to unstring acquisition parallel signal to the serial input signals from receiver 223; Decoder synthesizer 221 is decoded to the parallel signal from deserializer 222 and R doubly synthesizes to obtain W road parallel input signal, wherein, W, R be more than or equal to 2 integer.In one embodiment, R be more than or equal to 3 and be less than or equal to 10 natural number.
Those skilled in the art is to be understood that, signal processing apparatus generally includes signal transmitting module as during transmitting terminal, generally include signal receiving module as during receiving terminal, not only can comprise signal transmitting module and signal receiving module as transmitting terminal but also as during receiving terminal; As receiving terminal, the frequency of the receive clock generator of signal receiving module should be consistent with the frequency of the tranmitting data register generator of transmitting terminal.When signal receiving module and signal transmitting module are positioned at same equipment, tranmitting data register generator can be identical with the frequency of receive clock generator, even shares same clock generator, also can adopt different clock generators respectively.
Complicated clock recovery circuitry is that in prior art, SERDES, for the required assembly of signal transacting, not only increases cost, and makes signal handling equipment volume ratio comparatively large, and miniaturization is more difficult.In above-described embodiment, as long as transmitting terminal and receiving terminal adopt the clock generator of same frequency, by adopting over-sampling at transmitting terminal, adopting the technological means of over-sampling synthesis at receiving terminal, even if there is certain clock asynchronous, also original signal can correctly be recovered, thus do not need complicated clock recovery circuitry, reduce cost; The SERDES equipment that volume is very little can be made, be convenient to the miniaturization of the daily equipment such as HDMI transmission line.
Fig. 3 illustrates the structure chart of another embodiment of signal processing apparatus of the present invention.As shown in Figure 3, this signal processing apparatus comprises clock generator 300, the over-sampling unit 3111 that signal transmitting module comprises, coding unit 3112, serializer 312 and transmitter 313, the receiver 323 that signal receiving module comprises, deserializer 322, decoding unit 3212 and synthesis unit 3211.Serializer 312, transmitter 313, receiver 323, deserializer 322 can see the descriptions of assembly corresponding in Fig. 2, for being not described in detail at this for purpose of brevity.Over-sampling unit 3111 and coding unit 3112 correspond to over-sampling encoder, over-sampling unit 3111, receive W road parallel input signal, carry out R times of over-sampling to W road parallel input signal, export R × W road parallel signal of over-sampling; Coding unit 3112 receives the R × W road parallel signal from over-sampling unit 3111, exports after R × W road parallel signal coding.Decoding unit 3212 and synthesis unit 3211 correspond to decoder synthesizer, and decoding unit 3212 receives the parallel signal from deserializer 322, decodes to the parallel signal from deserializer 322, obtains decoded R × W road parallel signal; The synthesis unit 3211 R × W road parallel signal received from decoding unit 3212 carries out R and doubly synthesizes to obtain W road parallel input signal.
Fig. 4 illustrates the structure chart of another embodiment of signal processing apparatus of the present invention.As shown in Figure 4, this signal processing apparatus comprises clock generator 400, the single ended input buffering area (SingleEndedInputBuffer) 412 that signal transmitting module comprises, parallel input register (ParallelInputRegister) 413, oversampler 411, encoder 414, serializer 415 and transmitter 416, the receiver 426 that signal receiving module comprises, deserializer 425, decoder 424, sampling synthesizer 421, parallel output register 423, Single-end output buffering area 422.W single ended input buffering area 412, corresponding buffer memory W road parallel input signal, namely riches all the way send the input signal of bus for the corresponding buffer memory in each single ended input buffering area; W parallel-by-bit input register 413, synchronous and correspondence receives W bit of single ended input buffering area 412, i.e. correspondence single ended input buffering area of parallel input register 413; Oversampler 411, carries out R times of over-sampling to W bit of parallel input register 413, exports W × R bit parallel signal to encoder 414; W × R bit parallel signal that encoder 414 pairs of oversampler 411 export is encoded, parallel signal after output encoder is to serializer 415, serial bit stream is generated after serializer 415 carries out parallel-serial conversion, send to transmitter 416, serial bit stream exports as differential serial signals by transmitter 416, is sent to receiving terminal through transmission medium.Receiver 426 receives the differential serial input signal from transmitting terminal, sends to deserializer 425 after being converted into serial bit stream, and deserializer 425 pairs of serial bit streams unstring, and exports parallel signal; Decoder 424 is decoded to the parallel signal from deserializer 425, export W × R bit parallel signal to sampling synthesizer 421, sampling synthesizer 421 pairs of W × R bit parallel signal synthesize, export W bit parallel signal to W parallel-by-bit output register 423, parallel output register 423 receives the W bit parallel signal that sampling synthesizer 421 exports, export W bit parallel signal to W Single-end output buffering area 422, the W bit parallel signal that Single-end output buffering area 422 buffer memory parallel output register 423 exports, synchronism output is to reception bus.
It may be noted that, shown in Figure 4 16,8B/10B, 20, the symbol such as 10B/8B is only used for explanation, parallel input signal can be any multichannel, encoder/decoder also can adopt other coding/decoding to realize, and with coding realize and parallel input signal corresponding, the output of encoder and the input figure place of decoder also change thereupon.
The handling process of whole device is introduced below for N=15 (i.e. 16 road TX buses).First, the parallel input signal correspondence of 16 road TX buses is input to 16 single ended input buffering areas 412, the signal of input is latched and uses internal system time clock synchronous, from 16 single ended input buffering areas 412, get 1 bit (totally 16 bits) is respectively input to 16 parallel input registers 413 at every turn, 16 bits in parallel register 413 are through R times of over-sampling of oversampler 411, form R × 16 bit, be input to 8B/10B encoder 414, encode through encoder 414 and form R × 20 bit, output to serializer 415, the parallel signal of R × 20 bit is converted to serial bit stream by serializer 415, output to transmitter 416, differential serial signals R is generated by transmitter 416, N outputs to transmission medium.Oversampler 411, encoder 414 and serializer 415 all carry out work under the control of the bit rate clock of clock generator 400 generation.
At receiving terminal, receiver 426 receives differential serial input signal P, N, by receiver 426, differential serial signals is converted to serial bit stream and sends to deserializer 425, serial bit stream is converted to the parallel signal of R × 20 bit by deserializer 425, send to decoder 424, the parallel signal decoding of decoder 424 pairs of R × 20 bits obtains the parallel signal of R × 16 bit, send to sampling synthesizer 421, sampling synthesizer 421 pairs of R × 16 bits synthesize, obtain the parallel signal of 16 bits, correspondence outputs to 16 parallel output registers 423, 16 bit correspondences are outputted to 16 Single-end output buffering areas 422 by parallel output register 423, correspond respectively to RX bus 0-15 to export.Sampling synthesizer 421, decoder 424 and deserializer 425 all carry out work under the control of the bit rate clock of clock generator 400 generation.
Illustrate the operation of oversampler 411 and sampling synthesizer 421 below.For oversampler 411,16 bits such as received are 0110011100110010, then oversampler 411 is by 16 bit repeated samplings R time, such as, when R=3, generate 011001110011001001100111001100100110011100110010.For sampling synthesizer 421, when R=3, be added respectively if the signal received is each in the parallel signal of 011001110011001001100111001100100110011100110010, Ze Jiang 16 road, then divided by repeated sampling multiple R, 0110011100110010 is obtained; If wherein mistake appears in a frame synchronization, such as, the signal received is XXXXXXXXXXXXXXXX01100111001100100110011100110010, X represents 0 or 1, uncertain, because two frames below do not occur mistake, still can 0110011100110010 be recovered.
Signal processing apparatus shown in Fig. 2-Fig. 4, can provide separately as SERDES equipment, also can as the Implement of Function Module of microprocessor or the various network equipment, messaging device.
In actual applications, signal receiving device and sender unit not only can be positioned on same equipment, and some passages between them can be changed as required between sendaisle/receive path.Fig. 5 illustrates the diagram of the example of unidirectional, two-way signaling of the present invention.A, B, C, D represent each road signal.In following table, 0 and 1 represents low-voltage and high voltage respectively.A and D is one way signal, and B is two-way signaling.C, for object of encoding, represents the state of B.In input (Input) situation, mean that B is " owner " and " spokesman ", (Output) situation of output means that B is " subordinate " and " attentive listener ".This schematic diagram illustrates a signaling channel processing scheme.Can have more than one such signal at HDMI port, chip will support the signal that process is all.
Table 1
Table 2
Table 3
Above-mentioned table lists the logical condition of the state determining each signal.A and D respectively from whereabouts SERDES module, SERDES module principle is summarized as follows:
The signal of a bit sends three times (or more than three times) by transmitting terminal, if receiving terminal is sampled, at it by bit good for recovery 3 to the signal received with good timing.Due to clock drift, timing may be lost, and the data recovered may lose a bit, and (transmitting terminal and receiving terminal need use the clock of same frequency and have certain accuracy, such as +/-200ppmm), but, the signal of original sender transmission still correctly can be gone back by two bits recovered.Also can work more than the schemes of three times, the reduction accuracy of data can be increased, certainly may reduce data transfer rate.
If use optical fiber (single-ended drive laser) as medium, then can not need differential buffer district in the design.And for copper cash, differential signal is the better mode overcoming noise problem.
In prior art, 8/10B encoder is used for minimizing conversion and balance DC level.This encoder can not be needed in an embodiment of the present invention to save space and expense.
In the prior art, " PLL/ clock recovery ", " encoder ", " differential buffer district " are the key components making its work.In some embodiments of the invention, these modules are no longer required.In addition, Fig. 4 illustrates that input and output buffering area is physical separation.But in the system of some embodiments of the present invention, some in these input and output are identical signal pins, the input of these signal pins or output state by logic criterion and the setting of other conditions or can identify, input and output buffering area does not need physical separation.This is also one of hardware difference between existing SERDES and SERDES of the present invention design.
Fig. 6 illustrates the flow chart of an embodiment of signaling method of the present invention.
As shown in Figure 6, in step 602, receive W road parallel input signal, W be more than or equal to 2 integer.Based on reference clock synchronously and receive multidiameter delay input signal.
Step 604, carries out R times of over-sampling coding to W road parallel input signal, parallel signal after output encoder, R be more than or equal to 2 integer.Receive W road parallel input signal, R times of over-sampling is carried out to W road parallel input signal, export R × W road parallel signal of over-sampling.R × W road parallel signal is encoded, the parallel signal after output encoder.
Step 606, is converted to serial signal by the parallel signal after coding;
Step 608, exports difference serial output signal according to serial signal;
Fig. 7 illustrates the flow chart of an embodiment of signal acceptance method of the present invention.
As shown in Figure 7, in step 702, receive the differential serial input signal of over-sampling, export serial input signals according to the differential serial input signal received.
In step 704, to the acquisition parallel signal that unstrings to serial input signals.
In step 706, parallel signal to be decoded and R doubly synthesizes to obtain W road parallel input signal.Parallel signal is decoded, obtains decoded R × W road parallel signal; Carry out R to R × W road parallel signal doubly to synthesize to obtain W road parallel input signal.
In one embodiment, the low speed signal of parallel input signal to be speed be kHz scope, 3≤R≤10.
Method and apparatus of the present invention requires that transmitting terminal is consistent with the clock frequency of receiving terminal, can allow that the clock of transmitting terminal and receiving terminal has certain skew, not need clock recovery, and after coding, parallel signal does not comprise clock signal.
Can see the description of device embodiment in Fig. 2-5 for method, for for purpose of brevity, be not described in detail at this.
Description of the invention provides in order to example with for the purpose of describing, and is not exhaustively or limit the invention to disclosed form.Many modifications and variations are obvious for the ordinary skill in the art.Selecting and describing embodiment is in order to principle of the present invention and practical application are better described, and enables those of ordinary skill in the art understand the present invention thus design the various embodiments with various amendment being suitable for special-purpose.
Claims (14)
1. a signal processing apparatus, is characterized in that, comprising:
Clock generator, for generation of clock signal;
Signal transmitting module, described signal transmitting module comprises:
The over-sampling encoder be connected with described clock generator, for receiving W road parallel input signal, carries out R times of over-sampling coding to W road parallel input signal, parallel signal after output encoder, wherein, W, R be more than or equal to 2 integer;
The serializer be connected with described clock generator, for receiving the parallel signal after from the described coding of described over-sampling encoder, is converted to serial signal by the parallel signal after described coding;
Transmitter, for receiving the serial signal from described serializer, exports difference serial output signal;
And/or
Signal receiving module, described signal receiving module comprises:
Receiver, for receiving differential serial input signal, exports serial input signals;
The deserializer be connected with described clock generator, for the acquisition parallel signal that unstrings to the serial input signals from described receiver;
The decoder synthesizer be connected with described clock generator, for decode to the parallel signal from described deserializer and R doubly synthesizes to obtain W road parallel input signal, wherein, W, R be more than or equal to 2 integer.
2. device according to claim 1, is characterized in that, described clock generator has the clock frequency of N × W × R, and wherein, N is the data rate of W road parallel input signal.
3. device according to claim 1, is characterized in that, described over-sampling encoder comprises:
Over-sampling unit, for receiving W road parallel input signal, carries out R times of over-sampling to W road parallel input signal, exports R × W road parallel signal of over-sampling;
Coding unit, for receiving the R × W road parallel signal from described over-sampling unit, exports after described R × W road parallel signal coding.
4. device according to claim 1, is characterized in that, described decoder synthesizer comprises:
Decoding unit, for receiving the parallel signal from described deserializer, decodes to the parallel signal from described deserializer, obtains decoded R × W road parallel signal;
Synthesis unit, carries out R for the R × W road parallel signal received from described decoding unit and doubly synthesizes to obtain W road parallel input signal.
5. device according to claim 1, is characterized in that, described over-sampling encoder comprises:
Single ended input buffering area, for W road parallel input signal described in buffer memory;
Parallel input register, for synchronous and receive W bit of described single ended input buffering area;
Oversampler, for carrying out R times of over-sampling to W bit of described parallel input register, exports W × R bit parallel signal;
Encoder, encodes for the W × R bit parallel signal exported described oversampler, the parallel signal after output encoder.
6. device according to claim 1, is characterized in that, described decoder synthesizer comprises:
Decoder, decodes for the parallel signal that receives from deserializer, exports decoded W × R bit parallel signal;
Sampling synthesizer, for receiving W × R bit parallel signal that described decoder exports, carrying out synthesis and exporting W bit parallel signal;
Parallel output register, for receiving the W bit parallel signal that described sampling synthesizer exports, W bit parallel signal described in synchronism output;
W Single-end output buffering area, for the W bit parallel signal that parallel output register described in buffer memory exports.
7. device according to claim 1, is characterized in that, the low speed signal of described parallel input signal to be speed be kHz;
And/or
Described 3≤R≤10;
And/or
After described coding, parallel signal does not comprise clock signal.
8. a microprocessor, is characterized in that, comprises as the signal processing apparatus in claim 1-7 as described in any one.
9. a SERDES, is characterized in that, comprises as the signal processing apparatus in claim 1-7 as described in any one.
10. a signal processing method, is characterized in that, comprising:
The clock signal that receive clock generator produces;
Receive W road parallel input signal, W be more than or equal to 2 integer;
R times of over-sampling coding is carried out to W road parallel input signal, parallel signal after output encoder, wherein R be more than or equal to 2 integer;
Parallel signal after coding is converted to serial signal;
Difference serial output signal is exported according to serial signal;
And/or
The clock signal that receive clock generator produces;
Serial input signals is exported according to the differential serial input signal received;
Serial input signals is unstringed acquisition parallel signal;
Parallel signal to be decoded and R doubly synthesizes to obtain W road parallel input signal, wherein, W, R be more than or equal to 2 integer.
11. methods according to claim 10, is characterized in that, described R times of over-sampling coding output encoder is carried out to W road parallel input signal after parallel signal comprise:
Receive W road parallel input signal, R times of over-sampling is carried out to W road parallel input signal, export R × W road parallel signal of over-sampling;
Export after R × W road parallel signal coding.
12. methods according to claim 10, is characterized in that, describedly to decode to parallel signal and R doubly synthesizes to obtain W road parallel input signal and comprises:
Parallel signal is decoded, obtains decoded R × W road parallel signal;
Carry out R to R × W road parallel signal doubly to synthesize to obtain W road parallel input signal.
13. methods according to claim 10, is characterized in that, the low speed signal of described parallel input signal to be speed be kHz;
And/or
Described 3≤R≤10.
14. methods according to claim 10, is characterized in that, after described coding, parallel signal does not comprise clock signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210058431.4A CN102710240B (en) | 2011-03-08 | 2012-03-08 | Signal processing apparatus, method, SERDES and processor |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100545781 | 2011-03-08 | ||
| CN201110054578 | 2011-03-08 | ||
| CN201110054578.1 | 2011-03-08 | ||
| CN201210058431.4A CN102710240B (en) | 2011-03-08 | 2012-03-08 | Signal processing apparatus, method, SERDES and processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102710240A CN102710240A (en) | 2012-10-03 |
| CN102710240B true CN102710240B (en) | 2016-03-02 |
Family
ID=46797505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210058431.4A Active CN102710240B (en) | 2011-03-08 | 2012-03-08 | Signal processing apparatus, method, SERDES and processor |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102710240B (en) |
| WO (1) | WO2012119561A1 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103401551B (en) * | 2013-08-23 | 2016-03-30 | 中国人民解放军国防科学技术大学 | A kind of method of sampling of SerDes technology high speed serial signal and device |
| US9378174B2 (en) * | 2013-11-04 | 2016-06-28 | Xilinx, Inc. | SERDES receiver oversampling rate |
| CN107070595A (en) * | 2017-02-20 | 2017-08-18 | 郑州云海信息技术有限公司 | A kind of SERDES data rates Adaptable System and SERDES |
| CN107481674B (en) * | 2017-08-14 | 2020-04-28 | 深圳市华星光电半导体显示技术有限公司 | Display device |
| CN112368956B (en) * | 2018-07-11 | 2022-07-22 | 华为技术有限公司 | Apparatus, method and system for generating a signal |
| CN111082846B (en) * | 2019-11-14 | 2022-03-11 | 天津融汇微电子技术有限公司 | SERDES-based one-to-four repeater using method |
| CN112559427B (en) * | 2020-12-18 | 2023-11-28 | 深圳市紫光同创电子有限公司 | Lvds pairs of receiving devices and Lvds pairs of transmitting devices |
| CN115529087A (en) * | 2021-06-25 | 2022-12-27 | 科大国盾量子技术股份有限公司 | Device and method for extracting signal light position information |
| CN114691558B (en) * | 2021-10-20 | 2023-06-20 | 澜起电子科技(上海)有限公司 | Low-delay retimer and delay control method |
| CN114371822B (en) * | 2021-12-13 | 2023-12-01 | 青岛信芯微电子科技股份有限公司 | Data transmission device, chip, display device and data transmission method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1791120A (en) * | 2004-12-13 | 2006-06-21 | 奥特拉股份有限公司 | Techniques for optimizing design of a hard intellectual property block for data transmission |
| CN101669305A (en) * | 2007-02-28 | 2010-03-10 | 菲尼萨公司 | Multi-mode integrated circuit for use in optoelectronic devices |
| CN101706763A (en) * | 2009-11-20 | 2010-05-12 | 中兴通讯股份有限公司 | Method and device for serialization and deserialization |
| CN101753288A (en) * | 2009-12-11 | 2010-06-23 | 西安邮电学院 | Clock data recovery and serial-parallel conversion circuit based on over sampling |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8582705B2 (en) * | 2007-12-10 | 2013-11-12 | Ciena Corporation | Serializer-deserializer circuit with multi-format and multi-data rate capability |
| US9559881B2 (en) * | 2007-12-21 | 2017-01-31 | Altera Corporation | Transceiver system with reduced latency uncertainty |
-
2012
- 2012-03-08 WO PCT/CN2012/072094 patent/WO2012119561A1/en active Application Filing
- 2012-03-08 CN CN201210058431.4A patent/CN102710240B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1791120A (en) * | 2004-12-13 | 2006-06-21 | 奥特拉股份有限公司 | Techniques for optimizing design of a hard intellectual property block for data transmission |
| CN101669305A (en) * | 2007-02-28 | 2010-03-10 | 菲尼萨公司 | Multi-mode integrated circuit for use in optoelectronic devices |
| CN101706763A (en) * | 2009-11-20 | 2010-05-12 | 中兴通讯股份有限公司 | Method and device for serialization and deserialization |
| CN101753288A (en) * | 2009-12-11 | 2010-06-23 | 西安邮电学院 | Clock data recovery and serial-parallel conversion circuit based on over sampling |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2012119561A1 (en) | 2012-09-13 |
| CN102710240A (en) | 2012-10-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102710240B (en) | Signal processing apparatus, method, SERDES and processor | |
| CN102510328B (en) | High-speed parallel interface circuit | |
| EP0853852B1 (en) | Block coding for digital video transmission | |
| US6839862B2 (en) | Parallel data communication having skew intolerant data groups | |
| US8446978B2 (en) | Communication system | |
| JP4783245B2 (en) | Transceiver, transmitter, and receiver | |
| CA3161433A1 (en) | Transvascular diaphragm pacing systems and methods of use | |
| US10103830B2 (en) | Latency-optimized physical coding sublayer | |
| CN102340316A (en) | FPGA (Field Programmable Gate Array)-based micro-space oversampling direct-current balance serial deserializer | |
| EP1397895A2 (en) | Parallel data communication with multiple synchronisation codes | |
| CN102523436B (en) | Transmission terminal, receiving terminal, multi-channel video optical fiber transmission system and multi-channel video optical fiber transmission method | |
| EP3114792B1 (en) | Clock recovery circuit for multiple wire data signals | |
| WO2003030479A1 (en) | Parallel data communication having skew intolerant data groups and data validity indicator | |
| EP4125230B1 (en) | Low latency network device and method for treating received serial data | |
| JP2009109488A (en) | Serial data processor and processing method | |
| KR20180065119A (en) | Receiver for data communication | |
| JP3745229B2 (en) | Communication system including low-rate parallel electronic circuit with corrected skew and related method | |
| CN112543158A (en) | Serdes architecture for 64B/66B conversion | |
| CN100440773C (en) | Phase inserted transmit-receive circuit and its transmit-receive method | |
| CN116208173A (en) | Parallelization decoding device and method under high-speed serial interface clock-free line application | |
| CN101364960B (en) | High-speed differential interface | |
| CN111475447B (en) | High-speed serial transmission device based on LVDS and data transmission method | |
| CN104717440A (en) | LED transmitting card cascade interface | |
| Stojčev et al. | On-and Off-chip Signaling and Synchronization Methods in Electrical Interconnects | |
| CN110995390B (en) | Method for transparent transmission of SDH bus data based on FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C53 | Correction of patent for invention or patent application | ||
| CB02 | Change of applicant information |
Address after: Hangzhou City, Zhejiang province Xihu District 310024 Tong Street Ge Ya Zhuang No. 181 Applicant after: Zhejiang Rainbow Fish Communication Technology Co., Ltd. Address before: 310024, Hangzhou, Zhejiang province Xihu District transferred to Tong Street, Long Wu Industrial Zone No. 38 Applicant before: Zhejiang Rainbow Fish Communication Technology Co., Ltd. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 310024 Zhejiang province Hangzhou city Xihu District turn Tong Street Ge Ya Zhuang 181 Patentee after: Zhejiang Rainbow Fish Technology Co., Ltd. Address before: 310024 Zhejiang province Hangzhou city Xihu District turn Tong Street Ge Ya Zhuang 181 Patentee before: Zhejiang Rainbow Fish Communication Technology Co., Ltd. |
|
| CP01 | Change in the name or title of a patent holder |