CN100440773C

CN100440773C - Phase inserted transmit-receive circuit and its transmit-receive method

Info

Publication number: CN100440773C
Application number: CNB2006100767625A
Authority: CN
Inventors: 林小琪
Original assignee: Via Technologies Inc
Current assignee: Via Technologies Inc
Priority date: 2006-04-18
Filing date: 2006-04-18
Publication date: 2008-12-03
Anticipated expiration: 2026-04-18
Also published as: CN1832361A

Abstract

The present invention relates to a receiving-sending circuit which is used for sending out a data output signal and receiving a data input signal. The receiving-sending circuit comprises a phase locking module, a sending module and a receiving module, wherein the phase locking module is used for generating at least one clock signal which has the same frequency and different phases; the sending module is electrically connected with the phase locking module and is used for sending out the data output signal according to the clock signal. Besides, the receiving module is electrically connected with the phase locking module and is used for receiving the data input signal and restoring the data input signal according to the clock signal.

Description

Phase interpolation transmission circuit and receiving/transmission method thereof

Technical field

The invention relates to a kind of transmission circuit, especially in regard to the transmission circuit of a kind of sequence transmission system.

Background technology

Because the progress of communication science and technology, the transmission speed of sequence transmission significantly promotes, and is applied to fields such as wireless telecommunications or computer system.

As shown in Figure 1, the transmission circuit of a sequence transmission (transceiver) 1 comprise an encoder 11, incorporate into go here and there out transducer (parallel-in-serial-output converter) 12, one phase-locked loop (Phase Locked Loop) 14, one transmitter 13, a receiver 18, a clock data recoverer (Clock Data Recovery) 15, seals in and go out transducer (serial-in-parallel-output converter) 17 and one decoder 16.

Encoder 11 with a data D1 encode (as 8B/10B or 64B/66B) become data D2, phase-locked loop 14 produces a clock CLK, incorporate into go here and there out the data D2 of transducer 12 after will encoding according to clock CLK by and column signal transitions be sequence signal D3, transmitter 13 sends the data D3 after the conversion.

Receiver 18 receives a data D4, owing to do not have transmission clock in the lump during transfer of data, therefore, clock data restorer 15 must be in data D4 clock and the data of restore data D4, seal in and go out transducer 17 data D4 is transferred to and column signal D5 by sequence signal, decoder 16 is decoded as data D6 with data D5, at last data D6 is delivered to other hierarchy circuit and handles, for example: datalink layer connection.If transceiver module transmits data with much channel communication, the receiving terminal of each passage also needs clock and the data of clock data restorer to recover each passage separately.

Yet, transceiver module comprises two clock generating elements (phase-locked loop 14 and clock data restorer 15), the clock generating element occupies higher cost when design is manufactured, when particularly the clock generating element of high frequency or multichannel transmit, if can reduce the cost that the quantity of clock generating element in the transceiver module can reduce transceiver module.

Therefore, how to provide a kind of transmission circuit, to reduce the usage quantity of clock generating element in the transmission circuit, with the framework of simplification transmission circuit, and then the cost of minimizing transmission circuit, be that present industry needs most one of problem of attention.

Summary of the invention

Because above-mentioned problem the invention provides a kind of transmission circuit that can reduce the clock generating element.

Transmission circuit of the present invention is in order to send a data output signal and to receive a data input signal, and this transmission circuit comprises a phase-locked module, a sending module and a receiver module.Wherein, phase-locked module is in order to produce identical but the clock signal that phase place is different of at least one frequency, sending module and phase-locked module electrically connect, send data output signal in order to the foundation clock signal, receiver module then electrically connects with phase-locked module, in order to the reception data input signal, and according to the recovering clock signals data input signal.

In the transmission circuit of the present invention, sending module and receiver module are shared same group of phase-locked module sending respectively or restore data, with known technology by contrast, the quantity required of phase-locked module can reduce in the transmission circuit, with the framework of simplification transmission circuit, and then the cost of reduction transmission circuit.

Description of drawings

Fig. 1 is for showing a block diagram of known transmission circuit;

Fig. 2 is a block diagram of the transmission circuit of the demonstration embodiment of the invention;

Fig. 3 is another block diagram of the transmission circuit of the demonstration embodiment of the invention;

Fig. 4 is a schematic diagram of clock signal in the transmission circuit that shows the embodiment of the invention;

Fig. 5 is another schematic diagram of clock signal in the transmission circuit that shows the embodiment of the invention;

Fig. 6 is applied to a block diagram of multichannel transmission for the transmission circuit that shows the embodiment of the invention; And

Fig. 7 is a flow chart of the method for the transmission of the transmission circuit that shows the embodiment of the invention and reception.

The element numbers explanation:

1 transmission circuit

11 encoders

12 incorporate into and go here and there out circuit

13 transmitters

14 phase-locked loops

15 clock data restorers

16 decoders

17 seal in and go out device

18 receivers

2 transmission circuits

21 phase-locked modules

22 sending modules

23 receiver modules

231 phase interpolation unit

231a signal interpolation device

The 231b signal selector

232 phase comparison units

233 phasing units

234 seal in and go out the unit

The CLK clock

The D1-D6 data

D _OutData output signal

D _InData input signal

I ₄₁-I ₄₃The interpolation clock signal

I ₅₁-I ₅₃The interpolation clock signal

P _CkClock signal

P _Ck1-P _Ck10Clock signal

P _SsPhase adjustment signal

P _Cs1-P _Cs10Comparison of signal phase

R _F1-R _F10Reference clock signal

T _InData-signal

T _OutData-signal

S01～S04 process step

Embodiment

Hereinafter with reference to correlative type, the transmission circuit according to the embodiment of the invention is described, wherein identical assembly will be illustrated with identical reference marks.

Please refer to shown in Figure 2ly, send a data output signal D according to the transmission circuit 2 of the embodiment of the invention _OutWith reception one data input signal D _In, transmission circuit 2 comprises a phase-locked module 21, a sending module 22 and a receiver module 23.

Phase-locked module 21 produces at least one same frequency but the different clock signal P of phase place _Ck, sending module 22 electrically connects with phase-locked module 21, and receive clock signal P _CkWith data-signal T _Out, and according to clock signal P _CkSend data output signal D _Out, receiver module 23 electrically connects with phase-locked module 21, and receive clock signal P _CkWith data input signal D _In, and according to clock signal P _CkRestore data input signal D _InData and clock, and will be by data input signal D _InRecovered data signal T _InDelivering to other hierarchy circuit handles.That is to say that sending module 22 and receiver module 23 are according to identical clock signal P _CkAnd start.

The P of the clock signal in the present embodiment _CkFrequency is data output signal D _OutIntegral multiple/one of frequency, be 10 to be example then at this with integral multiple.

Please refer to Fig. 3 and shown in Figure 4, phase-locked module 21 produces a plurality of clock signal P _Ck1-P _Ck10, clock signal P _Ck1-P _Ck10For same frequency but out of phase, receiver module 23 comprises a phase interpolation unit 231, at least one phase comparison unit 232 and at least one phasing unit 233.

Phase interpolation unit 231 receive clock signal P _Ck1-P _Ck10With a phase adjustment signal P _Ss, and according to clock signal P _Ck1-P _Ck10With phase adjustment signal P _SsSelect a reference clock signal R _F1-R _F10 Phase interpolation unit 231 can be at adjacent clock signal P _Ck1-P _Ck10Between in insert identical but the interpolation clock signal that phase place is different of at least one frequency, and interpolation clock signal and clock signal P _Ck1-P _Ck10Operating frequency identical, but each clock signal P _Ck1-P _Ck10Then phase place is different each other with each interpolation clock signal.

In the present embodiment, clock signal P _Ck1-P _Ck10Frequency be 150MHz, and clock signal P _Ck1-P _Ck10Phase difference be 1/10th clock signal P _Ck1-P _Ck10In the cycle, sending module 22 is by the clock signals P that differs from one another _Ck1-P _Ck10Trigger, and when triggering, send data output signal D _Out, so sending module 22 sends data output signal D with the frequency of 1.5GHz in the sequence transmission mode _Out

Please refer to Fig. 3 and shown in Figure 5, phase interpolation unit 231 is at each clock signal P _Ck1-P _Ck10Between insert three interpolation clock signals, for example at clock signal P _Ck4-P _Ck5Between insert interpolation clock signal I ₄₁-I ₄₃, at clock signal P _Ck5-P _Ck6Between insert interpolation clock signal I ₅₁-I ₅₃, interpolation clock signal I ₄₁-I ₄₃, I ₅₁-I ₅₃With clock signal P _Ck1-P _Ck10Operating frequency be all 150MHz, but each clock signal P _Ck1-P _Ck10Then phase place is different each other with each interpolation clock signal.

Phase interpolation unit 231 is again according to phase adjustment signal P _Ss, self-clock signal P _Ck1-P _Ck10In the interpolation clock signal, choose wherein ten for reference clock signal R _F1-f ₁₀Reference clock signal R for example _F4By choosing interpolation clock signal I ₄₁And produce reference clock signal R _F5By choosing interpolation clock signal I ₅₂And produce.Reference clock signal R _F1-R _F10Can be for the clock and the data of receiver module restore data input signal.In addition, phase interpolation unit 231 is not to be a clock generating element, but is similar to the buffering area of clock signal, by postponing control to produce the reference clock signal of variant phase place.

The operating frequency of phase comparison unit 232 is 150MHz, data input signal D _InFrequency be 1.5GHz, phase comparison unit 232 once reads ten data input signal D _In, and with data input signal D _InIn everybody respectively with the reference clock signal R of variant phase place _F1-R _F10Compare phase place, to produce comparison of signal phase P respectively _Cs1-P _Cs10, therefore, data input signal D _InClock and data recovered.

Phasing unit 233 receiving phase comparison signal P _Cs1-P _Cs10, and according to comparison of signal phase P _Cs1-P _Cs10Produce a phase adjustment signal P _Ss, with control phase interpolation unit 231 from interpolation clock signal and clock signal P _Ck1-P _Ck10Select and data output signal D _InThe more approaching clock signal of phase place is reference clock signal R _F1-R _F10

In addition, receiver module more comprises one and seals in and go out unit 234, seals in and goes out unit 234 to electrically connect with phase comparison unit 232, and receive data recovered input signal D _In, and according to reference clock signal R _F1-R _F10To data recovered input signal D _InConvert data-signal T to _InData-signal T _InTransmission means is sent to other hierarchy circuit processing side by side.Because in the middle of digital transmission system, the data of a byte (byte) are just transmitted after being encoded to one ten long symbols (symbol) via 8B/10B.Because data input signal D _InFrequency is reference clock signal R _F1-R _F10/ 10th of a frequency, each reference clock signal R _F1-R _F10Correspond to data recovered input signal D during triggering respectively _InEach bit period.Operate in reference clock signal R when sealing in and going out unit 234 _F1During frequency, its in a reference clock cycle from data input signal D _InEssence is taken out ten positions, and these ten long symbols are converted to and column signal by sequence signal, with outputting data signals T _In

Transmission circuit 2 is handled high-frequency data (1.5GHz) with lower operating frequency (150MHz), not only can avoid the puzzlement of high-frequency noise, and also preferable for the beat tolerance of (jitter) of signal.In addition, because reference clock signal R _F1-R _F10Be and seal in and to go out the operating frequency of unit 234 identical, reference clock signal R _F1-R _F10Need not can supply to seal in and go out unit 234 translation data input signal D via extra frequency eliminating circuit _In

In addition, please refer to shown in Figure 6, transmission circuit 2 also can be applicable to the multichannel transmission, with the embodiment of Fig. 3 to Fig. 5 by contrast, receiver module 23 comprises a phase interpolation unit 231, a plurality of phase comparison unit 232, a plurality of phasing unit 233 and a plurality ofly seals in and go out unit 234, and phase interpolation unit 231 comprises a signal interpolation device 231a and a plurality of signal selector 231b.Utilize signal interpolation device 231a, each signal selector 231b, each phase comparison unit 232 and each phasing unit 233 to recover the data input signal D of each passage _InRespectively seal in and go out the data input signal D of unit 234 each passage of conversion _In

With the first passage is example, signal interpolation device 231a receive clock signal P _Ck1-P _Ck10, and according to clock signal P _Ck1-P _Ck10, producing a plurality of interpolation clock signals, signal selector 231b is receive clock signal P respectively _Ck1-P _Ck10, interpolation clock signal and corresponding phase adjustment signal P _Ss, and according to the phase adjustment signal P of first passage _SsFrom interpolation clock signal and clock signal P _Ck1-P _Ck10Select reference clock signal R _F1-R _F10The phase comparison unit 332 of first passage is with seal in and go out unit 234 can be according to reference clock signal R _F1-R _F10And start.

When transmission circuit 2 is applied to the multichannel transmission, only comprise a clock generating element in the transmission circuit 2, transmitter module 22 and receiver module 23 still can be shared identical phase-locked module 21, with known technology by contrast, each passage receiving terminal also can be shared single clock producing component (phase-locked module 21).

Owing to utilize the notion of frequency reducing to handle high-frequency data in the present embodiment, make each data-signal and clock signal in the transmission circuit 2 more can not be subjected to the interference of high-frequency noise, thereby transmitter module 22 and receiver module 23 are able to the reference clock signal R that shared lock phase module 21 produces _F1-R _F10So, only need a clock generating element to get final product in the transmission circuit 2.

In addition, please refer to shown in Figure 7ly, comprise the following steps according to the transmission of the transmission circuit of the embodiment of the invention and the method for reception.

At first, step S01 produces at least one clock signal, wherein identical the but phase place difference of clock signal frequency.

Then, step S02 is according to a phase adjustment signal, at least one interpolation clock signal of interpolation between adjacent clock signal, and wherein the interpolation clock signal is identical with clock signal frequency but phase place is different.

Then, step S03 self-clock signal and interpolation clock signal are selected at least one reference clock signal.

At last, step S04 is according to reference clock signal restore data input signal.

Owing to can be applicable to the data synchronous system of the transmission circuit 2 among earlier figures 2 and Fig. 3 according to the method for data synchronization of present embodiment, and the possible execution mode of above-mentioned method of data synchronization and effect discussed in the data synchronous system of previous embodiment, so repeat no more in this.

In sum, because of complying with in the transmission circuit of the present invention, sending module and receiver module are shared same group of phase-locked module to send respectively or restore data, with known technology by contrast, the quantity required of phase-locked module can reduce in the transmission circuit, with the framework of simplification transmission circuit, and then the cost of reduction transmission circuit.

The above only is an illustrative, but not is restrictive.Anyly do not break away from spirit of the present invention and category, and, all should be contained in the appended claim scope its equivalent modifications of carrying out or change.

Claims

1, a kind of transmission circuit, in order to send a data output signal and to receive a data input signal, transmission circuit comprises:

One phase-locked module is in order to produce identical but a plurality of clock signals that phase place is different of frequency;

One sending module electrically connects with this phase-locked module, in order to send described data output signal according to described clock signal; And

One receiver module electrically connects with this phase-locked module, in order to receiving described data input signal, and according to the described data input signal of described recovering clock signals;

Wherein this receiver module comprises:

One phase interpolation unit, it receives a described clock signal and a phase adjustment signal, in order to select at least one reference clock signal;

At least one phase comparison unit, it receives described reference clock signal and described data input signal, in order to the phase place of more described data input signal and described reference clock signal and produce a comparison of signal phase, utilize described phase comparison unit to recover described data input signal simultaneously;

At least one phasing unit receives described comparison of signal phase, in order to produce a phase adjustment signal according to described comparison of signal phase; And

One seals in and goes out the unit, electrically connects with this phase comparison unit, and receives the described data input signal that has recovered, and convert a data-signal to according to the described data input signal that described reference clock signal will recover.

2, transmission circuit as claimed in claim 1, the frequency of wherein said clock signal are integral multiple/one of described data output signal frequency.

3, transmission circuit as claimed in claim 1, wherein said phase interpolation unit interpolation frequency between adjacent clock signal is identical but a plurality of interpolation clock signals that phase place is different, and described interpolation clock signal is identical with described clock signal frequency but phase place is different.

4, transmission circuit as claimed in claim 3, wherein said phase interpolation unit is selected described reference clock signal according to described phase adjustment signal by described interpolation clock signal and described clock signal.

5, transmission circuit as claimed in claim 1 wherein comprises a plurality of phase comparison units and a plurality of phasing unit when this receiver module, and this phase-locked module is when producing described a plurality of clock signal, and described phase interpolation unit comprises:

One signal interpolation device in order to receiving described clock signal, and produces a plurality of interpolation clock signals according to described clock signal; And

A plurality of signal selectors, in order to receiving described clock signal, described interpolation clock signal and corresponding described phase adjustment signal respectively, and select described reference clock signal from described interpolation clock signal and described clock signal according to described phase adjustment signal.

6, a kind of transmission and the method that receives, in order to send a data output signal and to receive a data input signal, this method includes:

Produce a plurality of clock signals, wherein said clock signal frequency same phase difference;

According to a phase adjustment signal at least one interpolation clock signal of interpolation between adjacent described clock signal, wherein said interpolation clock signal is different with described clock signal frequency same phase;

Select at least one reference clock signal from described clock signal and described interpolation clock signal; And

Recover described data input signal according to described reference clock signal;

The frequency of wherein said clock signal is integral multiple/one of described data output signal frequency.

7, transmission as claimed in claim 6 and method of reseptance, the phase place that more comprises more described reference clock signal and described data input signal is in order to produce described phase adjustment signal.

8, transmission as claimed in claim 6 and method of reseptance, more comprise with the recovered data input signal convert to and column signal after export.

9, transmission as claimed in claim 6 and method of reseptance, wherein this method more comprises according to described clock signal and sends described data output signal.