CN109709826B - Method for quickly switching transmitting phases of transmitting and receiving components - Google Patents
Method for quickly switching transmitting phases of transmitting and receiving components Download PDFInfo
- Publication number
- CN109709826B CN109709826B CN201811471644.3A CN201811471644A CN109709826B CN 109709826 B CN109709826 B CN 109709826B CN 201811471644 A CN201811471644 A CN 201811471644A CN 109709826 B CN109709826 B CN 109709826B
- Authority
- CN
- China
- Prior art keywords
- data
- control data
- bit
- phase
- transmitting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention discloses a method for quickly switching transmitting phases of a transmitting and receiving assembly, which comprises the following steps: reading serial data into a shift register by using a chip selection signal and a clock signal; the latch signal stores the serial data in the shift register into a latch; under the action of a transmission pulse signal, a first switch selection circuit processes the serial data to form first parallel control data; under the action of transceiving pulses, a second switch selection circuit processes the first parallel control data to form second parallel control data, and the second parallel control data is used for driving a control device in a transmitting or receiving state; the invention optimizes the original data reading from twice to only one time by the mode of presetting data and reading and then selecting, and improves the data reading and converting speed while keeping the simpler control of the serial interface control signal.
Description
Technical Field
The invention relates to the technical field of vibration isolation and buffering of electronic equipment, in particular to a method for quickly switching transmitting phases of a transmitting and receiving assembly.
Background
The transceiving component is used as a basic component unit in the active phased array antenna and plays an extremely important role in a system. When the module receives and works, the module amplifies the signal fed in by the antenna with low noise, and then adjusts the amplitude and the phase of the signal through the attenuator, the phase shifter or the delayer. When the module is in transmission work, the phase of the input small signal is adjusted by the phase shifter, and then the small signal is amplified by the amplifying link in the module. The amplified signal reaches the value required by the system and is transmitted by the antenna array.
When the active phased array antenna performs beam scanning, the components need to work in different phase states through phase shifters or delay lines, so that the antenna units are in required phase difference. The speed at which the phase of the phase shifter is changed therefore determines the speed at which the antenna is scanned. In view of the convenience of computer control in beam scanning, digitally controlled phase shifters or time delays are typically employed inside the assembly. Such phase shifters or time delays typically employ a combination of multiple parallel control signals to control them to be in respective phases. In order to simplify the control interface between the components and the system, the components are usually controlled by serial signals, and the components need to convert the serial signals into parallel control signals required by phase shifters or time delays. The time required for signal switching determines the component phase control time and also limits the ability to rapidly scan the antenna beam.
In view of the above-mentioned drawbacks, the inventors of the present invention have finally obtained the present invention through a long period of research and practice.
Disclosure of Invention
In order to solve the technical defects, the invention adopts the technical scheme that a method for quickly switching the transmitting phase of a transmitting-receiving component is provided, and comprises the following steps;
s1, reading the serial data into the shift register by the chip selection signal and the clock signal;
s2, storing the serial data in the shift register into a latch by a latch signal;
s3, under the action of the emission pulse signal, the first switch selection circuit processes the serial data to form first parallel control data;
and S4, under the action of transceiving pulse, the second switch selection circuit processes the first parallel control data to form second parallel control data, and the second parallel control data is used for driving the control device in a transmitting or receiving state.
Preferably, the control data is set as n-bit serial data signals, and the control data comprises a-bit current state transmission phase shift control data and a-bit next state transmission phase shift control data; the data character segments of the current state emission phase-shift control data and the next state emission phase-shift control data are adjacently arranged; the control data also comprises a bit receiving phase shift control data, b bit receiving attenuation data and b bit transmitting attenuation data; and the data chain length n of the control data is 3a +2 b.
Preferably, in step S3, the transmission pulse signal performs a falling edge function, and the first switch selection circuit selects the current-state transmission phase-shift control data or the next-state transmission phase-shift control data under the falling edge function; and the selected current state emission phase-shift control data or the next state emission phase-shift control data and other bit data of original data form the first parallel control data, and the first parallel control data is placed in a buffer.
Preferably, the first parallel control data is 2a +2b bits of data, and the first parallel control data includes a bits of the current state transmission phase shift control data, a bits of the reception phase shift control data, b bits of the reception attenuation data, b bits of the transmission attenuation data, or a bits of the next state transmission phase shift control data, a bits of the reception phase shift control data, b bits of the reception attenuation data, and b bits of the transmission attenuation data.
Preferably, in step S4, under the action of the high and low levels of the transceiving pulses, the second switch selection circuit selects the control data with high or low bits from the first parallel control data by selecting high and low bits to form the second parallel control data, so as to drive the control device in the transmitting or receiving state.
Preferably, the high-order control data is a transmission status code, and the high-order control data includes the current-state transmission phase shift data and the transmission attenuation data or the next-state transmission phase shift data and the transmission attenuation data.
Preferably, the low-order control data is a reception status code, and the low-order control data includes the reception phase shift data and the reception attenuation data.
Compared with the prior art, the invention has the beneficial effects that: the invention optimizes the original data reading from twice to only one time by the mode of presetting data and reading and then selecting, and improves the data reading and converting speed while keeping the control of the serial interface control signal to be simpler.
Drawings
Fig. 1 is a schematic flow chart of a method for rapidly switching a transmitting phase of a transceiver module according to the present invention.
Detailed Description
The above and further features and advantages of the present invention are described in more detail below with reference to the accompanying drawings.
Example one
As shown in fig. 1, fig. 1 is a schematic flow chart of a method for rapidly switching a transmitting phase of a transceiver module according to the present invention; the invention relates to a method for quickly switching transmitting phases of a transmitting and receiving assembly, which comprises the following steps of;
s1, reading serial data SD0 into shift register SR by chip selection signal SEL and clock signal SC;
s2, a latch signal DRY stores the serial data SD0 in the shift register SR into a latch LA;
s3, under the action of the TRT, the first switch selection circuit S1 processes the serial data SD0 to form the first parallel control data SD 1;
s4, under the action of the TRR, the second switch selection circuit S2 processes the first parallel control data SD1 to form second parallel control data SD2, the second parallel control data SD2 is used to drive the control device in the transmitting or receiving state.
The control data SD0 is typically provided as an n-bit serial data signal, and the control data SD0 comprises a-bit current-state transmitted phase-shift control data (D)x+1，…，Dx+a) And a-bit next-state transmission phase shift control data (D)x+a+1，…，Dx+2a) (ii) a The data character segments of the current state emission phase shift control data and the next state emission phase shift control data are adjacently arranged and can be set to be the same. The control data SD0 further includes a-bit received phase shift control data, b-bit received attenuation data, and b-bit transmitted attenuation data. Therefore, in general, the data link length n of the control data SD0 is 3a +2 b.
In step S1, the clock signal SC reads the serial data SD0 into the shift register SR under the action of the chip select signal SEL; then, in the step S2, the control data SD0 in the shift register SR is stored in the latch LA by the action of the latch signal DRY.
In step S3, the transmission pulse signal TRT performs a falling edge action, and the first switch selection circuit S1 performs the falling edge action at the lower sideSelecting said current state transmit phase shift control data (D) under edge droppingx+1，…，Dx+a) Or said next state transmits phase shift control data (D)x+a+1，…，Dx+2a) After the current state is formed into parallel control data, the next state is formed into parallel control data, and the two processes are alternately carried out. The selected current state transmitting phase shift control data or the next state transmitting phase shift control data and other bit data of original data form first parallel control data SD1, and the other bit data of the original data are generally a bit of the receiving phase shift control data, b bit of the receiving attenuation data and b bit of the transmitting attenuation data; the first parallel control data SD1 is 2a +2b bit data, and the first parallel control data SD1 is placed in a buffer.
In step S4, under the action of the high and low levels of the transmit/receive pulse TRR, the second switch selection circuit S2 selects the high or low (a + b) bit data of the first parallel control data SD1 to form the second parallel control data SD2, so as to drive the control device in the transmitting or receiving state.
The invention comprises serial control data SD0, a clock signal SC, a chip selection signal SEL, a latch signal DRY, a transmission pulse TRT, a shift register SR, a latch LA, a transceiving switching signal pulse TRR, a first switch selection circuit S1, a second switch selection circuit S2, a drive circuit DR, first parallel control data SD1 and second parallel control data SD 2. The invention has the function of quickly converting serial control data SD0 into parallel drive control signals SD2 so as to drive microwave control devices in the assembly.
By setting the shift register SR and the latch LA, the receiving phase shift control data, the receiving attenuation data and the transmitting attenuation data with unchanged data between adjacent states are stored in the latch LA; by adopting the conversion circuit with the structure, when serial data SD0 containing two groups of adjacent data are driven into the latch LA, the serial data SD0 are read uniformly; the data in the latch LA can be read out in the current state and the next state respectively by only independently combining the data in the latch LA without repeatedly extracting the same receiving phase shift control data, receiving attenuation data and transmitting attenuation data. Therefore, the reading efficiency of the whole system can be improved, and the system conversion time can be shortened.
The invention simultaneously and adjacently arranges the phase control codes (2a bit data) of two transmitting pulses in the control serial data SD0 of the transceiving component, and converts the phase control codes into parallel data through a serial-parallel conversion circuit and stores the parallel data. Two sets of adjacent phase control codes are first selected by the switch selection circuit S1, which triggers the falling edge of the transmit pulse TRT. Then, the selected data and the remaining control data are made up into new data SD 1. The switch selection circuit S2 is driven by the TRR high and low levels to select a part of data from the SD1 to constitute SD2 to control the device state in the transmitting or receiving state. By the mode of presetting data and reading and then selecting, the original data reading is optimized from two times to only one time. And if the clock frequency is fc and the data length is n (2a +2b), the time t required by reading is 2 (2a +2b)/fc respectively by two transmitting phases, the method reduces the reading time from 2 (2a +2b)/fc read respectively to (3a +2b)/fc, shortens the reading time by (a +2b)/fc, and improves the data reading and converting speed.
Example two
In this embodiment, the control devices are a 6-bit phase shifter and a 6-bit attenuator, and the serial data SD0 needs to include 6-bit transmission phase shift data in the current state and 6-bit transmission phase shift data in the next state, which are driven in adjacent. The serial data SD0 should further include 6-bit transmission attenuation data, 6-bit reception phase shift data, and 6-bit reception attenuation data. Under the action of the chip selection signal SEL, the clock signal SC reads 30-bit serial data SD0 including the data into the shift register SR; the serial data SD0 in the shift register SR is then stored in the latch LA by the latch signal DRY.
Under the action of the falling edge of the transmission pulse signal TRT, the first switch selection circuit S1 selects the 6-bit transmission phase shift data in the current state or the 6-bit transmission phase shift data in the next state, and the 6-bit transmission phase shift data or the 6-bit transmission phase shift data in the next state form the 24-bit first parallel control data SD1 together with the remaining 18-bit transmission attenuation data, 6-bit reception phase shift data, and 6-bit reception attenuation data in the original serial data SD0 and are placed in the buffer.
Under the action of the high and low levels of the transmit-receive pulse TRR, the second switch selection circuit S2 selects the high 12-bit data (transmit state code) or the low 12-bit data (receive state code) in the first parallel control data SD1 to form second parallel control data SD2 by selecting the high and low data, so as to drive the control device in the transmit or receive state; wherein, the high-order 12-bit data (transmission status code) generally comprises 6-bit current state transmission phase shift data and 6-bit transmission attenuation data or 6-bit next state transmission phase shift data and 6-bit transmission attenuation data; the lower 12-bit data (reception state code) generally includes 6-bit reception phase-shifted data and 6-bit reception attenuation data.
The foregoing is merely a preferred embodiment of the invention, which is intended to be illustrative and not limiting. It will be understood by those skilled in the art that various changes, modifications and equivalents may be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (4)
1. A transmitting phase rapid switching method of a transmitting and receiving component is characterized by comprising the following steps;
s1, reading the serial data into the shift register by the chip selection signal and the clock signal;
s2, storing the serial data in the shift register into a latch by a latch signal;
s3, under the action of the emission pulse signal, the first switch selection circuit processes the serial data to form first parallel control data;
s4, under the action of transceiving pulse, the second switch selection circuit processes the first parallel control data to form second parallel control data, and the second parallel control data is used for driving a control device in a transmitting or receiving state;
the serial data is set into n-bit serial data signals, and the serial data comprises a-bit current state transmission phase-shift control data and a-bit next state transmission phase-shift control data; the data character segments of the current state emission phase-shift control data and the next state emission phase-shift control data are adjacently arranged; the serial data also comprises a bit receiving phase shift control data, b bit receiving attenuation data and b bit transmitting attenuation data; the length n of the serial data is 3a +2 b;
in step S3, the transmit pulse signal implements a falling edge function, and the first switch selection circuit selects the transmit phase shift control data in the current state or the transmit phase shift control data in the next state under the falling edge function; the selected current state emission phase shift control data or the next state emission phase shift control data and other bit data of original data form first parallel control data, and the first parallel control data is placed in a buffer;
in step S4, under the action of the high and low levels of the transceiving pulses, the second switch selection circuit selects the control data with high or low bits from the first parallel control data by selecting high and low bits to form the second parallel control data, so as to drive the control device in the transmitting or receiving state.
2. The method of claim 1, wherein the first parallel control data is 2a +2b bits of data, and the first parallel control data comprises a bits of the current state transmit phase shift control data, a bits of the receive phase shift control data, b bits of the receive attenuation data, b bits of the transmit attenuation data, or a bits of the next state transmit phase shift control data, a bits of the receive phase shift control data, b bits of the receive attenuation data, and b bits of the transmit attenuation data.
3. The method of claim 2, wherein the high-level control data is a transmission status code, and the high-level control data comprises the current-state transmission phase-shift data and the transmission attenuation data or the next-state transmission phase-shift data and the transmission attenuation data.
4. The method of claim 2, wherein the low-level control data is a receive status code, and the low-level control data comprises the receive phase-shifted data and the receive fading data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811471644.3A CN109709826B (en) | 2018-11-30 | 2018-11-30 | Method for quickly switching transmitting phases of transmitting and receiving components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811471644.3A CN109709826B (en) | 2018-11-30 | 2018-11-30 | Method for quickly switching transmitting phases of transmitting and receiving components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109709826A CN109709826A (en) | 2019-05-03 |
| CN109709826B true CN109709826B (en) | 2020-04-07 |
Family
ID=66254577
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811471644.3A Active CN109709826B (en) | 2018-11-30 | 2018-11-30 | Method for quickly switching transmitting phases of transmitting and receiving components |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109709826B (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6975557B2 (en) * | 2003-10-02 | 2005-12-13 | Broadcom Corporation | Phase controlled high speed interfaces |
| CN100440773C (en) * | 2006-04-18 | 2008-12-03 | 威盛电子股份有限公司 | Phase inserted transmit-receive circuit and its transmit-receive method |
| CN100495929C (en) * | 2006-07-28 | 2009-06-03 | 东南大学 | Confinement competition digital circuit with homophase displacement mode |
| CN102436796B (en) * | 2011-12-19 | 2013-10-30 | 北京大学深圳研究生院 | Display device and data driving circuit thereof |
| CN104714212B (en) * | 2015-02-15 | 2017-03-01 | 中国电子科技集团公司第三十八研究所 | T/R assembly control chip and its application in active phase array antenna system |
| CN108767445A (en) * | 2018-05-31 | 2018-11-06 | 北京神舟博远科技有限公司 | Reconfigurable multifunctional antenna based on distributed directly drive array |
-
2018
- 2018-11-30 CN CN201811471644.3A patent/CN109709826B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN109709826A (en) | 2019-05-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102813530B (en) | Drive equipment and method, the medical image system of two-dimensional transducer array | |
| US7215599B2 (en) | Ultrasonic transmitter, ultrasonic transceiver and sonar apparatus | |
| US6205189B1 (en) | Digital automatic gain control method and device for use in communication terminal of mobile radio communication system | |
| RU2008109239A (en) | WIRELESS COMMUNICATION DEVICE USING ADAPTIVE FORMATION OF DIRECTION DIAGRAM | |
| CN1258150C (en) | Semiconductor device | |
| US5986590A (en) | Antenna system | |
| US7450911B1 (en) | Multiplexed wireless receiver and transmitter | |
| US7551107B2 (en) | Multiplexer for controlling data output sequence and parallel-to-serial converter using the same | |
| CN1714520A (en) | Monitoring stability of an on-frequency repeater | |
| CN109709826B (en) | Method for quickly switching transmitting phases of transmitting and receiving components | |
| CN1287342A (en) | Display device, signal transmitting / receiving apparatus and radio transmitting apparatus | |
| WO2023168734A1 (en) | Digital full-broadband direct forwarding type radar transponder system and working method therefor | |
| CN109901115B (en) | Radar data transmission device and radar system | |
| NO832488L (en) | PROCEDURE AND STRENGTHENING SYSTEM | |
| US20070126616A1 (en) | Dynamically linearized digital-to-analog converter | |
| KR20070058568A (en) | System and method for ultra wideband communications using multiple code words | |
| US8185718B2 (en) | Code memory capable of code provision for a plurality of physical channels | |
| JP4210289B2 (en) | Digital-analog converter | |
| KR20140072355A (en) | Transmitting and receiving beam forming apparatus for active phased array antenna | |
| KR20050067373A (en) | Ultrasonic diagnostic apparatus | |
| US5040189A (en) | Multiple frequency radio system employing pulse repeaters | |
| US7741989B2 (en) | Radar system, radar transmission signal generation method, program therefor and program recording medium | |
| US7667627B2 (en) | Memory code generator | |
| RU2668224C1 (en) | Repeater of radio signals | |
| US20240125911A1 (en) | Pulse radar device and operating method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |