CN101364960B - High-speed differential interface - Google Patents
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- CN101364960B CN101364960B CN2008100403327A CN200810040332A CN101364960B CN 101364960 B CN101364960 B CN 101364960B CN 2008100403327 A CN2008100403327 A CN 2008100403327A CN 200810040332 A CN200810040332 A CN 200810040332A CN 101364960 B CN101364960 B CN 101364960B
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Abstract
The invention relates to a high speed differential interface which comprises a transmitter, a receiver, and a data channel and a clock channel between the transmitter and the receiver. The transmitter comprises an encoder for receiving external data, a serializer connected with the encoder, a driver connected with the outlet of the serializer and a frequency synthesizer for receiving reference clock signals, and the outlet of the frequency synthesizer is accessed into the serializer; and the receiver comprises a data latch unit connected with the driver through two differential data channels and a differential clock channel, a deseriallizer connected with the outlet of the data latch unit and a decoder connected with the outlet of the deseriallizer. By adopting the high speed differential interface with the structure, no frequency synthesizer is arranged on the receiver side, and the clock deviation and the data deviation mutually follow up and balance out. Through the entire interface circuit, small lead wire quantity, low energy consumption, low noise, high data rate and low cost are realized.
Description
Technical field
The present invention relates to a kind of high-speed differential interface (HSDI).
Background technology
Along with the development of mechanics of communication, require the data transmission bauds of chip chamber more and more faster.Now the demand of high speed data transfer is just being promoted interfacing and developing, and the low voltage difference signal possesses all above-mentioned characteristics to the direction of high speed, serial, difference, low-power consumption and point-to-point interface.The advantage of differential signal is that amplitude is less, can make the data transmission bauds maximization, and have more anti-interference, antimierophonic performance.At communication field, using more differential signal is exactly LVDS and HDMI (High Definition Multimedia Interface) (HDMI/TMDS).The level setting of these two kinds of signals all is to be defined by relevant international standard, and in general, the interface common-mode voltage of LVDS is 1.2v, and the interface termination voltage of HDMI/TMDS is 3.3v.
The structure of existing HDMI/TMDS mainly comprises the HDMI content sending apparatus as shown in Figure 1, the HDMI display terminal.Has the HDMI transmitter in the HDMI content sending apparatus, receiving video signals, audio signal and control/status signal.The HDMI display terminal comprises HDMI receiver and digital video information storage chip (EDID ROM).The HDMI receiver is sent out processed video, audio frequency and control/status signal.The EDID rom chip will show all audio frequency and the video format of being supported, comprise the color depth pattern.Be provided with three TMDS data channels and a TMDS clock channel between HDMI receiver and the HDMI transmitter, be used for data-signal in the HDMI transmitter and clock signal are transferred in the HDMI receiver.Video, audio-frequency information bag also are sent to the HDMI transmitter from HDMI transmitter H.Between HDMI transmitter and HDMI receiver, also carry out chip enable control (CEC)
The HDMI/TMDS of said structure has the audio/video format display data channel (DDC) of extra support, and this just needs extra input/output line.Simultaneously, this HDMI/TMDS is owing to need 3 data channels and 1 clock channel, and interface capacity is bigger.Reflector and receiver two ends all need to be provided with frequency synthesizer, have strengthened the complexity of cost and structure.Signal amplitude is 500mV, has caused higher energy consumption.Interface termination voltage is 3.3v, has limited the improving technology of high speed data transfer.
The structure of another kind of LVDS as shown in Figure 2, this LVDS comprises main graphic controller, transmitter, receiver and the LCD panel controller that links to each other successively.The advantage of above-mentioned LVDS is to have long transmission range and do not need codec.But this LVDS also has following deficiency: the interface common-mode voltage is 1.2v, has limited the improving technology of high speed data transfer.Need all in transmitter and the receiver that frequency synthesizer is set and come restore data, the frequency synthesizer of receiver one side will form another clock jitter and cause the data capture problem, and needs more circuit to compensate.This just makes the entire circuit complex structure, and cost improves.This LVDS is owing to need 4 data channels and 1 clock channel, and interface capacity is bigger.
Summary of the invention
The object of the present invention is to provide a kind of high-speed differential interface, to overcome the deficiency of above-mentioned HDMI/TMDS and LVDS interface.
In order to realize the foregoing invention purpose, technical scheme of the present invention is as follows:
A kind of high-speed differential interface comprises data channel and clock channel between transmitter, receiver and described transmitter and the receiver; Described transmitter comprises: encoder receives external data; Serializer links to each other with the encoder outlet; Driver links to each other with the serializer outlet; And frequency synthesizer, receiving reference clock signal, this frequency synthesizer output inserts described serializer; Described receiver comprises: data latches and links to each other with a differential clocks channel by two differential data channels between the described driver; Deserializer links to each other with the outlet of data latches; Decoder links to each other with the outlet of deserializer.
Adopt the high-speed differential interface of said structure, receiver-side does not have frequency synthesizer, thereby the clock jitter of this moment and data deviation are followed the tracks of mutually and cancelled out each other.Whole interface circuit has been realized low pin count, low-energy-consumption, low noise, high data rate, low cost.
The serialization rate of described serializer is 16: 1.
Described clock channel provides the data rate the same with data channel.
The capacity of described each differential data channel is 32bits.
Described receiver uses that clock is bilateral catches data along triggering method.
Described driver contains 6mA and draws electric current and speed-sensitive switch.
Description of drawings
Fig. 1 is the structure chart of existing HDMI/TMDS;
Fig. 2 is the structure chart of existing LVDS;
Fig. 3 is the structure chart of high-speed differential interface of the present invention.
Embodiment
According to Fig. 3, provide preferred embodiment of the present invention, and described in detail below, enable to understand better function of the present invention, characteristics.
Fig. 3 is the structure chart of high-speed differential interface of the present invention.As shown in Figure 3, a kind of high-speed differential interface mainly comprises transmitter, receiver two parts.Transmitter comprises encoder, serializer, driver and frequency synthesizer four parts.Encoder receives the data from the outside, carries out bit synchronization, promptly make the receiving terminal timing signal and the timing signal that receives between have given phase relation.When needed, encoder carries out the dc balance coding.Serializer links to each other with the encoder outlet.The serialization rate of this serializer is 16: 1, is used for 16 parallel datas are converted into 1 continuous data flow.Driver links to each other with the serializer outlet, and this driver contains 6mA and draws electric current and speed-sensitive switch.Frequency synthesizer, its output inserts described serializer, and this frequency synthesizer receives reference clock signal, produces 16 phase clocks based on reference clock and is input to serializer.
Described receiver comprises data latches, deserializer and decoder three parts.Link to each other with a differential clocks channel by two differential data channels between data latches and the described driver, provide suitable clock adjustment algorithm to optimize the strobe pulse location, catch data, conversion differential signal to digital signal.Described clock channel provides the data rate the same with data channel, and the capacity of each differential data channel is 32bits.Deserializer links to each other with the outlet of data latches, is used for continuous data flow is changed back parallel data.Decoder links to each other with the outlet of deserializer, is used to eliminate the dc balance coding and extracts the data of alignment again.
From the high-speed differential interface of said structure as can be seen, receiver-side is not provided with frequency synthesizer.This just strengthens the binary system error rate (BER) and is used for secure data transmission.Thereby the clock jitter of this moment and data deviation are followed the tracks of mutually and are cancelled out each other.Whole interface circuit has been realized low pin count, low-energy-consumption, low noise, high data rate, low cost.Receiver uses that clock is bilateral catches data along triggering method.This high-speed differential interface physical signalling amplitude of oscillation is 300mV, adopts 50 ohm terminal to come receiving-end voltage.
Above-described, be preferred embodiment of the present invention only, be not in order to limiting scope of the present invention, the above embodiment of the present invention can also be made various variations.Be that every simple, equivalence of doing according to the claims and the description of the present patent application changes and modification, all fall into the claim protection range of patent of the present invention.
Claims (6)
1. a high-speed differential interface comprises data channel and clock channel between transmitter, receiver and described transmitter and the receiver; It is characterized in that,
Described transmitter comprises:
Encoder receives external data, carries out bit synchronization;
Serializer links to each other with the encoder outlet;
Driver links to each other with the serializer outlet; With
Frequency synthesizer receives reference clock signal, and this frequency synthesizer output inserts described serializer;
Described receiver comprises:
Data latches and links to each other with a differential clocks channel by two differential data channels between the described driver;
Deserializer links to each other with the outlet of data latches;
Decoder links to each other with the outlet of deserializer.
2. high-speed differential interface as claimed in claim 1 is characterized in that, the serialization rate of described serializer is 16: 1.
3. high-speed differential interface as claimed in claim 2 is characterized in that, the capacity of described each differential data channel is 32bits.
4. as claim 1 or 2 or 3 described high-speed differential interfaces, it is characterized in that described clock channel provides the data rate the same with data channel.
5. as claim 1 or 2 or 3 described high-speed differential interfaces, it is characterized in that described receiver uses that clock is bilateral catches data along triggering method.
6. as claim 1 or 2 or 3 described high-speed differential interfaces, it is characterized in that described driver contains 6mA and draws electric current and speed-sensitive switch.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2008100403327A CN101364960B (en) | 2008-07-08 | 2008-07-08 | High-speed differential interface |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2008100403327A CN101364960B (en) | 2008-07-08 | 2008-07-08 | High-speed differential interface |
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| CN101364960A CN101364960A (en) | 2009-02-11 |
| CN101364960B true CN101364960B (en) | 2011-11-23 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102142987B (en) * | 2010-12-09 | 2014-01-08 | 浪潮(北京)电子信息产业有限公司 | Serial bus equipment and data transmission method thereof |
| CN107147863A (en) * | 2017-06-08 | 2017-09-08 | 晶晨半导体(上海)股份有限公司 | It is a kind of to reduce the method that high-definition interface is disturbed wireless signal |
| CN113810319B (en) * | 2021-11-17 | 2022-02-08 | 伟恩测试技术(武汉)有限公司 | Clock data transmission circuit, reception circuit, recovery circuit and method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1046057A (en) * | 1989-03-30 | 1990-10-10 | Gec-普列斯长途电讯有限公司 | High speed asynchronous data interface |
| CN1939072A (en) * | 2003-11-17 | 2007-03-28 | 索尼电子有限公司 | Method and system for wireless digital multimedia transmission |
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2008
- 2008-07-08 CN CN2008100403327A patent/CN101364960B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1046057A (en) * | 1989-03-30 | 1990-10-10 | Gec-普列斯长途电讯有限公司 | High speed asynchronous data interface |
| CN1939072A (en) * | 2003-11-17 | 2007-03-28 | 索尼电子有限公司 | Method and system for wireless digital multimedia transmission |
Non-Patent Citations (1)
| Title |
|---|
| 舒林锋.低压差分信号接口系统的设计.《武汉科技大学硕士学位论文》.2008,第1.1节，2.5节，6.1节，8.1节. * |
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Owner name: SHANGHAI WEIZHOU MICROELECTRONIC TECHNOLOGY CO., L Free format text: FORMER OWNER: HUAYA MICROELECTRONICS, INC. Effective date: 20121107 |
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