CN203616749U - Device for realizing high-speed board level communication - Google Patents
Device for realizing high-speed board level communication Download PDFInfo
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- CN203616749U CN203616749U CN201320656551.4U CN201320656551U CN203616749U CN 203616749 U CN203616749 U CN 203616749U CN 201320656551 U CN201320656551 U CN 201320656551U CN 203616749 U CN203616749 U CN 203616749U
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Abstract
The utility model provides a device for realizing high-speed board level communication. The device comprises a master control equipment interface, a buffer, a serializer/deserializer and a high-speed data transceiving interface which are serially connected in sequence; during data transmitting, the serializer/deserializer is used for converting parallel data input from the high-speed data transceiving interface into serial data, and then sending to master control equipment through the master control equipment interface after data balance is carried out on the serial data by the buffer; during data receiving, the buffer is used for receiving data from the master control equipment through the master control equipment interface and pre-emphasizing the data, then converting the pre-emphasized data into parallel data by the serializer/deserializer, and outputting the parallel data through the high-speed data transceiving interface. The device can be used for effectively improving the transmission rate and transmission distance of the data.
Description
Technical field
The utility model relates to communication technical field, in particular to a kind of device of realizing the communication of High-Speed-Board level.
Background technology
SERDES (SERializer/DESerializer) is a kind of time division multiplexing, the point-to-point communication technology, at transmitting terminal, multi-path low speed parallel signal is converted into high-speed serial signals, through transmission medium (optical cable or copper cash), finally again convert high-speed serial signals to low-speed parallel signal at receiving end.This point-to-point serial communication technology makes full use of the channel capacity of transmission medium, reduces required transmission channel and device pin number, thereby greatly reduces communications cost.
A typical SERDES transceiver is made up of sendaisle and receiving cable, as shown in Figure 1, mainly comprises: scrambler, serializer, transmitter and clock generation circuit composition sendaisle; Demoder, deserializer, receiver and clock recovery circuitry composition receiving cable.As its name suggests, encoder completes coding and decoding function, and wherein 8B/10B, 64B/66B and irregular coding are the most frequently used encoding schemes; Serializer and deserializer are responsible for from parallel-to-serial and from serial-to-parallel conversion.Serializer needs clock circuit, and clock circuit is realized by phaselocked loop (PLL) conventionally.Deserializer needs clock and data recovery circuit (CDR), and clock recovery circuitry is also realized by phaselocked loop conventionally, but has multiple way of realization as phase-interpolation, superfluous sampling etc.Transmitter and receiver complete the sending and receiving of differential signal, wherein LVDS (Low Voltage Differential Signaling, low-voltage differential signal) and CML (Current Mode Logic, CML) be two kinds of the most frequently used differential signal standards.Also have in addition some auxiliary circuits to be also absolutely necessary, for example go-and-return test, built-in error rate test etc.
The main performance index of SERDES chip comprises that shake produces, shake tolerance, jitter transfer and error rate of system (BER) etc.Shake produces depends on the particularly phase noise of voltage controlled oscillator (VCO) of clock circuit; The ability of clock recovery circuitry tolerance shake is depended in shake tolerance, and jitter transfer be must be satisfied when as repeater index, depend on the performance of clock circuit and clock recovery circuitry simultaneously.Error rate of system (conventionally requiring lower than 10-12) is determined jointly by clock jitter performance, sender signal amplitude, receiver sensitivity and link channel characteristic.
Adopt at present advanced balancing technique can realize the 10G backboard transmission of 40 inches of (1 meter) distances.
System transfer rate is lower at present, the transmission range of plate inter-stage is shorter, antijamming capability is relatively lower, and for the printed circuit board (PCB) of common FR4 grade, the intersymbol interference that skin effect and dielectric loss cause is the main factor of restriction backboard transfer rate and distance.
Utility model content
The utility model provides a kind of device of realizing the communication of High-Speed-Board level, in order to improve transfer rate and the transmission range of data.
For this reason, the utility model embodiment provides following technical scheme:
A device of realizing the communication of High-Speed-Board level, comprising:
The main control equipment interface, impact damper, serial/deserializer and the high-speed data transmitting-receiving interface that are connected in series successively;
In the time that data send, serial/deserializer, by being converted to serial data from the parallel data of high-speed data transmitting-receiving interface input, is then carried out sending to main control equipment by described main control equipment interface after data balancing to described serial data by impact damper;
In the time of data receiver, impact damper receives the data from main control equipment by main control equipment interface, and described data are carried out to pre-emphasis, then by serial/deserializer, the data after pre-emphasis is converted to parallel data, and receives and dispatches interface output by high-speed data.
Preferably, described device also comprises: small computer system interface, is serially connected between described impact damper and main control equipment interface.
Preferably, described serial/deserializer is field programmable gate array.
Preferably, described field programmable gate array comprises the input of 16b it and the output of 16b it, for transmitting synchronizing signal, handshake.
Preferably, described impact damper is single pass LVDS impact damper.
Preferably, described high-speed data transmitting-receiving interface is Serial Lite II Two lanes interface.
Preferably, described high-speed data transmitting-receiving interface supports that flank speed is 625MB/s.
Preferably, a single pass LVDS impact damper of every pair of difference docking of described Serial Lite II Two lanes interface.
The device of High-Speed-Board level communication that what the utility model embodiment provided realize, by transmitting pre-emphasis and receiving equalization function, is guaranteeing, under the prerequisite of signal lossless, effectively to have improved transfer rate and transmission range.
Accompanying drawing explanation
Accompanying drawing described herein is used to provide further understanding of the present utility model, forms the application's a part, and schematic description and description of the present utility model is used for explaining the utility model, does not form improper restriction of the present utility model.In the accompanying drawings:
Fig. 1 is SERDES sendaisle receiving cable composition model in prior art;
Fig. 2 is the theory diagram that the utility model embodiment realizes the device of High-Speed-Board level communication;
Fig. 3 is a kind of specific implementation structural drawing of the utility model embodiment device of realizing the communication of High-Speed-Board level.
Embodiment
The utility model embodiment realizes the device of High-Speed-Board level communication, by transmitting pre-emphasis and receiving equalization function, transmitting terminal is promoted the high fdrequency component of input signal, thereby the loss characteristics of compensate for channel, guaranteeing, under the prerequisite of signal lossless, effectively to improve transfer rate and transmission range.
As shown in Figure 2, be the theory diagram that the utility model embodiment realizes the device of High-Speed-Board level communication.
This device comprises: the main control equipment interface, impact damper, serial/deserializer and the high-speed data transmitting-receiving interface that are connected in series successively.
In the time that data send, serial/deserializer, by being converted to serial data from the parallel data of high-speed data transmitting-receiving interface input, is then carried out sending to main control equipment by described main control equipment interface after data balancing to described serial data by impact damper.
In the time of data receiver, impact damper receives the data from main control equipment by main control equipment interface, and described data are carried out to pre-emphasis, then by serial/deserializer, the data after pre-emphasis is converted to parallel data, and receives and dispatches interface output by high-speed data.
Because high fdrequency component mainly appears at rising edge and the falling edge of signal, so impact damper receives after data, the amplitude of rising edge and negative edge is strengthened, improve high fdrequency component, compensate the loss in transmitting procedure, improve the quality of signal.
Because exist and crosstalk in the middle of circuit, the component of crosstalking after pre-emphasis also can be strengthened, and the harm of crosstalking in increasing circuit, so carry out high-pass filtering when signal receives, is carried out data balancing, and minimizing is crosstalked.
When main control equipment sends or receives data, suppose that signal high fdrequency component is 10, noise is 1, and restoring so signal high band signal to noise ratio is 10: 1; If the high boost to signal before record, suppose to be promoted to 20, while transmission again after record, the noise of introducing is 1, is still now the signal to noise ratio of 10: 1, but high fdrequency component has now been raised, when high fdrequency component is decayed, noise is also attenuated, if signal high fdrequency component decay is reverted to original 10, noise will be lowered to 0.5.
Visible, the utility model embodiment realizes the device of High-Speed-Board level communication, utilizes data buffer, can effectively improve message transmission rate and transmission range.And this device has been simplified high speed serialization agreement, has reduced risk, can make message transmission rate expand and be raised to 102Gbps from 622Mbps, logic takies still less.
As shown in Figure 3, be a kind of specific implementation structural drawing of the utility model embodiment device of realizing the communication of High-Speed-Board level.
Wherein, Serial Lite II Two lanes is high-speed transceiver interface, and support flank speed is 625MB/s, can be used as print data stream transmission channel; SerDes interface is outside SerDes chip interface, adopt the common I/0 pin of FPGA, support LVTTL (low voltage transistor logic) and LVCMOS (low pressure complementary metal oxide semiconductor) level, comprise the input of 16bit and the output of 16bit, be used for transmitting various synchronizing signals, handshake, PAR (P0sitive Acknowledgement with Retransmi ssion) protocol signal (Txd, Rxd), selection work can reach 80Mhz chip in full-duplex mode bus interface frequency.
High speed LVDS interface (maximum rate: 1.2Gbps) and internal resource that self-defined SerDes utilizes FPGA to carry, realize the functions such as data output, command transfer, the signal of MBI (multiple bus interface) be synchronous.This self defined interface provides three road high-speed-differential outputs, and the input of two-way high-speed-differential, can adopt parallel clock also can adopt the mode of embedded clock, and embedded clock can improve data bandwidth.
Serial Lite II Two lanes interface and every pair of differential pair of self-defined SerDes interface all need to connect a single pass LVDS impact damper (makes Low Voltage Differential Signal form a buffer cell at a high speed a large amount of differential datas, guarantee data integrity), even if transmission speed is up to 3.125gbps like this, still can guarantee that signal integrity is intact, greatly strengthen the anti-noise jamming ability of signal path.Impact damper can drive the signal on FR4 base plate and cable with flank speed, is best suited for communication facilities, storage and imaging system.
The physical transmission medium of MBI interface can adopt Camera Link standard cable or CAT6 standard cable, guarantees the transmission range of 10m.
Utilize Serial Lite II Two lanes and self-defined SerDes mode to transmit data, flank speed can reach 3.125Gbps.Utilize SerDes interface to realize the functions such as data output, command transfer, the signal of MBI interface be synchronous.Utilize signal equalization technology to realize at transmitting terminal, be referred to as pre-emphasis (pre-emphasis), also can realize at receiving end.
Method and the device of High-Speed-Board level communication that what the embodiment of the present invention provided realize, by transmitting pre-emphasis and receiving equalization function, guaranteeing, under the prerequisite of signal lossless, effectively to have improved transfer rate and transmission range.Adopt at present advanced balancing technique can realize the 10G backboard transmission of 40 inches of (1 meter) distances.
The foregoing is only preferred embodiment of the present utility model, be not limited to the utility model, for a person skilled in the art, the utility model can have various modifications and variations.All within spirit of the present utility model and principle, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection domain of the present utility model.
Claims (8)
1. a device of realizing the communication of High-Speed-Board level, is characterized in that, comprising:
The main control equipment interface, impact damper, serial/deserializer and the high-speed data transmitting-receiving interface that are connected in series successively;
In the time that data send, serial/deserializer, by being converted to serial data from the parallel data of high-speed data transmitting-receiving interface input, is then carried out sending to main control equipment by described main control equipment interface after data balancing to described serial data by impact damper;
In the time of data receiver, impact damper receives the data from main control equipment by main control equipment interface, and described data are carried out to pre-emphasis, then by serial/deserializer, the data after pre-emphasis is converted to parallel data, and receives and dispatches interface output by high-speed data.
2. device according to claim 1, is characterized in that, also comprises: small computer system interface, is serially connected between described impact damper and main control equipment interface.
3. device according to claim 1, is characterized in that, described serial/deserializer is field programmable gate array.
4. device according to claim 3, is characterized in that, described field programmable gate array comprises the input of 16bit and the output of 16bit, for transmitting synchronizing signal, handshake.
5. device according to claim 1, is characterized in that, described impact damper is single pass LVDS impact damper.
6. device according to claim 5, is characterized in that, described high-speed data transmitting-receiving interface is Serial Lite II Two lanes interface.
7. device according to claim 6, is characterized in that, described high-speed data transmitting-receiving interface supports that flank speed is 625MB/s.
8. device according to claim 6, is characterized in that, a single pass LVDS impact damper of every pair of difference docking of described Serial Lite II Two l anes interface.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320656551.4U CN203616749U (en) | 2013-10-23 | 2013-10-23 | Device for realizing high-speed board level communication |
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| CN201320656551.4U CN203616749U (en) | 2013-10-23 | 2013-10-23 | Device for realizing high-speed board level communication |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104297590A (en) * | 2014-09-30 | 2015-01-21 | 东南大学 | Parallel test device based on electric signals |
| CN106301386A (en) * | 2015-05-18 | 2017-01-04 | 华为技术有限公司 | Data save method and deserializer |
| CN107241160A (en) * | 2016-03-28 | 2017-10-10 | 华为技术有限公司 | The method and apparatus for determining parameter |
| WO2017193683A1 (en) * | 2016-05-09 | 2017-11-16 | 浪潮电子信息产业股份有限公司 | Signal enhancement board, and signal enhancement method and system |
| CN107924379A (en) * | 2015-08-26 | 2018-04-17 | 高通股份有限公司 | For being extended to SOUNDWIRE（SOUNDWIRE‑XL）The system and method for the speed detection of cable |
-
2013
- 2013-10-23 CN CN201320656551.4U patent/CN203616749U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104297590A (en) * | 2014-09-30 | 2015-01-21 | 东南大学 | Parallel test device based on electric signals |
| CN106301386A (en) * | 2015-05-18 | 2017-01-04 | 华为技术有限公司 | Data save method and deserializer |
| CN106301386B (en) * | 2015-05-18 | 2019-11-05 | 华为技术有限公司 | Data save method and deserializer |
| CN107924379A (en) * | 2015-08-26 | 2018-04-17 | 高通股份有限公司 | For being extended to SOUNDWIRE（SOUNDWIRE‑XL）The system and method for the speed detection of cable |
| CN107241160A (en) * | 2016-03-28 | 2017-10-10 | 华为技术有限公司 | The method and apparatus for determining parameter |
| WO2017193683A1 (en) * | 2016-05-09 | 2017-11-16 | 浪潮电子信息产业股份有限公司 | Signal enhancement board, and signal enhancement method and system |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140528 Termination date: 20191023 |