WO2008143937A2

WO2008143937A2 - Asymmetric transmit/receive data rate circuit interface

Info

Publication number: WO2008143937A2
Application number: PCT/US2008/006238
Authority: WO
Inventors: Brian S. Leibowitz; Jared Levan Zerbe
Original assignee: Rambus, Inc.
Priority date: 2007-05-17
Filing date: 2008-05-15
Publication date: 2008-11-27
Also published as: WO2008143937A3

Abstract

A system implements asymmetric data transfer between circuit blocks. The asymmetric data rate is between receivers and transmitters of different integrated circuits across a set of channels. In an embodiment, a first circuit or memory controller includes a transmission circuit to transmit data at a first data, rate over a data channel 8 to a reception circuit of a second circuit or a memory 6. The first circuit or memory controller also includes a reception circuit to receive data at a second data rate, different from the first data rate, over a data channel from a transmission circuit of the second circuit or memory. Thus, data is transferred at a greater rate per channel in one direction between circuits compared to the other direction. For example, a data transfer rate for either a read data operation or a write data operation exceeds the transfer rate of the other operation.

Description

ASYMMETRIC TRANSMIT/RECEIVE DATA RATE CIRCUIT INTERFACE

CROSS REFERENCE

[0001] The present application claims the benefit of Application Serial No. 60/930,524, filed May 17, 2007, entitled DATA CIRCUIT INTERFACE WITH ASYMMETRIC TRANSMIT/RECEIVE DATA RATES, the disclosure of which is hereby incorporated herein by reference. BACKGROUND ART

[0002] The performance of conventional digital systems is limited by the transmission interconnection between integrated circuits. In such systems, a transmitter sends data onto a channel by setting a signal parameter of an output signal, such as current or voltage, to one of a plurality of discrete values during each of a succession of intervals referred to herein as data intervals. The data is in turn received by a receiver on the channel . The receiving IC device needs to be able to recognize the discrete values set by the transmitter in the data so it may be used in the receiving IC device.

[0003] The transmitted data typically experiences corruption as it propagates through the channel from the transmitter to the receiver. Such corruption can cause inter-symbol interference

(ISI) and make it more difficult, or impossible, for the receiver to determine the value of the signal parameter during each individual data interval . The corruption which causes ISI may arise from frequency dependent attenuation in the signal path, reflections from impedance discontinuities in the signal path, or other factors. Typically, signal components at higher frequencies are attenuated to a greater degree than signal components at lower frequencies. These problems typically become more significant in high-performance systems where data is transmitted at a high data rate.

[0004] Equalization schemes may be used in high-performance communication links to compensate for all or part of the corruption imposed by the channel and thus maintain an acceptable

i error rate. For example, equalization may include processes for emphasizing or attenuating a selected frequency or frequencies of a signal, often to compensate for frequency-specific attenuation of the signal. Also, error correction schemes can be used to reduce the effective bit error rate. However, equalization and error correction circuitry can increase system complexity, cost, implementation difficulty, power requirements and size. [0005] For example, in a memory interface system that includes a memory controller circuit and several memory circuits, there are one or more channels for data transfer between the controller and one or more memory circuits. These data exchanges are typically for read and write operations. It would be desirable to implement high speed data transmission schemes in such systems in a manner that minimizes circuit complexity while still improving data throughput .

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present technology is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which like reference numerals refer to similar elements including:

[0007] FIG. 1 shows example components in a memory controller system embodiment employing asymmetric data rate transfer technology;

[0008] FIG. 2 shows hypothetical clock and data signals associated with an embodiment of the technology;

[0009] FIG. 3 illustrates hypothetical signals for another embodiment of the technology;

[0010] FIG. 4 illustrates hypothetical clock and data signals associated with another embodiment of a transceiver circuit of the technology;

[0011] FIG. 5 is a memory controller and memory circuit embodiment with equalization circuitry and clock multiplication circuitry; [0012] FIG. 6 illustrates a further memory controller and memory embodiment with equalization circuitry and clock multiplication circuitry;

[0013] FIG. 7 is another memory controller and memory embodiment with equalization circuitry and clock multiplication circuitry; [0014] FIG. 8 is a still further memory interface embodiment with equalization circuitry and clock multiplication circuitry; [0015] FIG. 9 illustrates a memory controller and memory embodiment with error correction encoding/decoding circuit blocks;

[0016] FIG. 10 illustrates another memory controller and memory embodiment with error correction encoding/decoding circuit blocks;

[0017] FIG. 11 is a graphics processing device implementing asymmetric data rate transfer technology;

[0018] FIG. 12 shows communication system components in an integrated circuit block embodiment of the asymmetric communication rate data system technology;

[0019] FIG. 13 is a multiple transmitter and multiple data channel embodiment;

[0020] FIG. 13A is a memory controller embodiment with multiple discrete memories connected by a multi-drop bus;

[0021] FIG. 14A is an example transmission circuit block with a transmitter and equalization circuits suitable for implementation with disclosed embodiments;

[0022] FIG. 14B illustrates a reception circuit block suitable for use with the embodiments described herein; and [0023] FIG. 14C illustrates an example timing circuit formed by a fractional phase lock loop circuit block suitable for use in the disclosed embodiments. DETAILED DESCRIPTION

[0024] A data system 2 according to one embodiment of the asymmetric data rate transfer technology (Fig. 1) includes a first circuit which in this embodiment is a memory controller 4. The system further includes a second circuit which in this embodiment is a memory 6 such as a static random access memory or dynamic random access memory. A set of one or more data channels 8 extend between memory controller 4 and memory 6. In the particular embodiment depicted, the first circuit block or memory controller 4 is formed as one integrated circuit chip and the second circuit block or memory 6 includes one or more integrated circuit chips separate from chip 4. The data channels 8 may include elements commonly used for transmission of signals between chips as, for example, wires or conductors on a circuit panel. Merely by way of example, the memory controller and memory may be parts of a single computer system or other electronic device, and may be disposed in proximity to one another as, for example, within about 10 meters of one another, and the data channels may be less than about 10 meters long. [0025] Memory controller 4 includes a transmitter circuit block 10 or sending means, which is arranged to receive write data 7 to be written into the memory 6 and send output signals along one or more of the channels 8, such output signals having one or more signal parameters which represent particular write data. For example, the particular embodiment shown in Fig. 1 uses a common transmission scheme which is known as 2 -PAM. In this scheme, the transmitter circuit block 10 sends an output signal during a succession of data intervals. The signal ultimately received during a particular data interval has a single parameter, such as current or voltage, which represents a 1 or 0 value for a single bit of the transmitted data. In the particular embodiment of Fig. 1, the output signals from memory controller transmitter circuit block 10 typically are sent as unmodulated or baseband signals along the data channels 8. Stated another way, in this embodiment the output signal is not modulated on a carrier wave. Merely by way of example, each output signal may be a single- ended voltage or current signal sent along an individual conductor of a channel, or may be a differential voltage or current signal sent along a pair of conductors. The transmitter circuit block 10 may incorporate appropriate voltage or current drivers (not shown) for generating these signals.

[0026] Transmitter circuit block 10 includes a transmit equalization circuit 76. The transmit equalization circuit varies the output signal during each data interval depending upon the value of the bit currently being transmitted, as well as the values of the bits transmitted at one or more preceding or succeeding data intervals. The effect of such variation is typically to enhance the high-frequency components in the stream of the output signal relative to the low-frequency components to compensate for high frequency channel loss. Transmit equalization, and various types of transmit equalization circuits, are disclosed, for example, in United States Patent 6,542,555. As set forth in the '555 patent, the transmit equalization circuit may include, for example, a single tap or multi-tap finite impulse response filter. Other forms of transmit equalization circuit can be used.

[0027] The first circuit or memory controller 4 further includes a receiver circuit block 12. The receiver circuit block 12 or receiver means is arranged to sample a signal representing data sent to the memory controller 4 along one or more of the channels 8 , and to convert each such sample into one or more values of read data 9. In the particular example depicted, the receiver circuit block 12 is arranged to sample a signal parameter of the received signal during each data interval of the received signal, and compare a value of the signal parameter to a threshold so as to assign a digital data value to the signal for each data interval. For example, in the particular embodiment of Fig. 1, the received signal is a 2 -PAM signal, and the receiver circuit 12 assigns a 1 or 0 bit value to each data interval depending upon whether the signal parameter, such as the sampled voltage, is above or below the threshold.

[0028] The receiver circuit block 12 further includes a receiver equalization circuit 78. As further discussed below, the receiver equalization circuit 78 is arranged to modify the signal parameter of the received signal during each data interval before such signal parameter is compared to the threshold. The modification varies depending on the data values for signals received during preceding data intervals. Typically, the receive equalization circuit enhances high-frequency components in a stream of received signals. Receive equalization serves to compensate for signal corruption caused by transmission along the data channels. For example, such an equalizer may be a continuous time linear equalizer, a decision feedback equalizer (DFE) , a partial response decision feedback equalizer (PrDFE) , etc. Other forms of receive equalization can be used. [0029] The memory controller further includes a memory controller timing circuit 72, which is arranged to generate a memory controller transmitter clock signal MC_Clk_Tx and supply that signal to transmitter circuit block 10, and to generate a memory controller receiver clock signal MC_Clk_Rx and supply that clock signal to receiver circuit block 12. As discussed further below, the data received by the memory controller has a higher data rate (Rate B, Fig. 1) than the data sent by the memory controller (Rate A, Fig. 1) and MC_Clk_Rx has a higher clock rate than MC_Clk_Tx. In the particular embodiment shown, timing circuit 72 is arranged to accept an external clock signal CIk such as a system clock or reference clock signal and apply different functions Fl (x) and F2 (x) to the external clock signals so as to generate MC_Clk_Tx and MC_Clk_Rx, and to maintain synchronization with certain clock signals used by the second circuit or memory 6. Merely by way of example, timing circuit 72 may include conventional components such as frequency dividers or multipliers, phase-locked or delay-locked loops, and conventional control components for adjusting the operation of these elements in response to stored calibration information or measured conditions such as, for example, phase offset between data intervals of a received data signal and MC_Clk_Rx.

[0030] Additionally, the memory controller optionally includes a control circuit 73 or controller means for generating control signals which control the operating modes of the components in memory controller 4 and memory 6. Thus, control circuit 73 may be arranged to send certain control signals to the memory 6 to control its operations. In the particular example depicted in Fig. 1, the system 2 includes a control instruction channel 70 separate from the data channels 8. In other embodiments, the control instructions may be sent along some or all of the data channels 8 as opposed to or in addition to the control channel and may be sent at a rate different or about equal to the rates for transmission of the read or write data. Whatever mode of transmission is used for the control signals, however, the control signals are distinct from the signals representing data to be read from the memory or written into the memory. Unless otherwise stated, references in this disclosure to "data" in the context of a memory system should be taken as referring to data to be read from the memory or written into the memory, as distinguished from control instructions.

[0031] The control circuit 73 typically includes control logic circuit block (s) (not shown) to actuate the operations required for writing data into the memory and for reading data out of the memory. The control instructions may include the addressing information that may be necessary for accessing certain cells of the memory core to be written or read. Aside from the particular data transfer operating modes of the device, control instructions may also include instructions for test, calibration and/or setup mode(s) for configuration and/or testing of the memory circuit. [0032] The second circuit or memory 6 includes a memory core 3 with cells for storing user data. The memory 6 further includes a memory receiver circuit block 16, which includes a sampling and thresholding circuit similar to that of memory controller receiver circuit block 12 for sampling the signals received from the memory controller along one or more of the data channels 8 and recovering digital values. In this embodiment, the memory receiver circuit block 16 does not include a receive equalizer circuit. The memory 6 further includes a memory transmitter 14, which may be similar to the transmitter circuit block 10 of the memory controller 4 discussed above. In this embodiment, the memory controller transmitter 14 also does not include a transmit equalizer. In this respect, the circuitry of the memory 6 can be simpler than the circuitry of the memory controller 4. [0033] The second circuit or memory 6 also includes a memory timing circuit 74, which in this embodiment is arranged to receive the same external clock signal CIk or reference clock as supplied to the timing circuit of the memory controller circuit 4. Memory timing circuit 74 is arranged to provide a memory transmit clock M_Clk_Tx to memory transmitter 14 and to supply a memory receive clock M_Clk_Rx to the memory receiver 16. The memory timing circuit 74 may include components similar to those discussed above in connection with the memory controller timing circuit 72.

[0034] In the particular embodiment shown, the memory timing circuit 74 derives the memory receive clock signal M_Clk_Rx by applying function F2 (x) to the external clock signal CIk; this may be the same function used to derive the memory controller transmit clock signal MC_Clk_Tx in the timing circuit 72 of the controller 4. Thus, the memory controller 4 receive clock signal may be substantially in synchronism with the memory controller transmit clock signal. Likewise, the memory timing circuit 74 applies function Fl (x) to CIk to derive M_Clk_Tx; this is the same function used to derive MC_Clk_Rx in the memory controller, so that the memory transmit clock signal M_Clk_Tx will be substantially in synchronism with MC_Clk Rx. The memory transmit clock signal M_Clk Tx in this embodiment has a higher clock rate than the memory receive clock signal M_Clk_Rx.

[0035] In Fig. 1, memory transmitter 14 and memory receiver 16 are depicted as connected directly to the memory core 3 for simplicity of illustration. In practice, memory 6 typically includes additional circuitry such as buffers, address decoders and the like, which may be connected between the memory core and the memory transmitter and receiver. This additional circuitry may include components responsive to control instructions, including address instructions, for routing data received by memory receiver 16 to particular memory cells during a writing operation and to select particular memory cells and convey the data from those cells to memory transmitter 14 during a read operation.

[0036] In operation, the control circuit 73 of memory controller 4 actuates the components discussed above to write data into the memory 6 and to read data from the memory. During a write operation, signals representing write data 7 are transmitted by transmitter circuit block 10 of the memory controller 4 and received by memory receiver 16 of the memory 6 at a first data rate A. The data is written into the memory core 3. During a read operation, signals representing data read out of the memory core 3 are transmitted by memory transmitter 14 at a second data rate B. The first and second data rates A and B respectively are different from one another. In this embodiment, the second data rate B is higher than the first data rate A. Unless otherwise specified, a data rate refers to a data rate per channel, i.e., the number of bits per unit time sent represented by the signals sent along a channel. Also, unless otherwise specified, the data rates referred to herein should be understood as instantaneous data rates prevailing on the data channels during the times when signals are being sent, as opposed to average data rates calculated over the entire time of operation of the system, including dwell periods when no data is being sent. [0037] The signals used by the first circuit block or memory controller 4 and by the second circuit block or memory 6 (Fig. 1) are depicted in Fig. 2. Graph of clock signal 32 represents the first circuit or memory controller transmit clock signal MC_Clk_Tx, and also represents the second circuit or memory receive clock signal M_Clk_Rx. In practice, the receive clock signal M_Clk_Rx may be offset in phase from the transmit clock signal MC_Clk_Tx; such offset is not shown in Fig. 2. Likewise, graph of clock signal 34 represents the transmit clock M_Clk_Tx of the second circuit or memory, and also represents the receive clock MC_Clk_Rx of the memory controller. Graph of data signal 36 is a simplified representation of the data signal transmitted by the first circuit or memory controller at the second or lower data rate A in Fig. 1, and also represents the data signal received by the second circuit or memory. The data signal has data intervals I₃₆ corresponding to the intervals of the I₃₂ of the memory controller transmit clock signal 32. Within each data interval the signal parameter of the data signal such as voltage or current has a value representing 0 or a value representing 1. As mentioned above, the transmit equalization process applied in the transmitter circuit block 10 of the memory controller 4 may cause the values representing 0 to differ from one another and may cause the values representing 1 to differ from one another; these variations are omitted in Fig. 2. Graph of data signal 38 represents the data signal sent by the second circuit or memory at a second, higher data rate B in Fig. 1, and thus also represents the data signal received by the first circuit or memory controller 4. The data intervals I₃₈ correspond to intervals I₃₄ of the second circuit or memory transmit clock signal 34. Within each data interval I₃₈ the signal parameter of data signal 38, such as voltage or current, has a value representing 0 or a value representing 1. In this embodiment, both of the data signals are shown using bi-level or 2 -PAM data symbol encoding with either a high or low signal for representing either digital data bit 1 or 0 respectively; the data signal 38 sent from the second circuit or memory has a higher data rate than data signal 36 simply because data signal 38 has shorter data intervals based on a higher clock rate.

[0038] As discussed above, the receiver circuit block 12 of the first circuit or memory controller 4 incorporates a receive equalization circuit 78, whereas the memory receiver 16 of the memory 6 does not include a receive equalization circuit. The receive equalization circuit creates an improved representation of the received signal representing data, and compensates for ISI introduced by the data channel 8. Therefore, receiver circuit block 12 can recover the data from the transmitted signal at an acceptable bit error rate even though the data is transmitted at a high rate, and even though the data is transmitted from the memory without transmit equalization in circuit block of the memory transmitter 14. The memory receiver 16 of the memory need not be capable of receiving data at such a high rate, and accordingly can be less complex while still maintaining an acceptable bit error rate. The use of transmit equalization 76 associated with transmitter circuit block 10 of the memory controller 4 also facilitates achieving an acceptable bit error rate in data transmission to the memory. However, the transmit equalization circuit 76 need not provide the same level of compensation for characteristics of the data channels 8 as the receive equalization circuit 78.

[0039] Stated another way, in this embodiment, the combination of memory transmitter 14, data channels 8, memory controller receiver circuit block 10 and receive equalization circuit 78 which is used for read data provides a data path which is more robust than the data path used for write data, i.e., transmitter circuit block 10 in the memory controller, transmit equalization circuit 76, data path 8 and memory receiver 16 in the memory. Thus, increasing effective data rate transmission in one direction between two points of a channel relative to another direction of data transfer between the two points can be achieved by selective implementation of signal conditioning or recovery circuitry such as the equalization circuits (pre-transmit equalization and/or post -transmit equalization) and/or error correction circuitry as discussed in more detail herein. [0040] The system can provide good performance in many common memory applications. In many applications, data is read from the memory more often than data is written to the memory. For example, program instructions, graphics data such as the data used to display an image on a screen, and other types of data commonly are read more often that they are written. Thus, the higher data rate used in reading data from the memory has a greater effect on overall system performance than the lower data rate used in writing to the memory. The system discussed above with reference to Figs. 1 and 2 also minimizes circuit complexity in the second circuit or memory 6. This can be advantageous because it is frequently easier and less expensive to incorporate elements such as those used in equalization circuitry in the memory controller than in the memory. Moreover, this advantage is even more pronounced where a single memory controller is used with more than one memory. In some cases it may be possible to build a receive equalizer that can better compensate for channel corruption than a transmit equalizer having similar cost or complexity, allowing the read path to operate at higher possible rates than the write path, if all equalization is to be implemented at the memory.

[0041] In the embodiment discussed above with reference to Figs. 1 and 2, the data rate for signals conveying data read from the second circuit or memory is higher than the data rate for signals conveying data being written to the memory. This arrangement can be reversed. Thus, for memory applications where more write operations are performed than read operations, a faster data rate for write operations will present a benefit.

[0042] In other embodiments asymmetric data rate links between circuit blocks may be implemented with or without different clock rates for transmitters and receivers of each circuit as discussed above, by implementing different data symbols in the data signals sent between the transmission block and reception block of each circuit. For example, as illustrated in the FIG. 3, the second circuit includes a transmission circuit block operable for transmitting a data signal 48 using a multi-symbol encoding format, such as a pulse amplitude modulated signal with 4 symbols (e.g., a 4-pulse amplitude modulation scheme known as 4-PAM) . As illustrated in FIG. 3, the four different levels of the signal parameter, such as voltage or current levels, represent four different two-bit data signals 00, 01, 10 and 11. Thus, the single level in a single data interval I₄₈ represents two bits of transmitted data. In this embodiment, the second circuit includes a reception circuit block that receives data signals 46 using a symbol data encoding format that uses only high and low signals to represent 1 and 0 respectively (e.g., a 2-pulse amplitude modulation scheme known as 2-PAM) . In this type of signal, only a single bit is transmitted in any given data window I₄₆. Exemplary transceivers capable of such signal modulation are illustrated in U.S. Patent Application no. 6,396,329. The description of these circuits has been omitted here for purposes of brevity.

[0043] The first circuit coupled with this type of second circuit includes transmitters and receivers with complementary symbol encoding capabilities. Thus, the transmission circuit block of the first circuit would transmit with the same symbol set of the receiver of the second circuit and the reception circuit block of the first circuit will receive with the same symbol set of the transmitter of the second circuit . [0044] Using transmission and reception circuits with different symbol encoding sets, data may be received and transmitted at different rates per channel even when the clocking of the transmitters and receivers of each circuit is the same. As illustrated in FIG. 3, the transmit clock signals 44 and 42 have the same frequency. Thus, signal 48 sent from the second circuit to the first circuit has data intervals I₄₈ whereas signal 46 sent from the first circuit to the second circuit has data intervals I₄₆ of the same duration, but signal 48 has twice the data rate of signal 46. Such a system can offer an advantageous performance, for example, if it is easier or more cost effective to build a 4-PAM receiver in the first circuit than it is to build a 4-PAM receiver in the second circuit. Moreover, the use of the different data symbol sets as discussed above may be combined along with different clocking signals as previously discussed. Such a signaling scheme is illustrated further by the signal graph of FIG. 4, which shows a first circuit receiving and transmitting with different symbol sets and different clocking rates such that different data rates per channel are implemented. [0045] A further embodiment of the technology illustrated in FIG. 5 is similar to the embodiment of FIG. 1 and may include the components or functionality of the embodiment of FIG. 1. However, in this embodiment transmit equalization circuitry 77 is also associated with the circuit block of the memory transmitter 14. Transmit equalization circuitry 77 may be similar to the transmit equalization circuit 76 of the memory controller. Including transmit equalization circuitry in the memory further enhances the path used for read data. In this regard, receive equalization circuitry (not shown) may also be added to the reception circuit block 16 of the memory circuit of this or other embodiments. In embodiments where the write data rate is less than the read data rate, a simple receive equalization circuit of limited capability and limited complexity may be provided in the memory, whereas a more robust receive equalization circuit can be provided in the memory controller such that different data rates are applied.

[0046] In the embodiment of Fig. 5, a timing circuit 80 is implemented in the first circuit or memory controller 4 and not in the second circuit or memory 6. The transmit and receive clock signals are used in the memory controller and are forwarded along clock channels 82 to the memory.

[0047] In the particular example of FIG. 5, the timing circuit 80 utilizes a fractional phase lock loop controlled by a multiplier signal RxTxMuIt. The multiplier signal may be generated by additional control logic blocks (not shown) to control the function of the timing circuit that multiplies the input clock signal to generate an output clock signal at a different rate. In the illustrated example, an input clock signal that may also be the memory controller transmit clock signal MC_Clk_Tx is multiplied to produce the memory controller receive clock signal MC_Clk_Rx. These signals are then forwarded on clock channels 82 to the memory circuit but may be switched to the complementary receive and transmit clock signal inputs as previously discussed so that the transmit clock of the first circuit matches the receive clock of the second circuit and vice- versa. As a result of this forwarding, no timing circuit for generating the transmit clock and receive clock signals is utilized in the memory or second circuit or memory 6. Optionally, the memory controller 4 of FIG. 5, may also include phase interpolators (not shown) to adjust the phase of the memory controller transmit and receive circuits to compensate for phase mismatches due to channel transmission times or other factors. Such circuitry may also optionally be applied to other embodiments described herein.

[0048] In the example embodiment of Fig. 5, a 12.8 GHz clock signal is derived from a 6.4 GHz clock signal by the timing circuit 80. Such exemplary clock signals can be utilized to implement the different data transfer rates per channel of, for example, 12.8 Gbps and 6.4 Gbps respectively. While the embodiments of the application may be implemented with clock or timing circuits that have data rates other than the example rates of the embodiments shown herein, it is preferable to have at least one direction of data flow on the data channel at a high frequency such as a rate in excess of one gigahertz (1 GHz) . The data rate of the other direction of data on the channel may similarly exceed this level but will typically not exceed the other data rate.

[0049] The embodiment of FIG. 6 is like the embodiment of FIG. 5. However, in this example, only a single clock signal is forwarded by a clock channel to the second circuit or memory. A timing circuit 90 of the first circuit or memory controller, which may be implemented with a fixed control input 91 that controls a frequency multiplication of the input clock signal by some fixed value such as an integer (e.g., two), generates a higher clock signal. In this example, the higher one of the transmit clock and receive clock signals is forwarded by channel 82. A timing circuit 92 of the memory divides the frequency (e.g., multiplies by 0.5) the transferred signal by the same fixed amount to generate the other clock signal for the memory circuit. The actual resulting clock rates and asymmetric data rates are again shown for illustrative purposes.

[0050] The embodiment of FIG. 7 is similar to the embodiment of FIG. 6. However, in this embodiment, rather than using a fixed rate multiplier or rate divider in the timing circuits of the controller and the memory, the timing circuits may be controlled to implement different clock multiples of an input clock signal based on a common rate control input signal 101. The timing circuit control input 104 of each of the timing circuits 100, 102 may dynamically alter the rate of the output clock signal of each timing circuit such that each timing circuit can dynamically produce the desired relationship in the resulting clock signals. Thus, in the illustrated embodiment, a timing circuit control input of integer two and an input clock signal of 6.4 GHz (such as the memory controller transmit clock signal MC_Clk_Tx) will result in the transmit clock and receive clock signals of 6.4GHz and 12.8GHz and thus, can be used for implementing the different data rates transmitted between the circuits.

[0051] The embodiment of the controller and memory circuits of FIG. 8, is similar to the embodiment of FIG. 7. However, in this circuit configuration, the higher one of the two clock signals and a timing control signal 101 are input to a timing circuit 102 to dynamically control generation of a lower transmission clock signal. Thus, the timing circuit 102 is an integer divider circuit that divides the input clock signal by the rate control input signal 101. Both the higher clock signal (e.g., MC_Clk_Rx) and the rate control input signal 101 are forwarded to the memory circuit from the memory controller circuit. As a result, the timing circuit blocks 102 of each circuit may include the same general integer divider/multiplier circuit design.

[0052] The embodiment of FIG. 9 includes additional data representation improvement circuitry in the form of error correction circuitry. The error correction circuitry is used for one direction of the data transmission between the first and second circuits. An error correction encoding circuit block 120 is associated with the transmission circuit block 14 of the second circuit or memory 6. A compatible error correction decoding circuit block 122 is associated with the receiver circuit block 12 of the memory controller. Error correction encoding circuit block 120 may be a conventional error correction encoding circuit. Such a circuit typically adds correction bits to the data signal to be transmitted based on the data content of the signal. These extra bits are then decoded on the reception side to check the received data based on the extra bits. Errors in the data signal may be corrected or a signal requesting retransmission of the data signal may be generated by the decoding circuit block 122. The error correction circuitry thus tends to reduce the bit error rate of the read data recovered at the first circuit or memory, and provides a more robust data path for the read data. In the embodiment of Fig. 9, the error correction decoding circuit block 122 is used together with a receive equalization circuit 78. Stated another way, the data representation improvement circuitry associated with the receiver circuit block 12 of the first circuit or memory controller 4 includes both the receive equalization circuit 78 and the error correction decoding circuit block 122. In a variant, the error correction circuitry can be provided without the equalization circuitry.

[0053] Because the error correction encoding circuit 120 of Fig. 9 adds additional bits to the data read from the memory core, the signals sent by the memory transmitter 14 circuit block of the memory will have a bit rate, referred to herein as the "raw" bit rate, higher than the data rate. In the particular example shown in Fig. 9, the data rate is 12.8 Gbps; 12.8 Gbps of data read from memory core 3 is carried by the signals sent by memory transmitter 14. The raw bit rate is 14.4 Gbps. The transmitting circuit 14 of the memory is clocked by a memory raw transmit clock signal M__Clk_TxRaw compatible with the raw bit rate. In the example of Fig. 9, the transmit clock M_Clk_TxRaw has a clock rate equal to the raw bit rate. The sampling and thresholding circuits incorporated in the receiver circuit block 12 of memory- controller 4 are clocked by a memory controller raw receive clock MC_Clk_RxRaw having the same clock rate as M_Clk_TxRaw. [0054] In the embodiment of FIG. 9, timing circuit block 124 of the memory controller is a fractional phase lock loop. For example, one suitable circuit for use as block 124 is illustrated in FIG. 14; this circuit generates an output clock signal having a frequency X* (N/M) from an input clock signal having a frequency X. An input clock signal such as the memory controller receive clock signal (MC_Clk_Rx) may be input to the timing circuit block 124 to derive a clock signal suitable for use as MC_Clk_RxRaw. MC_Clk_RxRaw is forwarded to memory 6, where it is used as M_Clk_TxRaw.

[0055] In the example of FIG. 9, clock signals MC_Clk_Rx and M_Clk_Tx at the lower, actual data rate (12.8 Gbps) used for read data are also provided. These signals may be used, for example, for clocking data out of the memory core 3 and clocking data out of the error correction decoder at the memory controller. In a variant, the control logic (not shown) may turn off the error encoding circuit 120 of the memory and the error decoding circuit of the memory controller. When the error encoding circuitry is off, the clock signal M_Clk_Tx may be used to implement a transmit rate based on that signal while the additional clock signal and clock signal MC_Clk_Rx may regulate timing of data receipt by a receiver of the memory controller of the data from the memory with encoded bits. In a further variant, a memory controller may have control logic which detects whether the memory is or is not equipped with error encoding and selects the appropriate receive clock signal (MC_Clk_RxRaw or MC_Clk_Rx) . [0056] The embodiment shown of FIG. 10 is similar to that of FIG. 9. In the embodiment of Fig. 10 uses an additional timing circuit 124 used in the memory 6. Timing circuit block 124 includes fractional phase lock loop to generate the clock signal M_Clk_TxRaw in the memory circuit from a clock signal forwarded from the memory controller. Relative to the embodiment of FIG. 9, this implementation reduces the number of clock signals forwarded between the circuits but increases the circuit blocks of the memory circuit .

[0057] FIG. 11 depicts a graphics device embodiment that implements the asymmetric data rate transfer technology. Such a device, which, for example, may be a computer graphics card, typically will include a graphics means or graphics processor 200 that controls the formulating, generating, displaying and/or rendering of images using imaging data from the memory. The graphics processor is operatively connected to the memory controller 204. The memory controller 204 is connected to a memory 206 by one or more sets of data paths 208. The memory controller 204 and memory 206 include data transmission and reception circuitry as discussed above. Imaging data, such as pixel information, geometry information or texture information, etc., and/or any other graphics rendering instructions, algorithms or software etc., is accessed by write and/or read data operating modes of the memory controller 204 and memory 206. Operation of the memory controller 204 may be controlled by of the graphics processor 200. Asymmetric data transfer rates may be implemented with any of the transmission circuit blocks and reception circuit blocks as discussed herein, or other variants. In such a device, with implementations of the forms and with circuit elements as previously discussed, a transmission data rate per channel for read operations may be optimized to be different or greater than the transmission data rate per channel for write operations. Alternatively, depending on the desired application of the technology to graphics systems, a transmission data rate per channel for write operations may be optimized to be different or greater than the transmission data rate per channel for read operations.

[0058] The data systems 2 as discussed herein may be part of the integrated circuits of digital processing devices, computers, computer peripherals, graphics processing devices, etc. By way of example, the circuits may be implemented as part of a central processing unit or CPU as commonly employed in a digital computer or may be employed as an intermediary between the CPU and other circuit chips. Thus, circuits as discussed herein can be incorporated in the communication path between a processor such as a CPU and a cache memory. The technology may also be implemented as elements of point-to-point connections according to protocols such as PCI Express, Serial ATA and other protocols. The technology can also be used with bus connections, i.e., arrangements in which the same signal is sent to plural devices connected to the same conductors. In other embodiments, the circuits may be an element of data input or output device controllers or the like, such as a memory controller. [0059] In the memory controller embodiment as previously discussed and illustrated, the memory controller generally acts as the device that sends data to the memory for a writing operation and accepts data back from the memory for a reading operation. Moreover, in examples previously discussed, the memory controller also sends the control instructions for the memory. However, this is not essential. Control instructions may also come from a separate or additional source. These instructions from an additional or separate source may be routed through the memory controller or may go to the memory from the other source without the memory controller acting as an intermediary.

[0060] To accommodate different transfer data rates as discussed herein when implemented with a memory controller/memory circuit (s) embodiment, the memory core of the memory may optionally utilize the higher and lower frequency clock signals (i.e., the transmit clock signal and the receive clock signal) or clock signals having the rates thereof in the actual cell storage and access operations of the memory core. In this event, the memory core ' may be controlled to utilize each different clock rate depending on the mode of operation (e.g., read or write). Alternatively, one of the clock rates may be used, such as the higher clock rate of the transmission clock rates. In such a case and to compensate for a lower receive data rate with the memory receiver 16, a buffer (not shown) may be implemented between the memory receiver 16 and the memory core to buffer incoming data signals until sufficient data has been received so that data may be stored in the cells of the core at the higher clock rate.

[0061] Other configurations of the data rate asymmetry technology may be implemented as illustrated by the following additional examples, which are provided to further assist those skilled in the art with practicing and/or understanding principles of the technology. For example, in FIG. 12, a first integrated circuit block C-I and second integrated circuit block C-2 can be a portion of a common or single integrated circuit or chip or may be two or more chips including such blocks . A receiver and a transmitter of either chip may be implemented as a transceiver as illustrated by the transceiver circuit block 18, 20. Optionally, multiple receivers and transmitters coupled by additional channels may be implemented as illustrated in the example embodiment of FIG. 13. In the embodiment, the different data rates A and B may be implemented with data rate A being greater than data rate B. Either the first circuit or second circuit may be implemented as either a memory controller 4 or a memory 6. Moreover, in some embodiments, multiple data rates may be used such that one or more are different from one or more other rates of the set of channels. For example, another channel or channels of the system may utilize different rates C and D (not shown) for data exchange between memory controller 4 and memory 6 such that C and D may be different from each other as previously discussed and such that C and D are also different from one or both of the rates A and B of other channels of the system.

[0062] As with other embodiments, the channel 8 provides a transmission means for purposes of permitting data communication between the two integrated chips or two circuit blocks. Although a single channel may be used, the transceiver circuit blocks can be coupled by a set of channels, having one or more channels or a data path means for transmission of data signals over some distance. A channel 8 is essentially a medium over which a data signal may traverse and may be one or more traces, wires or other medium to carry the data signal. Multiple channels are illustrated in the embodiment of FIG. 13.

[0063] The transmitters and receivers of the technology may be configured to operate the channel 8 as a unidirectional channel 8-UC in that a trace may carry a data signal in one direction from one circuit block to another. In the case of an implementation of a differential transmitter and differential receiver two or more traces may be used to transfer a data signal .

[0064] As shown in Fig. 13, a channel 8 may be bi-directional in which it carries data signals in two directions back and forth between circuit blocks with a circuit trace or wire or multiple wires in the case of the differential transmitter. Bidirectional channels 8-BC are illustrated in FIGS. 12 and 13. The transfer of data signals over such a bidirectional channel 8-BC may occur in both directions simultaneously or it may alternate intermittently as necessary such that the channel is used for transfer of a signal in only one direction at a time. For example, the data path may carry signals by transferring a data sequence signal from one point to another point and upon completion of the transfer of that signal, a transfer of another data signal in the opposite direction. Such a bidirectional channel 8-BC may also be implemented in a transfer of data where data signals are transmitted on the channel from two directions during a common time interval such that they are concurrently transmitted between two points of a channel or both ends of a channel (e.g., by multiplexing). Optionally, as shown in FIG. 13A, a channel 8 may connect one circuit block C-I-1, such as a memory controller, to multiple other circuit blocks (e.g., C-2-1 and C-2-2) , such as two or more discrete memories, in a multidrop bus configuration. This type of configuration may be applied to any of the embodiments discussed herein. Moreover, the channel 8 may also comprise a point-to-point data path, such as the embodiment illustrated in FIG. 13.

[0065] As previously mentioned, the transmission circuit blocks of the embodiments of the described technology may optionally include an output driver 150 and a multi-tap transmit equalizer 152, such as the circuit illustrated in FIG. 14A. The transmit equalizer may be composed of a transmit pipe 154 and an array of one or more output drivers or sub-drivers 156. Output driver and sub-drivers function collectively to drive an equalized version of a transmit data signal onto the channel.

[0066] Similarly, as previously discussed the reception circuit blocks may optionally include receive or post-transmit equalization circuitry, such as an adaptive equalizing circuit illustrated in FIG. 14B. Such a post-transmit equalization circuit typically includes a thresholder 151, tap weights 153 and equalization logic 157. The circuit is designed to improve the representation of data presented at the input of the thresholder 151 by emphasis or deemphasis of that input signal depending on the frequency or pattern of data previously received at the thresholder 151.

[0067] Optionally, a connection where a channel and circuit block may be joined may include a set of circuit contacts or set of contact pads, such as one or more contact pads (not shown) , that may be useful for implementing a connection between a channel 8 or end of a channel and an input or output of one of the integrated circuits .

[0068] In general, each of the circuits implemented in the asymmetric data rate transfer technology presented herein may be constructed with electrical elements such as traces, capacitors, resistors, transistors, etc. that are based on metal oxide semiconductor (MOS) technology, but may also be implemented using other technology such as bipolar technology or any other technology in which a signal-controlled current flow may be achieved.

[0069] Furthermore, these circuits may be constructed using automated systems that fabricate integrated circuits. For example, the components and systems described may be designed as one or more integrated circuits, or a portion (s) of an integrated circuit, based on design control instructions for doing so with circuit-forming apparatus that controls the fabrication of the blocks of the integrated circuits. The instructions may be in the form of data stored in, for example, a computer-readable medium such as a magnetic tape or an optical or magnetic disk. The design control instructions typically encode data structures or other information describing the circuitry that can be physically created as the blocks of the integrated circuits. Although any appropriate format may be used for such encoding, such data structures are commonly written in Caltech Intermediate Format (CIF) , Calma GDS II Stream Format (GDSII) , or Electronic Design Interchange Format (EDIF) . Those of skill in the art of integrated circuit design can develop such data structures from schematic diagrams of the type detailed above and the corresponding descriptions and encode the data structures on computer readable medium. Those of skill in the art of integrated circuit fabrication can then use such encoded data to fabricate integrated circuits comprising one or more of the circuits described herein.

[0070] In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols are set forth to provide a thorough understanding of the present technology. In some instances, the terminology and symbols may imply specific details that are not required to practice the technology. For example, although the terms "first" and "second" have been used herein, unless otherwise specified, the language is not intended to provide any specified order but merely to assist in explaining elements of the technology. [0071] Moreover, although the technology herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the technology. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the technology. For example, although wired channels are explicitly discussed, wireless channels may also be implemented with the technology such that asynchronous data rate wireless transmissions may be made between chips using wireless transmitters and receivers that operate by, for example, infrared data signals or electromagnetic data signals sent between the circuit blocks of the technology. Similarly, the channels may be implemented with capacitive, inductive and/or optical principles and can use components for such channels, such as the transmitter and receiver technology capable of transmitting data by such channels.

Claims

CLAIMS :

1. A method of operating a memory and memory controller comprising:

(a) transmitting, on a first channel, a signal representing write data from a memory controller to a memory at a first data rate ; and

(b) transmitting, on a second channel, a signal representing read data from the memory to the memory controller at a second data rate different than the first data rate.

2. The method of claim 1 wherein the first channel and the second channel are the same channel .

3. The method of claim 1 further comprising transmitting, on a third channel between the memory and the memory controller, a signal at a third rate that is about equal to one of the first data rate and the second data rate.

4. The method of claim 1 wherein the second data rate is higher than the first data rate.

5. The method of claim 4 wherein the transmitting the signal representing write data and the transmitting the signal representing read data are performed on different channels.

6. The method of claim 5 wherein the transmitting the signal representing write data and the transmitting the signal representing read data is performed concurrently on the same channel .

7. The method of claim 6 wherein the signal representing write data and the signal representing read data are interleaved on the same channel .

8. The method of claim 4 further comprising processing, within the memory controller, the signal representing read data to create an improved representation of the read data.

9. The method of claim 8 wherein the transmitting of the signal representing read data is without pre-processing, in the memory, of the signal representing read data to improve a representation of the read data at the memory controller.

10. The method of claim 8 further comprising preprocessing, in the memory, of the signal representing read data to improve a representation of the second data.

11. The method of claim 8 further comprising preprocessing, in the memory controller, of the signal representing the write data to improve a representation of the write data at the memory.

12. The method of claim 11 wherein the transmitting of the signal representing write data is without processing, in the memory, of the signal representing write data to improve a representation of the write data at the memory.

13. The method of claim 1 wherein the first data rate is higher than the second data rate.

14. The method of claim 13 further comprising processing, within the memory, the signal representing write data to improve a representation of the write data at the memory.

15. The method of claim 14 further comprising preprocessing, in the memory controller, of the signal representing write data to improve a representation of the write data at the memory.

16. An apparatus comprising: a memory circuit; a memory controller circuit; and a plurality of data paths coupled to the memory circuit and the memory controller circuit, wherein the memory circuit transmits read data on at least one path of the plurality of data paths at a first data rate, and wherein the memory controller transmits write data on at least one path of the plurality of data paths at a second data rate, and wherein the first data rate is different than the second data rate.

17. The apparatus as claimed in claim 16 wherein the first data rate is higher than the second data rate.

18. The apparatus of claim 17 wherein the memory circuit comprises a first transmitter and a first timing circuit and the memory controller circuit comprises a second transmitter and a second timing circuit, wherein the first timing circuit generates a first timing signal to regulate transmission with the first transmitter and the second timing circuit generates a second timing signal to regulate transmission with the second transmitter, and wherein the first timing signal and the second timing signal have different rates.

19. The apparatus of claim 18 wherein the memory controller circuit comprises a received signal processing circuit to process a data signal received from the memory circuit to improve the representation of data transmitted in the signal .

20. The apparatus of claim 19 wherein the received signal processing circuit includes at least one component selected from the group consisting of an equalizer circuit and an error correction circuit.

21. The apparatus of claim 20 wherein the equalizer circuit is at least one of a continuous time linear equalizer, a decision feedback equalizer, and a partial response decision feedback equalizer.

22. The apparatus of claim 20 further comprising a graphics processor coupled with the memory controller circuit to process imaging data from the memory circuit .

23. The apparatus of claim 16 wherein the second data rate is higher than the first data rate.

24. The apparatus of claim 23 wherein the memory circuit comprises a first transmitter and a first timing circuit and the memory controller circuit comprises a second transmitter and a second timing circuit, wherein the first timing circuit generates a first timing signal to regulate transmission with the first transmitter and the second timing circuit generates a second timing signal to regulate transmission with the second transmitter, and wherein the first timing signal and the second timing signal have different rates.

25. The apparatus of claim 24 wherein the memory circuit comprises a received signal processing circuit to process a data signal received from the memory controller circuit to improve the signal ' s representation of data transmitted in the signal .

26. The apparatus as claimed in claim 25 wherein the received signal processing circuit includes at least one component selected from the group consisting of equalizer circuits and error correction circuits.

27. The apparatus of claim 16 further comprising: a master clock signal circuit in one of the memory- control circuit and memory circuit and a slave clock signal circuit in the other one of the memory control circuit and memory circuit, wherein the slave clock signal circuit is connected to the master clock signal circuit, wherein one of the clock signal circuits generates a first clock signal at a first clock rate, and wherein the other one of the clock signal circuits generates a second clock signal at a second clock rate that is different from the first clock rate.

28. The apparatus of claim 27 wherein the memory controller circuit includes the master clock signal circuit .

29. The apparatus of claim 16 further comprising a reference clock input and clock circuits in the memory and memory controller, wherein the clock circuits are connected to the reference clock input, wherein one of the clock circuits generates a first clock signal for the first data rate, and wherein the other one of the clock signal circuits generates a second clock signal at a rate that is different from the first clock signal for the second data rate.

30. The apparatus of claim 29 wherein one of the data rates is an integer multiple of the other one of the data rates.

31. The apparatus of claim 16 wherein the memory circuit comprises a first transmitter to transmit a data symbol of a first symbol set, wherein the first data symbol is represented by a first signal pulse, and the memory controller circuit comprises a second transmitter to transmit a second data symbol of a second symbol set, wherein the second data symbol is represented by a second signal pulse, and wherein the first symbol set and the second symbol set have different numbers of symbols.

32. The apparatus of claim 16 wherein the memory controller circuit, memory circuit and data path are disposed on at least one semiconductor chip.

33. The apparatus of claim 16 further comprising an additional memory circuit connected with the memory controller, the memory controller to control transfer of data from the memory controller to the additional memory at the first data rate and to control transfer of data from the additional memory to the memory controller at the second data rate.

34. The apparatus of claim 17 wherein the memory circuit comprises a first transmitter operative to transmit a first data symbol selected from a first symbol set, wherein the first data symbol is represented by a first signal pulse, and the memory controller circuit comprises a second transmitter operative to transmit a second data symbol selected from a second symbol set, wherein the second data symbol is represented by a second signal pulse, wherein the first symbol set and the second symbol set have different numbers of symbols.

35. The apparatus of claim 17 further comprising first and second chips, wherein the memory controller circuit is disposed in the first chip, at least a portion of the memory circuit is disposed in the second chip, and the plurality of data paths extends between the first and second chips.

36. The apparatus of claim 34 wherein the plurality of data paths is less than three meters long.

37. The apparatus of claim 36 wherein the memory controller circuit and memory circuit send the data as unmodulated baseband data .

38. The apparatus of claim 37 wherein the plurality of data paths comprises one of a multi-drop bus and point-to-point channels.

39. A device comprising: a graphics processor to process data for formulating images; a memory to store data for the graphics processor; a memory controller coupled with the graphics processor, the memory controller circuit to control data transfer to and from the memory so that data is transferred to the memory in a write operation at a first data rate and so that data is read from the memory in a read operation at a second data rate higher than the first data rate.

40. The device of claim 39 wherein the memory controller circuit and graphics processor circuit are elements of a single semiconductor chip.

41. The device of claim 39 wherein the data comprises graphics rendering instructions.

42. The device of claim 39 wherein the data comprises imaging data.

43. A memory controller comprising: a controller circuit with a transmitter to send first data on a first data channel for a memory at a first data rate per channel and a receiver to receive second data from a second data channel for the memory at a second data rate per channel different from the first data rate per channel .

44. The memory controller of claim 43 wherein the second data rate per channel is greater than the first data rate per channel .

45. The memory controller of claim 44 wherein one of the data rates is an integer multiple of the other one of the data rates, wherein the integer multiple is an integer other than one.

46. The memory controller of claim 44 further comprising a first equalizer coupled to the receiver to process the second data received by the receiver.

47. The memory controller of claim 46 further comprising a second equalizer coupled to the transmitter to process first data for transmission by the transmitter.

48. The memory controller of claim 47 further comprising an error correction decoder coupled to the first equalizer to process first data received by the receiver.

49. The memory controller of claim 48 further comprising a memory control circuit with control logic to actuate a read or write process of the memory.

50. The memory controller of claim 44 further comprising a first memory timing circuit output to control data transmission rate of the memory at the second data rate per channel .

51. The memory controller of claim 50 further comprising a second memory timing circuit output to control data reception rate of the memory at the first data rate per channel .

52. The memory controller of claim 51 wherein the controller circuit, the transmitter, the receiver, the first memory timing circuit output and the second memory timing circuit output comprise a single semiconductor chip.

53. The memory controller of claim 52 further comprising a set of circuit contact pads to connect a memory circuit .

54. The memory controller of claim 51 wherein the transmitter transmits data along a data channel that is less than about 3 meters long.

55. The memory controller of claim 54 wherein the controller circuit sends the first data as unmodulated baseband data and receives the second data as unmodulated baseband data.

56. The memory controller of claim 55 where the first data channel and the second data channel are the same channel .

57. A memory circuit comprising: a plurality of data storage cells coupled to at least one transmitter and to at least one receiver, wherein the transmitter is structured to send first data on a first data channel at a first data rate per channel and wherein the receiver is structured to receive second data on a second data channel at a second data rate per channel, the second data rate per channel being different from the first data rate per channel .

58. The memory circuit of claim 57 wherein the first data channel and the second data channel are the same channel .

59. The memory circuit of claim 57 wherein the first data rate per channel is greater than the second data rate per channel .

60. The memory circuit of claim 59 further comprising an equalization circuit coupled to the transmitter to process the first data for transmission by the transmitter.

61. The memory circuit of claim 59 further comprising an error correction encoder coupled to the equalization circuit to process first data for transmission by the transmitter.

62. The memory circuit of claim 59 wherein no equalization circuit is in any data path between the receiver and the plurality of data storage cells.

63. The memory circuit of claim 59 further comprising: a transmit clock input; and a receive clock input, wherein the transmit clock input is coupled to a first timing circuit having a first output clock rate and the receive clock input is coupled to a second timing circuit having a second output clock rate that is different from the first output clock rate.

64. The memory circuit of claim 59 wherein the plurality of data storage cells, the at least one transmitter circuit block and the at least one receiver comprise a single semiconductor chip.

65. The memory circuit of claim 59 wherein the memory circuit sends the first data as unmodulated baseband data and receives the second data as unmodulated baseband data.

66. The memory circuit of claim 65 wherein the plurality of data storage cells comprises dynamic random access memory cells.

67. An information-bearing medium having computer-readable information thereon, the computer-readable information to control a circuit-forming apparatus to form a block of an integrated circuit including a memory controller or memory, the computer- readable information comprising: instructions to form at least one transmitter circuit to transmit first data at a first data rate; and instructions to form at least one receiver circuit to receive second data at a second data rate different than the first data rate.

68. The information-bearing medium of claim 67 further comprising instructions to form at least one equalization circuit coupled to the at least one transmitter circuit .

69. The information-bearing medium of claim 68 further comprising instructions to form at least one equalization circuit coupled to the receiver circuit.

70. The information-bearing medium of claim 68 wherein the first data rate is greater than the second data rate.

71. The information-bearing medium of claim 68 wherein the second data rate is greater than the first data rate.

72. The information-bearing medium of claim 67 further comprising instructions to form at least one equalization circuit coupled to the receiver circuit .

73. The information-bearing medium of claim 72 wherein the second data rate is greater than the first data rate.

74. The information-bearing medium of claim 72 further comprising instructions to form at least one memory controller circuit including logic gates that comprise a data read and a data write control procedure.

75. The information-bearing medium of claim 67 further comprising instructions to form at least one error correction decoding circuit coupled to the receiver circuit .

76. The information-bearing medium of claim 67 further comprising instructions to form at least one error correction encoding circuit coupled to the transmitter circuit .

77. A set of signal outputs between a first integrated circuit block and second integrated circuit block coupled together, comprising: a first signal component for a data channel having one of a plurality of discrete values for each one of a series of data intervals, the plurality of discrete values transmitted over a first time interval on the data channel and comprising a first data rate output from the first integrated circuit block; and a second signal component for the data channel having one of a plurality of discrete values for each one of a series of data intervals, the plurality of discrete values transmitted over a second time interval on the data channel and representing a second data rate from the second integrated circuit block, the second data rate different from the first data rate.

78. The set of signal outputs of claim 77 wherein the first signal component and the second signal component each comprise binary symbol encoded data.

79. The set of signal outputs of claim 77 wherein one of the first signal component and the second signal component comprises symbol encoded data having a number of symbols that exceeds two.

80. The set of signal outputs of claim 77 wherein the first signal component and the second signal component are on the data channel concurrently.

81. The set of signal outputs of claim 77 wherein the first signal component and the second signal component are on the data channel in succession.

82. The set of signal outputs of claim 77 wherein the first signal component and the second signal component are unmodulated baseband data.

83. A memory system comprising: a memory including a first transmitter coupled to a first data channel, the first transmitter having a first data transmission rate on the first data channel; and a memory controller including a second transmitter coupled to a second data channel, the second transmitter having a second data transmission rate on the second data channel, wherein the first data transmission rate is different from the second data transmission rate.

84. The memory system of claim 83 wherein the first data channel and the second data channel are the same channel .

85. The memory system of claim 83 wherein the first data transmission rate is greater than the second data transmission rate .

86. The memory system of claim 85 wherein the memory includes a first receiver coupled to the second transmitter by a data channel, the first receiver having a data transmission rate substantially equal to the second data transmission rate.

87. The memory system of claim 86 wherein the memory controller includes a second receiver coupled to the first transmitter by a data channel, the second receiver having a data transmission rate substantially equal to the first data transmission rate.

88. The memory system of claim 87 wherein the memory controller comprises an equalization circuit coupled to the second receiver.

89. The memory system of claim 88 wherein the memory comprises an equalization circuit coupled to the first transmitter.

90. The memory system of claim 89 wherein the memory controller comprises an equalization circuit coupled to the second transmitter.

91. The memory system of claim 90 wherein the memory comprises circuit traces between the first receiver and cells of the memory without an equalization circuit.

92. The memory system of claim 91 wherein the first transmitter, second transmitter, first receiver and second receiver are jointly coupled by at least one data channel.

93. The memory system of claim 92 wherein the memory comprises a first additional transmitter and first additional receiver and wherein the memory controller comprises a second additional transmitter and second additional receiver.

94. The memory system of claim 93 wherein the first additional transmitter, second additional transmitter, first additional receiver and second additional receiver are jointly coupled by at least one additional data channel.

95. The memory system of claim 94 wherein the memory comprises a dynamic random access memory.

96. The memory system of claim 95 further comprising a graphics processing device.

97. The memory system of claim 95 further comprising a computer.

98. The memory system of claim 93 wherein the first transmitter and second transmitter are structured to transmit signals intermittently on the at least one data channel.

99. The memory system of claim 93 wherein the first transmitter and second transmitter are structured to transmit signals concurrently on the at least one data channel.

100. An apparatus comprising: a data path, data storage means for storing data and for transmitting first data on the data path at a first data transmission rate per channel , and controller means for controlling the data storage means and for transmitting second data on the data path at a second data transmission rate per channel, wherein the second data transmission rate is different from the first data transmission rate.

101. The apparatus of claim 100 wherein the first data transmission rate per channel is greater than the second data rate per channel .

102. The apparatus of claim 101 wherein the controlling the data storage means comprises a write data operation and a read data operation.

103. The apparatus of claim 102 wherein the controller means further comprises means for improving the representation of data received by the controller means.

104. The apparatus of claim 103 wherein the means for improving is a device selected from a group consisting of means for equalizing signal data and means for error correcting signal data .

105. The apparatus of claim 104 wherein the controller means comprises first timing means for regulating the transmission of the controller means at the first data rate per channel; and wherein the data storage means comprises second timing means for regulating the transmission of the data storage means at the second data rate per channel; and wherein the first timing means and the second timing means have different clock rates .

106. The apparatus of claim 105 further comprising graphics means for processing imaging data from the storage means to formulate images .

107. The apparatus of claim 105 wherein the controller means and data storage means comprise a single semiconductor chip.

108. The apparatus of claim 105 wherein the data path is less than about 3 meters long.

109. The apparatus of claim 105 wherein the controller means further comprises means for sending the second data as unmodulated baseband data on the data path, and wherein the data storage means further comprises means for sending the first data as unmodulated baseband data on the data path.

110. The apparatus of claim 100 wherein the data storage means comprises a dynamic random access memory.

111. An integrated circuit comprising: a data path set coupling a first circuit and a second circuit, the first circuit including a transmission block to transmit a write data signal at a first data rate per channel to the second circuit on a first channel, the second circuit including a transmission block to transmit a read data signal at a second data rate per channel to the first circuit on a second channel, such that the first data rate per channel and second data rate per channel are different.

112. The integrated circuit of claim 111 wherein the second data transmission rate per channel is greater than the first data rate per channel .

113. The integrated circuit of claim 112 wherein the first circuit includes a reception block to receive the read data signal at the second data rate per channel.

114. The integrated circuit of claim 113 wherein the second circuit includes a reception block to receive the write data signal at the first data rate per channel .

115. The integrated circuit of claim 114 wherein the first circuit includes a post-transmit equalization block coupled with the reception block of the first circuit to process the read data signal .

116. The integrated circuit of claim 115 wherein the first circuit includes a pre-transmit equalization block coupled with the transmission block of the first circuit to process the write data signals.

117. The integrated circuit of claim 116 wherein the second circuit includes a pre-transmit equalization block coupled with the transmission block of the second circuit to process the write data signals.

118. The integrated circuit of claim 117 wherein the first circuit includes an error correction decoding block coupled with the reception block of the second circuit and the second circuit includes an error correction encoding block coupled with the reception block of the second circuit.

119. The integrated circuit of claim 118 wherein the first circuit and second circuit comprise a single semiconductor chip.

120. The integrated circuit of claim 118 wherein the data path set comprises at least one data channel connecting the first circuit and second circuit, the data channel being less than about 3 meters long.

121. The integrated circuit of claim 120 wherein the transmission blocks of the first circuit and the second circuit transmit data of the data signals as unmodulated baseband data.

122. The integrated circuit of claim 120 wherein the first circuit comprises a transmission clock block having a first clock rate and a reception clock block having a second clock rate, the second clock rate being different from the first clock rate.

123. The integrated circuit of claim 111 wherein the first circuit is a memory input/output controller and the second circuit is a DRAM.

124. The integrated circuit of claim 122 wherein the first channel and the second channel are the same channel .